JPH0225932A - Data processor - Google Patents

Abstract

PURPOSE:To improve the data processing efficiency by calculating a source address at an address addition part of an address calculation stage and replacing the stack pointer of the address calculation stage to obtain a destination address. CONSTITUTION:The operand addresses 212 and 213 are calculated at an address addition part and the stack pointer of an address calculation stage 203 is replaced at the stage 203 when the push and push A instructions are processed. Then the value of the stack pointer is transferred synchronously with the flow of a pipeline. Thus the pipeline processing efficiency is improved without producing the conflict of the stack pointer at the stage 203 among the instructions produced after the push and push A instructions. Then the performance of a data processor is improved since a push instruction can be carried out in a single step at the minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a data processing device that achieves high processing performance through an advanced pipeline processing mechanism.

[Conventional technology]

FIG. 33 is a block diagram showing the configuration of a data processing device that performs conventional pipeline processing, in which 202 is an instruction decode stage, 203 is an address calculation stage, 204 is an operand fetch stage, 205 is an execution stage,
60 is a stack pointer.

Furthermore, in the execution stage 205, store processing and data calculation processing can be performed in parallel, and it is possible to start processing the next instruction without waiting for the end of store processing.

Next, the operation will be explained. The push command appears to be
This is an operand instruction that pushes the source operand written in the instruction onto the stack. When pushing to the stack, the value obtained by decrementing the value of the stack pointer by the size of the operand specifies the destination address, and the source operand is written there.

In the case of a push instruction, there are two operands: a source operand written in the instruction and a destination operand at the top of the stack. Conventionally, the source operand is written in the address calculation stage 203 and the destination operand is written in the execution stage 205. I was calculating.

FIG. 34 is a flowchart showing the operation of each stage when the source operand of a push instruction is in memory.

In the address calculation stage 203, a source address is calculated based on the addressing mode in the push command (step 1).

Next, in the operand fetch stage 204, step l
Data is fetched from the address indicated by the address calculated in (step 2).

Next, in the execution stage 205, the destination address (stack top) is set in the stack pointer 60 by decrementing the stack pointer by the size of the operand (step 3a).

Next, the decremented value of the stack pointer is written to the address register and the fetched source operand is written to the data register (step 3b).

The value of the data register is written to the address indicated by the address register (step 3c).

The flow of only push instructions is like this, but if instructions are flown by pipeline processing, ideally, once the address calculation in step 1 is finished and the address calculation stage is available, the address calculation for the next instruction will start. is executed immediately. In this way, if the most efficient pipeline processing is performed, each stage is always processing an instruction, and the processing time at the execution stage determines the execution time of the instruction.

However, the pipeline does not always flow smoothly, and there are several causes that reduce efficiency.One of them is the problem that the speed is limited at the slowest stage. The minimum time required to process one stage is 2 clocks.Here, even if the execution ends in the execution stage or 2 clocks,
If the address calculation stage takes four clocks, the execution time of the instruction will be four clocks. Therefore, it is desirable to equalize the number of clocks for instruction execution in each stage and focus on reducing the number of clocks at the stage with the largest number of clocks.

Another problem is that there is a resource conflict at each stage, so the conflict at the address calculation stage, which is particularly relevant to the present invention, will be explained. In the address calculation stage 203, each instruction calculates an address, but a preceding instruction in the pipeline may overwrite the value of a register or memory referenced during execution of this calculation.

In this case, the result of the address calculation that has already been performed will be incorrect. In order to produce correct results even when such a resource conflict occurs, if there is a possibility that the preceding instruction will rewrite the necessary resources, do not calculate the address until the preceding instruction finishes processing. Otherwise, if the referenced resource is rewritten after performing address calculation, the address calculation must be redone.

The problem when executing the push instruction shown in Figure 34 is that until the execution of this push instruction is finished and the value of the stack pointer is rewritten, the stack pointer will cause a conflict, so later instructions will use the stack when calculating the address. The pointer value cannot be referenced. Therefore, if the next instruction after a push instruction refers to stack boiling in the address calculation stage, the total number of clocks in the address calculation stage, operand fetch stage, and execution stage after the push instruction ends and until the next instruction ends. is required. Also, in order to calculate the destination address in the execution stage, the execution stage
This means that the push command takes at least four clocks.

There is a push eight command which is similar to the push command.
In this instruction, the source address is specified as the source operand, there is no "fetching data from memory in the operand fetch stage 204" in step 2 in FIG.
will be forwarded to. Other than that, it is the same as the push instruction,
have the same problem.

[Problem to be solved by the invention]

In this way, in conventional data processing devices, the value of the stack pointer is updated during processing at the execution stage, so
The execution time of the push instruction increases, and there is a possibility that stack pointer conflicts may occur in address calculations for instructions after the push instruction, which hinders speeding up.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a data processing device that can execute push instructions at high speed and that does not cause stack pointer conflicts in instructions after the push instruction.

(Means for Solving the Problems) The data processing device of the present invention provides a working stack pointer in a stage after the address calculation stage in the pipeline, so that the stack pointer in the address calculation stage is independent of the address addition section. The stack pointer can be incremented or decremented, and the value of this stack pointer is transferred to the stack pointer of each stage in synchronization with the flow of instructions in the vibe line.

[Operation] The data processing device according to the present invention calculates the source address in the address addition section of the address calculation stage, and obtains the destination address by updating the stack pointer of the address calculation stage.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

(1) “Instruction format of the data processing device of the present invention”
The instructions of the data processing device of the present invention have a variable length in units of 16 bits, and instructions with an odd number of bytes are not used.

The data processing device of the present invention has an instruction format system specially devised for the purpose of shortening high-frequency instructions. For example, for 2-operand instructions, there is a general format that basically has a configuration of "4 bytes + extension" and all addressing modes can be used, and a general format in which only frequently used instructions and addressing modes can be used. There are two abbreviated formats.

The meanings of the symbols appearing in the instruction format of the data processing device of the present invention are as follows.

: Part where operation code is entered #; Part where literal or immediate value is entered Ea: Part that specifies the operand in 8 mini 8-bit addressing mode Sh: Part that specifies the operand in 6-bit abbreviated addressing mode Rn: Register In the partial format in which the upper operand is specified by a register number, as shown in FIG. 3, the right side is the LSB side and the higher address. address N and address N
The instruction format cannot be determined without looking at the +1 2 bytes, but this is based on the assumption that instructions are always fetched and decoded in units of 16 bits (2 bytes), as mentioned above. This is because

In the data processing apparatus of the present invention, in any format, the extended part of Ea or sh of each operand is always located immediately after the halfword containing the basic part of Ea or sh. This overrides any immediate data or extensions of the instruction implicitly specified by the instruction. Therefore, 4
For instructions larger than a byte, the operation code of the instruction may be divided by the extension part of Ea.

Further, as will be described later, even when an extension part is added to the extension part of Ea in the multi-stage indirect mode, that part is given priority over the next instruction operation code. For example, the first
Contains fial in halfword and E in second halfword
Consider the case of a 6-byte instruction including a2 and up to the third halfword. Since the multi-stage indirect mode is used for Eal, assuming that the multi-stage indirect mode extension part is attached in addition to the normal extension part, the actual instruction bit pattern is the first bit pattern of the instruction.
Halfword (contains the base of Eal) I Extension of Eal, multi-indirect mode extension of Eal, second halfword of instruction (contains base of Ea2) + extension of Eal, third halfword of instruction The order is as follows.

(1,1) r Shortened Two-Operand Instruction" FIGS. 4 to 7 are schematic diagrams showing the shortened format of a two-operand instruction.

FIG. 4 is a schematic diagram showing the format of an operation instruction between memory registers. This format includes L-format, where the source operand side is memory, and S-format, where the destination operand side is memory.
There is a t.

In L-format, sh represents a source operand designation field, Rn represents a destination operand register designation field, and RR designates the sh operand size. The size of the destination operand located on the register is fixed at 32 bits. Sign extension is performed when the size of the register side and the memory side are different and the size of the source side is small.

In the S-format, sh represents a destination operand designation field, Rn represents a source operand register designation field, and RR represents sh operand size designation. The size of the source operand located on the register is fixed at 32 bits. If the size of the register side and the memory side are different and the size of the source side is large, the overflow portion is truncated and an overflow check is performed.

FIG. 5 is a schematic diagram showing the format (R-format) of an inter-register operation instruction. Rn is a destination register designation field, and Rm is a source register designation field. The operand size is only 32 bits.

Figure 6 shows the format of literal-memory operation instructions (
FIG. 2 is a schematic diagram showing a low format. The space between is the destination operand size specification field, 1l.
lll is a literal source operand specification field, and sh is a destination operand specification field.

Figure 7 shows the format of an immediate-memory operation instruction (1-
FIG. sh is the operand size specification field (common for source and destination), and sh is the destination operand specification field. The size of the immediate value of [-format is 8.16.32 bits, which is the same as the size of the destination operand, and zero extension and sign extension are not performed.

(1, 2) r-ship type 1-operand instruction” Figure 8 shows the general format of the l-operand instruction (Gl-forma
It is a schematic diagram showing t). MM is a field specifying the operand size. Some Glformat instructions have extensions in addition to the Ha extension. There are also orders not to use goods.

(1, 3) r-Ship Type 2-Operand Instruction" FIGS. 9 to 11 are schematic diagrams showing the general format of the 2-operand instruction. This formant includes instructions that have a maximum of two operands in general addressing mode specified by 8 bits. The total number of operands itself may be three or more.

FIG. 9 is a schematic diagram showing the format (G-format) of an instruction whose first operand requires memory reading. EaM is the specified field of the destination operand, goods is the specified field of the destination operand size, and F! , aR is a source operand specification field, and RR is a source operand size specification field. In some G-format instructions, Ea
There are extensions other than those of M or EaR.

FIG. 10 is a schematic diagram showing the format (E-format) of an instruction whose first operand is an 8-bit immediate value.

EaM is a destination operand specification field, Open is a destination operand size specification field, and . . . is a source operand value.

Although E-format and I-format are similar in function, they are very different in terms of way of thinking. Specifically, E-format only has two operands.
It is a derivative of G-format, and the source operand size is fixed at 8 bits, and the destination operand size can be selected from 8/16/32 bits. That is, the E-format assumes operations between different sizes, and the 8-bit source operand is zero-extended or sign-extended to match the size of the destination operand. On the other hand, I-format is a shortened form of an immediate value pattern that is frequently used especially in transfer instructions and comparison instructions, and the size of the source operand and destination operand are equal.

FIG. 11 is a schematic diagram showing the format (GA-format) of an instruction whose first operand is only address calculation. Ea- is a destination operand designation field, 4 is a destination operand size designation field, and Ea8 is a source operand designation field. The execution address calculation result itself is used as the source operand.

FIG. 12 is a schematic diagram showing the format of a short branch instruction. cccc is a branch condition specification field, and disp:8 is a displacement specification field with respect to the jump destination. In the data processing device of the present invention, when specifying a displacement with 8 bits, the specified value in the bit pattern is doubled. Let it be a displacement value.

(1, 4) r Addressing Mode There are two methods for specifying the addressing mode of the data processing apparatus of the present invention: an abbreviated form in which the addressing mode is specified using 6 bits including registers, and a general form in which the addressing mode is specified using 8 bits.

If an undefined addressing mode is specified, or if a semantically inappropriate combination of addressing modes is specified, a reserved instruction exception will occur in the same way as when an undefined instruction is executed. , exception handling is triggered.

This applies when the destination is in immediate mode, or when immediate mode is used in the addressing mode specification field that should involve address calculation.

The meanings of the symbols used in the format diagram are as follows.

Rn: Register specification mem HA: Memory contents of the address indicated by EA (Sh) Specification method in 76-bit abbreviated addressing mode (Ha): Specification method in 8-bit general addressing mode The dashed line in the format diagram The enclosed area indicates the extension.

(1, 4, 1) r Basic Addressing Mode” The data processing device of the present invention supports various addressing modes. Among these, the basic addressing modes supported by the data processing device of the present invention include register direct mode, register indirect mode, register relative indirect mode, immediate mode, absolute mode, PC (program counter) relative indirect mode, and stack pop. mode and stack push mode.

In register direct mode, the contents of the register are used as operands. A schematic diagram of the format is shown in FIG.

Rn indicates the number of a general-purpose register.

In register indirect mode, the operand is the contents of the memory whose address is the contents of the register. A schematic diagram of the formant is shown in FIG. Rn indicates the number of a general-purpose register.

In register relative indirect mode, the displacement value is 1.
There are two types depending on whether it is 6 bits or 32 bits. 16 bits or 32 bits for register contents, respectively.
The operand is the contents of the memory whose address is the value plus the bit displacement value. A schematic diagram of the format is shown in FIG. 15, where Rn indicates the number of the general-purpose register. disp:16 and disp:32 each indicate a 16-bit displacement value or a 32-bit displacement value. Displacement values are treated as signed.

In the immediate mode, the bit pattern specified in the instruction code is treated as a binary number and used as an operand. A schematic diagram of the format is shown in FIG.

imm-data indicates an immediate value. The size of imm-data is specified in the instruction as the operand size.

In absolute mode, the address value is indicated by 16 bits or 32
There are two types depending on whether it is indicated by a bit. Each operand is the contents of the memory whose address is a 16-bit or 32-bit bit pattern specified in the instruction code. A schematic diagram of the format is shown in Figure 17, a.
bs:16 and abs:32 indicate a 16-bit or 32-bit address value, respectively.

abs: When an address is indicated by 16, the specified address value is sign-extended to 32 bits.

11c relative indirect mode has a displacement value of 16
There are two types depending on whether it is bit or 32 bit. Each operand is the contents of the memory whose address is the value obtained by adding a 16-bit or 32-bit displacement value to the contents of the program counter.

A schematic diagram of the format is shown in FIG. disp:
16 and disp:32 each indicate a 16-bit displacement value or a 32-bit displacement value. Displacement values are treated as signed. In PC relative indirect mode, the referenced program counter value is the start address of the instruction containing the operand. When the value of the program counter is referenced in the multi-stage indirect addressing mode, the first address of the instruction is similarly used as the PC-relative reference value.

The stack pop mode uses the contents of the memory whose address is the contents of the stack pointer (SP) as the operand.

After accessing the operand, increment the stack pointer by the operand size.

For example, when handling 32-bit data, SP is updated (incremented) by +4 after operand access. It is also possible to specify stack pop mode for operands of size B and H, each with SP +1.
It is updated (incremented) by +2. A schematic diagram of the format is shown in FIG. A reserved instruction exception is generated for operands for which the stack pop mode has no meaning.

Specifically, the reserved instruction exception is the stack pop mode specification for the write operand and read-modify-write operand.

In stack push mode, the operand is the contents of the memory whose address is the contents obtained by decrementing the contents of the stack pointer by the operand size. In stack push mode, the stack pointer is decremented before operand access. For example, when handling 32-bit data, SP is updated (decremented) by -4 before operand access. It is also possible to specify stack push mode for operands of size B, )(, and SP is updated (decremented) by -1 and -2, respectively. A schematic diagram of the format is shown in FIG.

For operands for which the stack push mode has no meaning, a reserved instruction exception is generated. Specifically, reserved instruction exceptions include the read operand,
This is a stack push mode specification for the read-modify-write operand.

(1, 4, 2) Multi-stage indirect addressing mode No matter how complex addressing is, it is basically broken down into a combination of addition and indirect references. Therefore, if addition and indirect reference operations are provided as addressing primitives and can be combined arbitrarily, any complex addressing mode can be realized. The multi-stage indirect addressing mode of the data processing device of the present invention is an addressing mode based on this idea. Complex addressing modes are particularly useful for inter-module data references or AI (artificial intelligence) language processing systems.

When specifying the multi-stage indirect addressing mode, the basic addressing mode specification field specifies one of three types of specification methods: register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute-based multi-stage indirect mode.

The register-based multi-stage indirect mode is an addressing mode in which the value of a register is used as the base value for multi-stage indirect addressing to be extended. A schematic diagram of the format is shown in FIG. Rn indicates the number of a general-purpose register.

The PC-based multi-stage indirect mode is an addressing mode in which the value of the program counter is used as the base value for multi-stage indirect addressing. The second schematic diagram of the format
Shown in Figure 2.

The absolute base multi-stage indirect mode is an addressing mode that uses zero as the base value of extended multi-stage indirect addressing. A schematic diagram of the format is shown in FIG.

The multi-stage indirect mode specification field to be expanded has a unit of 16 bits, and this is repeated any number of times.

One-stage multi-stage indirect mode allows displacement addition and index register scaling (Xi,
2. X4. X8) and performs indirect reference to memory. A schematic diagram of the format of the multi-stage indirect mode is shown in FIG. Each field has the meaning shown below.

E・0: Continuation of multi-stage indirect mode E=1 End of near address calculation tmp ==> address of opera
nd■=0: No memory indirect reference tmp + disp + Rx * 5
cale ==> tmp1=1: Memory indirect reference mem tip + disp + Rx
Rate 5cale ==>tmpM=0: <
Rx> is used as the index: Special index <Rx>=O Do not add the index value (Rx=O) <Rx>・1 Use the program counter as the index value (Rx=PC) <Rx>=2~ reserved 0.0 7 4-bit field d in multi-stage indirect mode
The value of 4 is multiplied by 4 to create a displacement value, and this is added. d4 is treated as signed, and is always multiplied by 4 regardless of the operand size. D・1: Specified in the extension part of multi-stage indirect mode. d 1
spx (16/32 bits) is the displacement value, and the size of the extension to which this is added is specified in the d4 field. d4=ooo1 dispx is 16 bits d4□0
010 dispx is 32 bits Xx: index scale (scale=1/2/4/8) x2. x4. When x B is scaled, the intermediate value (
An undefined value is entered as t+*p). Although the effective address obtained by this multi-stage indirect mode is an unpredictable value, no exceptions occur. Do not specify scaling for the program counter.

Variations of instruction formats in the multi-stage indirect mode are shown in FIGS. 25 and 26.

FIG. 25 shows variations on whether the multi-stage indirect mode continues or ends.

FIG. 26 shows variations in displacement size.

If a multi-stage indirect mode with an arbitrary number of stages can be used, there is no need for the compiler to differentiate between cases based on the number of stages, which has the advantage of reducing the burden on the compiler. This is because even if the frequency of multiple indirect references is very low, the compiler must always be able to generate correct code. Therefore, any number of stages is possible in the format.

(1, 5) r Exception Handling” The data processing device of the present invention has abundant exception handling functions to reduce the software load. In the data processing device of the present invention, exception handling is re-execution of instruction processing (exception).
They are divided into three types and named: , those that complete instruction processing (traps), and interrupts. Furthermore, in the data processing apparatus of the present invention, these three types of exception handling and system failure are collectively referred to as EIT.

(2) "Configuration of Functional Blocks" FIG. 1 is a block diagram showing the configuration of the data processing device of the present invention.

Functionally, the inside of the data processing device of the present invention can be roughly divided into an instruction fetch unit 101. Instruction decoding unit 102, P
C calculation section 103. Operand address calculation unit 104゜Micro ROM unit 105. Data calculation unit 106. It is divided into an external bus interface section 107.

In addition, in FIG. 1, an address output circuit 108 for outputting an address to the outside of the CPU, and a data input/output circuit 109 for inputting and outputting data to and from the outside of the CPU are shown separately from other functional blocks.

(2, 1) 'Instruction fetch unit' The instruction fetch unit 101 includes a branch buffer, an instruction queue 301 and its control unit, and determines the address of the next instruction to be fetched and transfers it to the branch buffer or CP.
u Fetch instructions from external memory. It also registers instructions to the branch buffer.

Since the branch buffer is small, it operates as a selective cache. The details of the operation of the branch buffer are described in detail in Japanese Patent Application No. 61-202041.

The address of the next instruction to be fetched is stored in the instruction queue 30.
It is calculated by a dedicated counter as the address of the instruction to be input into the address number 1. When a branch or jump occurs, the address of a new instruction is transferred from the PC calculation unit 103 or the data calculation unit 106.

When fetching an instruction from a memory external to the CPU, the address of the instruction to be fetched is sent from the address output circuit 108 to the CPU via the external bus interface unit 107.
The instruction code is output from the U and fetched from the data input/output circuit 109. Then, among the buffered instruction codes, the instruction code to be decoded next is output to the instruction decoding unit 102.

(2, 2) r Instruction Decoding Unit” The instruction decoding unit 102 basically decodes instruction codes in units of 16 bits (halfwords). This block includes an FHW decoder that decodes the operation code contained in the first halfword, a second . It includes an NFHW decoder that decodes the operation code included in the third halfword, and an addressing mode decoder that decodes the addressing mode. These FIIW decoder, N P II W decoder, and addressing mode decoder are collectively referred to as a first decoder 303 .

A second decoder 305 further decodes the output of the Fl+- decoder or the NFHW decoder to calculate the entry address of the micro ROM, a branch prediction mechanism that predicts the branch of a conditional branch instruction, and a bib line conflict check when calculating the operand address. Also included is an address calculation conflict checking mechanism.

The instruction decode unit 102 reads the instruction code input from the instruction fetch unit 101 every two clocks (one step).
~Decode 6 bytes at a time. Among the decoding results, information regarding the calculation in the data calculation unit 106 is stored in the micro ROM.
Information related to the operand address calculation is output to the operand address calculation section 104, and information related to the PC calculation is output to the PC calculation section 103.

(2, 3) ``Micro ROM section'' The micro ROM section 105 mainly includes a data calculation section 106.
It includes a micro ROM, a micro sequencer, a micro instruction decoder, etc. in which a micro program for controlling the micro program is stored. A microinstruction is read from the microROM once every two clocks (l step). In addition to the sequence processing indicated by the microprogram, the microsequencer accepts processing of exceptions, interrupts, and traps (these three are collectively referred to as BIT) using hardware.

The micro ROM unit 105 also manages store buffers. The micro ROM unit 105 is manually supplied with flag information based on interrupts or arithmetic execution results that do not depend on instruction codes, and outputs from the instruction decoding unit such as the output from the second decoder 305. The output of the micro-decoder is mainly output to the data calculation unit 106, but some information, such as other preceding processing stop information due to execution of a jump instruction, is also output to other blocks.

(2, 4) r Operand Address Calculation Unit The operand address calculation unit 104 is hard-wired controlled by information related to operand address calculation output from the address decoder of the instruction decoding unit 102, etc. This block performs most of the processing related to operand address calculation. A check is also made to see if the address of the memory access for memory indirect addressing and the operand address fall into the I/Ofi, ff area mapped to memory.

The address calculation result is sent to the external bus interface section 107.
sent to. The general purpose register and program counter values necessary for address calculation are input from the data calculation section.

When indirect memory addressing is performed, the address output circuit 108 outputs the memory address to be referenced to the outside of the CPU through the external bus interface unit 107, and the indirect address value input from the data input/output unit 109 is fetched through the instruction decoding unit 102. .

(2, 5) rpc calculation unit” The PC calculation unit 103 is hard-wired controlled by information related to PC calculation output from the instruction decoding unit 102, and calculates the pc value of the instruction. The data processing device of the present invention has a variable length instruction set, and the length of the instruction cannot be determined unless the instruction is decoded. For this reason, PC
The calculation unit 103 creates the pc value of the next instruction by adding the instruction length output from the instruction decoding unit 102 to the pc value of the instruction being decoded. In addition, the instruction decoding unit 1
When 02 decodes a branch instruction and instructs a branch at the decoding stage, the pc value of the branch destination instruction is calculated by adding the branch displacement instead of the instruction length to the pc value of the branch instruction. In the data processing apparatus of the present invention, branching to a branch instruction at the instruction decoding stage is called a branch branch.

Regarding this Bribranch method, please refer to the patent application No. 61-204.
500 and Japanese Patent Application No. 61-200557.

The calculation result of the pc calculation unit 103 is output as the pc value of each instruction together with the instruction decoding result, and at the time of pre-branch, it is output to the instruction fetch unit 101 as the address of the next instruction to be decoded. It is also used as an address for branch prediction of the next instruction to be decoded by the instruction decoding unit 102.

The branch prediction method is described in detail in Japanese Patent Application No. 8394/1983.

(2, 6) r Data Operation Unit The data operation unit 106 is controlled by a microprogram, and uses registers and arithmetic units to execute operations necessary to realize the function of each instruction according to the output information of the micro ROM unit 105. When the operand to be operated on is an address or an immediate value, the address or immediate value calculated by the operand address calculation unit 104 is passed through the external hash interface unit 107 and obtained. In addition, when the operand to be calculated is in the memory outside the CPU, the address calculated by the address calculation unit 104 is sent to the address output circuit l by the bus ink face unit.
The data input/output circuit 109 obtains the operands outputted from O8 and fetched from the memory outside the CPU.

Examples of arithmetic units include LIJ313, barrel shifter, priority encoder or counter, and shift register. The registers and the main arithmetic unit are connected by three buses, and one microinstruction that instructs one register-to-register operation is processed in two clocks (one step).

When it is necessary to access memory external to the CPU during data calculation, the address is output from the address output circuit 108 to the outside of CI) U through the external bus interface section 107 according to instructions from the microprogram, and the address is output to the outside of the CI) U through the data input/output circuit 109. Fetch data.

When storing data in a memory external to the CPU, an address is output from the address output circuit 108 through the external bus interface section 107, and at the same time, data is output from the data input/output circuit 109 to the outside of the CPU. In order to efficiently store operands, the data calculation unit 106
is equipped with a 4-byte storeba sofa.

When the data calculation unit 106 obtains a new instruction address by performing jump instruction processing or exception processing, it outputs this to the instruction fetch unit 101 and the pc calculation unit 103.

(Left below) (2, 7) ``External Bus Interface Section'' The external bus interface section 107 controls communications on the external bus of the data processing apparatus of the present invention. All memory accesses are performed in clock synchronization, with a minimum of two clock cycles (
It can be done in one step).

The access request to the memory is the instruction fair 101,
Operand address calculation unit 104 and data calculation unit 10
arises independently from 6. External bus interface section 10
7 arbitrates these memory access requests. Furthermore, when accessing data at a memory address that straddles a 32-bit (1 word) aligned boundary, which is the data bus size that connects the memory and the CPU, it is automatically detected within this block that it straddles a word boundary. This is done by breaking it down into multiple memory accesses.

It also performs conflict prevention processing when the pre-fetch operand and store operand overlap, and bypass processing from the store operand to the fetch operand.

(3) [Pipeline mechanism j The pipeline processing function of the data processing device of the present invention is
As schematically shown in the figure.

The instruction fetch stage (IF
Stage) 201. Decode stage (D stage) 202 for decoding instructions. Operand address calculation stage (to stage) 203 for calculating addresses of operands. Micro ROM access (especially R stage 2)
06) and the operand briefetch (
Operand fetch stage (F stage) 204. A five-stage configuration of an execution stage (E stage) 205 for executing instructions is the basis of pipeline processing.

In addition to having a one-stage store buffer in the E stage 205,
Some of the high-performance instructions pipeline the instruction execution itself, so there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and in theory the five stages operate completely independently.

Each stage can perform one process in a minimum of two clocks (one step). Therefore, ideally two clocks (
Pipeline processing progresses one after another for each step (1 step).

The data processing device of the present invention has some instructions that cannot be processed with just one basic pipeline process, such as memory-to-memory operations or memory indirect addressing, but the data processing device of the present invention can handle these processes. It is designed to perform pipeline processing as balanced as possible. An instruction having multiple memory operands is decomposed into multiple pipeline processing units (step codes) based on the number of memory operands and subjected to vibe line processing.

Regarding the decomposition method of pipeline processing units, please refer to the patent application 1986.
It is described in detail in No.-236456.

The information passed from the IF stage 201 to the D stage 202 is the instruction code 211 itself. D stage 2
There are two types of information passed from 02 to the A stage 203: information related to the operation specified by the instruction (referred to as D code 212), and information related to operand address calculation (referred to as A code 213).

The information passed from the A stage 203 to the F stage 204 is an R code 214 that includes the microprogram entry address or microprogram parameters, and an F code 215 that includes the operand address and access method instruction information. .

The information passed from the F stage 204 to the E stage 205 is two types: an E code 216 including arithmetic control information and literals, and an S code 217 including operands or operand addresses.

El↑ detected at a stage other than E stage 205 is BIT until the code reaches E stage 205.
Does not start processing. Only the instructions being processed in the E stage 205 are instructions in the execution stage, and the instructions being processed in the IF stage 201
This is because the instructions being processed between F stage 204 and F stage 204 have not yet reached the execution stage. Therefore, when a BIT is detected at a stage other than the E stage 205, its detection is recorded in the step code and only transmitted to the next stage.

(3,1) r pipeline processing unit” (3,1,l)
Classification of Instruction Code Fields The pipeline processing unit of the data processing apparatus of the present invention is determined using the format characteristics of the instruction set.

As described in section (1), the instructions of the data processing device of the present invention are variable-length instructions in 2-byte units, and basically consist of "2-byte basic instruction part + 0 to 4-byte addressing extension part". An instruction is constructed by repeating ~3 times.

In most cases, the instruction basic part has an operation code part and an addressing mode specification part, and if index addressing or memory indirect addressing is required, a "2-byte multi-stage indirect mode specification part" is used instead of the addressing extension part. +0 to 4 bytes of addressing extension” is optionally added. Also, depending on the command, 2 or 4
An instruction-specific extension of bytes is appended at the end.

The instruction basic part includes the instruction operation code, basic addressing mode, literal, etc. Addressing extensions include displacement, absolute address,
Either an immediate value or a displacement of a branch instruction. Instruction-specific extensions include a register map, immediate value specification for I-format instructions, and the like. FIG. 27 is a schematic diagram showing the characteristics of the basic instruction format of the data processing device of the present invention.

(3, 1, 2) Decomposition of instructions into r-step codes The data processing device of the present invention performs pipeline processing that takes advantage of the characteristics of the instruction format described above.

In the D stage 202, “2-byte instruction basic part +0 to 4
"byte addressing extension", "multi-stage indirect mode specification section + addressing extension", or instruction-specific extension are processed as one decoding unit.The decoding result of each time is called a step code, and from the A stage 203 onwards, this step Code is the unit of pipeline processing.The number of step codes is unique for each instruction, and if multi-stage indirect mode is not specified, one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes.Multi-stage When the indirect mode is designated, the step code increases accordingly.However, as will be described later, this only occurs at the decoding stage.

(3, 1, 3) ``Program counter management'' It is possible that all the step codes existing on the pipeline of the data processing device of the present invention are for different instructions,
Therefore, the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction that the step code is based on. The program counter value that accompanies the step code and flows through each stage of the pipeline is referred to as the step program counter (SPC). The SPC is passed between pipeline stages one after another.

(3, 2) Processing of Each Vibration Line Stage The turnout step codes of each pipeline stage are given names for convenience as shown in FIG. Further, the step code performs processing related to the operation code, and there are two series: a series that becomes the entry address of the microprogram and parameters for the E stage 205, and a series that becomes the operand for the microinstruction of the E stage 205.

(3, 2, 1) r instruction fetch stage The instruction fetch stage (IF stage) 201 fetches instructions from memory or branch buffer and stores them in the instruction queue 30.
1 and outputs the instruction code to the D stage 202. The manual operation of the instruction queue 301 is performed in aligned 4-byte units. When fetching instructions from memory, a minimum of 2 clocks (l steps) per 4 aligned bytes
It takes.

If the branch buffer is hit, it can be fetched in 1 clock per aligned 4 bytes. The output unit of the instruction queue 301 is variable every 2 bytes, and up to 6 bytes can be output during 2 clocks. Immediately after a branch, the instruction queue 301 is bypassed and the instruction basic unit 2
It is also possible to transfer the bytes directly to the instruction decoder.

Control of registering and clearing instructions in the branch buffer,
Management of the address of the instruction to be fetched and instruction queue 3
01 is also controlled by the IF stage 201.

EITs detected at the IF stage 201 include bus access exceptions when fetching instructions from memory, address translation exceptions due to memory protection violations, and the like.

(3, 2, 2) "r instruction decode stage" instruction decode stage (D stage) 202 is ■F stage 201
Decodes the instruction code input from. Decoding is carried out using the first unit that combines the FHW decoder, NFHW decoder, and addressing mode decoder of the instruction decoding unit 102.
2 clocks (1 step) using decoder 303
This is performed once per unit, and one decoding process consumes an instruction code of 0 to 6 bytes (no instruction code is consumed in output processing of a step code including the return destination address of an IET instruction, etc.). A stage 203 with one decoding
In response, a control code and address modification information, which is the A code 213 as address calculation information, and a control code and 8-bit literal information, which are the 1] code 212 as the intermediate decoding result of the operation code, are output.

The D stage 202 also performs control of the PC calculation unit 103 for each instruction, branch prediction processing, branch processing for a branch instruction, and instruction code output processing from the instruction queue 301.

EITs detected in the D stage 202 include reserved instruction exceptions and odd address jump traps at the time of a branch. Further, various BITs transferred from the IF stage 201 are encoded into step codes and transferred to the A stage 203.

(3, 2, 3) r operand address calculation stage”
Operand address calculation stage (A stage) 203
The processing functions are broadly divided into two. One is a process in which the second decoder 305 of the instruction decoding unit 102 is used to decode the operation code at a later stage, and the other is a process in which the operand address calculation unit 104 calculates an operand address.

The subsequent decoding process of the operation code is D code 2.
12 as an input, and outputs an R code 214 including register and memory write reservations, microprogram entry addresses, parameters for the microprogram, and the like. Note that the register or memory write reservation is intended to prevent incorrect address calculation from being performed due to the contents of the register or memory referenced in address calculation being rewritten by a preceding instruction on the pipeline. Register or memory write reservations are made for each instruction, not for each step code, to avoid deadlock. The reservation of writing to registers and memory is described in detail in Japanese Patent Application No. 144394/1983.

The operand address calculation process takes the A code 213 as input, and operates the operand address calculation unit 1 according to the A code 213.
Address calculation is performed in combination with addition or memory indirect reference in step 04, and the calculation result is output as F code 215. At this time, a conflict check is performed when reading registers and memory during address calculation, and if a conflict is indicated because the preceding instruction has not finished writing to the register or memory, the preceding instruction executes the writing process at E stage 205. Wait until it finishes. It also checks whether the operand address and the memory indirect reference address fall within the l10SI area mapped to memory.

The BIT detected in the A stage 203 includes a reserved instruction exception,
privileged instruction exception, bus access exception, address translation exception,
There is a debug trap due to an operand breakpoint hit during memory indirect addressing. If the D code 212 or A code 213 itself indicates that an EIT has occurred, the A stage 203 does not perform address calculation processing on that code, and transfers the EIT to the R code 21.
4 and F code 215.

(3, 2, 4) r Micro ROM access stage
The operand fetch stage (F stage) 204 is also roughly divided into two processes. One is access processing of the micro ROM, and is particularly referred to as the R stage 206. The other is operand briefetch processing, particularly referred to as OF stage 207. The R stage 206 and the OF stage 207 do not necessarily operate simultaneously (they operate independently depending on whether memory access rights can be acquired, etc.).

Micro ROM access processing, which is the processing of the R stage 206, is performed on the R code 214 at the next E stage 205.
E code 21 which is the execution control code used for execution in
This is micro ROM access and micro instruction decoding processing to generate 6. When processing for one R code 214 is broken down into two or more microprogram steps, the micro ROM is used in the E stage 205 and the next R code 214 waits for micro ROM access. Micro ROM access to R code 214 occurs during the last micro instruction execution in the previous E stage 205. In the data processing device of the present invention, most basic instructions are executed in one microprogram step, so in reality, micro ROM accesses to the R code 214 are often executed one after another.

There is no new BIT detected in the R stage 206.

When the R code 214 indicates an instruction processing re-execution type EIT, the microprogram for that EIT processing is executed, so the R stage 206
Fetch the microinstruction according to 4.

If R code 214 indicates an odd address jump trap, R stage 206 sends it to E code 216.
convey by. This is for Bribranch,
In the E stage 205, if a branch does not occur in the E code 216, the branch is made valid and an odd address jump trap is generated.

(3, 2, 5) r Operand Fetch Stage The operand fetch stage (OF stage) 207 performs operand prefetch processing of the above two processes performed in the F stage 204.

Operand briefetch takes F code 215 as input,
The fetched operand and its address are sent to S code 21.
Output as 7. One F code 215 specifies operand fetch of 4 bytes or less, although it may span word boundaries. The F code 215 also includes a designation as to whether or not to access the operand, and the A stage 203
When transferring the operand address itself or the immediate value calculated in , to the E stage 205, the operand prefetch is not performed, and the contents of the F code 215 are transferred as the S code 217. If the operand to be pre-fetched matches the operand to be written by the E stage 205, the operand pre-fetch is not performed from memory but is bypassed. In addition, for the [10 area, operand prefetch is delayed, and operand fetch is performed after waiting until all preceding instructions are completed.

The BITs detected in the OF stage 207 include a bus access exception, an address translation exception, and a debug trap caused by a breakpoint hit for operand briefetch. When the F code 215 indicates an EIT other than a debug trap, it is transferred to the S code 217 and no operand prefetch is performed. F code 21
When 5 indicates a debug trap, the same processing as when BIT is not indicated is performed for the F code 215, and the debug trap is transmitted to the S code 217.

(3, 2, 6) r Execution Stage” The execution stage (E stage) 205 operates with the E code 216 and the S code 217 as input. This E stage 205 is a stage for executing instructions, and all processing performed in stages before the F stage 204 is preprocessing for the E stage 205. When a jump instruction is executed or BIT processing is started at E stage 205, all processing from IF stage 201 to F stage 204 is invalidated. E stage 20
5 is controlled by a microprogram, R code 21
The instructions are executed by executing a series of microprograms starting from the microprogram entry address shown in 4.

Micro RO? The reading of I and the execution of microinstructions are performed in a pipelined manner. Therefore, when a branch occurs in a microprogram, one microstep becomes vacant. In addition, the E stage 205 includes the data calculation section 10
Using the store buffer in 6, it is also possible to perform pipeline processing for storing operands within 4 bytes and executing the next microinstruction.

In the E stage 205, the write reservation for registers and memory made in the A stage 203 is canceled after the operand is written.

Further, if a conditional branch instruction issues a branch at the E stage 205, the branch prediction for that conditional branch instruction was incorrect, so the branch history is rewritten.

BITs detected in the E stage 205 include bus access exceptions, address translation exceptions, debug traps, odd address jump traps, reserved function exceptions, illegal operand exceptions, reserved stack format exceptions, divide-by-zero traps, unconditional traps, and conditional traps. There are , delayed context traps, external interrupts, delayed interrupts, reset interrupts, and system failures.

All BITs detected at E stage 205 are processed, but BITs from IF stage 201 before E stage
BIT detected between stages 2040 and reflected in R code 214 or S code 217 is not necessarily BIT.
It does not necessarily have to be processed by IT. It was detected between IP stage 201 and F stage 204, but the preceding instruction was
All BITs that have not reached the E stage 205 due to a jump instruction being executed at the stage 205 or the like are cancelled. This means that the instruction that caused the IEIT was never executed in the first place.

External interrupts and delayed interrupts are processed at E stage 20 at the end of instructions.
5 is directly accepted, and the necessary processing is executed by the microprogram. Other various EIT processes are performed by microprograms.

(3, 3) rState control of each pipeline stage Each stage of the pipeline has an input latch and an output latch, and basically operates independently of other stages. Each stage completes the previous processing and transfers the processing result from the output lunch to the input latch of the next stage, and when the input latch of its own stage has all the input signals necessary for the next processing, the next stage is started. start processing.

In other words, in each stage, all human input signals for the next process output from the previous stage are valid, the current processing result is transferred to the input latch of the next stage, and when the output latch becomes empty, the next process starts. Start.

All input signals must be available at the clock timing immediately before each stage starts operating. If the input signals are not ready, the stage is in a waiting state (waiting for input). When transferring from the output latch to the next stage's manual latch, the input lunch of the next stage must be free, and even if the input latch of the next stage is not free, the pipeline stage will wait. state (waiting for output). If a necessary memory access right cannot be acquired, a wait is inserted into the memory access being processed, or other pipeline conflicts occur, the processing itself at each stage will be delayed.

(3, 4), Step Code Processing Regarding Push r, Push A Instructions” FIG. 28 is a block diagram for explaining the present invention. 61 is a working stage stack pointer (ASP) of the operand address calculation stage (A stage 203)
, which indicates the value of the stack pointer associated with the instruction being executed in the A stage 203. 62 is a working stage stack pointer (FSP) of the operand fetch stage (F stage 204), and 63 is a working stage stack pointer (C3P) of the execution stage (E stage 205).
), each indicating the value of the stack pointer associated with the instruction being executed at each stage. 64 is a stack pointer group at the software level, 70 is an address register (FA register) of the F stage 204, and 71 is an S
Address register (SA register) that stores the operand address as code 217, 72 is E stage 20
5 address register (AA register), 73 a data register (DD ranging) of the E stage 205 for data exchanged with the outside, and 74 a data register of the F stage 204.
75 is an address adder of the A stage 203, and 80 to 87 are internal data buses.

102 is an instruction decoding unit, 106 is an execution stage 205
108 is an address output circuit, and 109 is a data input/output circuit.

FIG. 32 is an instruction format diagram of push and push^ instructions processed in the data processing device of the present invention.

Further, FIGS. 29, 30, and 31 are flowcharts showing operations at each stage of the push and push^ commands executed in the data processing device of the present invention.
In Figure 9, the source is memory, in Figure 30, the source is register,
FIG. 31 shows the case of a push command. Also step 5
100 to 5105 are A stage 203, step 520
0 to 5205 are F stage 204 and step 5300
5307 indicate the operations at the E stage 205, respectively.

Push processed in the data processing device of the present invention,
The push eight command has the format shown in Figure 32,
Stores the source operand specified in the instruction to the top of the stack. In a push instruction, the value indicated by the source ranging mode becomes the source operand, and in a push^ instruction, the source address becomes the source operand.

Further, as the destination address, a value obtained by decrementing the value of the stack pointer by the size of the operand is used. In this way, the push and push instructions are instructions that can be transferred between memories and require two address calculations, so they originally require two step codes.

However, in the present invention, the ASI'61 is provided with a decrement function, and the address calculation in the A stage 33 and the 85l
) 61 bride-decrements are performed simultaneously in one stem code.

Push, Push A commands in Figures 2, 28, and 29
30 and 31, we will follow the flow of the vibe line. First, after decoding the push and push to A instructions in the instruction decoding unit 102, addressing mode information, update control information of the ASP61, etc. are converted into one step code (A code 213) and sent to the address addition unit 75 of the A stage 203 and the ASP61. Output.

Information on the opcode side of the instruction is output as a D code 212.

The operation of each stage after this is shown in Figures 29, 30, and 3.
Shown in Figure 1. The processing of one E code 216 in the E stage 205 is called one step.

First, FIG. 30 shows a case where the source is a register in a push instruction.

In the A stage 203, ^5P61 is decremented by the size of the operand according to the ^sp update control information of the A code 213. And this decremented 85P61
The value of is transferred to the FSP 62 in synchronization with the flow of the step code in the pipeline (S103), and the source register number etc. is output as the R code 214 (S103).
102).

In the F stage 204, the value of the FSP62 is transferred to the C3P63 in synchronization with the flow of the step code in the pipeline (S203). Furthermore, an E code 216 including a signal for accessing the source register is generated and outputted from the R code 214 (S202).

At the E stage 205, the value of C5P63 is written into the AA register 72 as the destination address.

The route at this time is C3P63→St bus 82→AA register 72.

Further, the value of the register specified by the E code 216 is written to the DD register 73. The path at this time is register 76
→S2 bus 87→data calculation unit 106→DO bus 85→
It becomes DD register 73. Since these two routes do not collide, they are executed in one step (S303).

Next, the DD register 7 is set to the address pointed to by the AA register 72.
A value of 3 is written (S304). This store processing can be executed independently of the data calculation processing at the E stage 205, and the next instruction can be processed in parallel with the store processing.

Next, FIG. 29 shows a case where the source is a memory in a push instruction.

In the A stage 203, the ASP 61 is decremented by the size of the operand according to the ^sp update control information of the A code 213. And this decremented ASP6
The value of 1 is transferred to the FSP 62 in synchronization with the flow in the by-line of the step code (S101). Also, the address addition unit 75 calculates the source address (5100).
, is output as F code 215.

In the F stage 204, the value of the FSP 62 is transferred to the C3P 63 in synchronization with the flow of the step code in the pipeline (S201). The source address of the F code 215 is stored in the FA register 70, and the source operand is fetched from memory based on the value and sent to the S lo register 74.
(S200).

In the E stage 205, the value of C5P63 is written as the destination address of the AA register 72ζ (S
300). The route at this time is C3P63→Sl bus 82→AA register 72.

The source operand fetched in the F stage 204 is transferred from the SD register (74) to the DD register 73 (S301). The route at this time is: SO register 73 → S1 bus 87 → theta calculation unit 106
→D.

Bus 85 → 00 register 73 becomes.

Since these two paths both include the S1 bus 82, the steps are performed in two parts. However, although the SD register 74 also has a path that passes through the S2 bus 87,
In 5, the above route is taken because it is easier to execute the register directly and other parts. As a case where there is no route to the SL bus 82 other than directly to the register, there is a case where the source is an immediate value. The immediate value data is output as is from the address adder 75, passes through the AO bus 3→F^ register 70→SA register 71, and is output to the S1 path 82. At this time, since the C5P63→AA register 72 only has a route that uses the S1 bus 82, the process is divided into two steps and executed.

In accordance with this immediate value, etc., the memory case is also executed in two steps.

Then, the value of the DD register 73 is written to the address pointed to by the AA register 72 (S302).

In this embodiment, two steps are required in the E stage 205 due to a conflict on the Sl bus 82. However, if the SA register 71 → data calculation unit 106 and C5P63 → static register 72 can be performed in one step by extending the S2 bus 87, then the E stage 205
can be combined into one step.

Next, FIG. 31 shows the case of the push A command.

At the A stage 203, the ASP 61 is decremented by the size of the operand according to the ^sp update control information of the A code 213. And this decremented ^5P61
The value of is transferred to the FSP (62) in synchronization with the flow of the step code in the pipeline (S105). In addition, the address adder 75 calculates the source address and F code 2.
15 (S104).

In the F stage 204, the value of the FSP62 is transferred to the C5P63 in synchronization with the flow of the step code in the pipeline (S205). F code 215 source address
The value is stored in the A register 70 and transferred to the SA register 71 (5204). This value becomes the source operand.

In the E stage 205, the value of C5P63 is written to the AA register 72 as the destination address (S3
05). The route at this time is C5P63→Sl bus 82→AA register 72.

The value of the SA register 71 is sent to the Rolo register 73 as a source operand (S306). The route at this time is SA
The sequence is as follows: register 71→S1 bus 87→theta calculation unit 106→RO bus 85→DO register 73. Since these two paths both include the S1 bus 82, it is executed in two steps.

The value of the DD register 73 is written to the address pointed to by the AA register 72 (S307).

In this way, push, push A command is A stage 20
When the process ends in step 3, the value of the stack pointer at the end of this instruction is stored in the ASP 61. Therefore, even if the step code of a later instruction refers to the stack pointer at the A stage 203, a conflict regarding the stack pointer will not occur because the push or push A instruction will not rewrite the value of ASP61 at the F stage 204 or E stage 205. do not have. For example, even if the addressing mode of the next instruction is (SP + disp), by executing (ASP + disp) in the address adder 75, it will be correct without waiting for the end of execution of the push, push^ instruction. You will get an address.

Furthermore, when the source of a push instruction is a register, the number of execution steps at each stage is one step, and the instruction execution time at this time is a minimum of two clocks. In other words, the calculation in the address adder 75 and the update in the ASP 61 are
By doing this with one step code, the push instruction is faster due to the increase in execution steps (1 step → 2 steps) in the A stage 203, which occurs when generating two step codes for the source side and the destination side. It is possible to make changes.

[Effects of the Invention] As described above, according to the present invention, in the address calculation stage during push and push eight instruction processing, the operand address is calculated in the address adder and the stack pointer in the address calculation stage is updated. By transferring the stack pointer value in synchronization with the flow of the pipeline, the instructions after the push and push A instructions can improve pipeline processing efficiency without causing conflicts regarding the stack pointer at the address calculation stage. Furthermore, since a push command can be executed in at least one step, the performance of the data processing device is improved.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a pipeline of a data processing device according to an embodiment of the present invention, and FIGS. FIG. 28 is a diagram showing the characteristics of the instruction format of a data processing device according to an embodiment of the present invention; FIG. 28 is a configuration diagram of a stack pointer-related portion of a data processing device according to an embodiment of the present invention; FIGS. 32 is an execution flowchart of the push and push^ instructions executed in the data processing device of the present invention, FIG. 32 is an instruction form diagram of the push and push eight instructions executed in the data processing device of the present invention, and FIG. 33 is a conventional FIG. 34 is a block diagram of the data processing device of FIG. 34, which is a conventional push instruction execution flowchart. 203... Address calculation stage (A stage) 20
5... Execution stage (E stage) 212-217.
・Step code which is the unit of pipeline processing 6
1...A stage working stage stack pointer 63...E stage working stage stack pointer 75...A stage address addition unit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. An execution stage that executes an instruction, which includes a push instruction that pushes operand values that can be specified in general-purpose addressing mode onto a stack in memory, and a process that precedes processing in the execution stage. an address calculation stage that calculates an address of an operand; and an address adder controlled by the address calculation stage that calculates an address of an operand; a first stack pointer that is controlled by the address calculation stage and performs decrement processing in conjunction with operand processing when the general-purpose addressing mode is stack push mode; and a second stack pointer that is controlled by the execution stage. , the first stack pointer is updated prior to the update process of the second stack pointer, and during the push instruction processing, the address calculation of the operand is performed using the address adder in the address calculation stage; A data processing device characterized in that a stack pointer is updated in accordance with a push operation on the first stack pointer.