JPH0298734A - Data processor - Google Patents

Abstract

PURPOSE:To perform a balanced pipeline processing at the time of processing a POP instruction by generating a process unit with respect to a source operand shown by the POP instruction indirectly, and performing the pipeline processing of the process unit. CONSTITUTION:The step code (4-1) of an instruction one preceding to the POP instruction requires three steps in a processing at an E stage 205, therefore, a two step queue state for the step code of the POP instruction is generated at an F stage 204. In such a case, the number of step codes to be processed at the E stage 205 is reduced by the absorption of a step code (2-1), and as a result, the number of steps required for the entire processing can be reduced. Thus, high possibility to reduce the number of steps required for the processing can be generated when a queue state on a pipeline mechanism is generated by absorbing an unrequired step code (2-1) on the pipeline mechanism. In such a way, it is possible to accelerate the processing speed of a data processor.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device that operates according to a pipeline processing method, and in particular has a processing function for an instruction that uses a POP instruction as a source operand. The present invention relates to a data processing device having a data processing device.

[Prior Art] The configuration of the pipeline processing function of a conventional data processing device is shown in the block diagram of FIG.

A conventional data processing device has an instruction fetch stage 391.
．． Instruction decode stage 392. Operand address calculation stage 393. Operand fetch stage 394
and an execution stage 395. Then, in the decoding stage, the instruction is decomposed into unit codes (step codes) for pipeline processing and pipeline processing is performed. Details of such a data processing device are disclosed in Japanese Patent Laid-Open No. 89932/1983.

In the conventional data processing device as described above, the instruction fetch stage 391 . Instruction decode stage 392. It is divided into a part that performs preprocessing such as an operand address calculation stage 393 and an operand fetch stage 394, and a part that executes instructions such as an execution stage 395.

The preprocessing portion performs only preprocessing regarding operands specified in the instruction, and the instruction is executed by the execution stage 395 using the operands prepared by the preprocessing.

However, in such data processing devices, although an instruction has only one operand specification part, instructions that have other operands implicit in the functional meaning of the instruction are not processed in the pipeline. In some cases, sufficient pretreatment is not performed on the above.

An example of such an instruction is a pop (r'OP) instruction. It is assumed that the POP instruction can specify a memory or a register as a destination.

In a data processing device, a stack area is usually formed in a memory space for saving data. An instruction to save data to the stack and an instruction to read the saved data from the stack are provided. The former command is pt+so command, the latter command is P
These instructions are called OP instructions and are symmetrical to each other. Note that the stack pointer (SP) always indicates the address of the highest (stack top) of the stack.

The POP instruction is an l-operand instruction that has only an operand for specifying a destination. However, in terms of the function of the instruction itself, the POP instruction is actually a two-operand instruction that implies that the source operand is the top of the stack, and is equivalent to an inter-memory or inter-memory-register transfer instruction.

When processing a POP instruction, only a step code for processing the destination is generated by the destination designation section of the POP instruction on the pipeline of a conventional data processing device.

Processing of this step code means calculating the destination address in the operand address calculation stage 393, which is a part that performs preprocessing of the instruction. However, since the POP instruction does not have a source specification section, no step code regarding the source is generated, and no preprocessing regarding the source specification section is performed.

Processing related to the source specification part is executed in the execution stage 395, which is the part that executes instructions, by a series of microinstructions when the pop instruction is executed. in particular,
In the execution stage 395, the process related to the source specification section of fetching data from the top of the stack is first performed, and then the pop instruction is transferred to the destination address prepared in preprocessing. It is processed.

In such processing, the execution stage 395 carries out processing related to the source specification part that should be performed as preprocessing in a normal two-operand instruction, so the processing load on the execution stage 395 is extremely large. Furthermore, since the processing load at each stage is uneven, processing efficiency in pipeline processing is reduced.

[Problems to be Solved by the Invention] In a conventional data processing device, the pop instruction as described above is processed on a pipeline processing mechanism.

At this time, since the execution stage itself needs to perform processing to fetch the operand from the top of the stack, the load of de-processing in the stage that executes the instruction is greater than that in the stage that performs preprocessing, and There is a problem that processing efficiency does not improve.

The present invention has been made to solve such problems, and it is an object of the present invention to provide a data processing device that can efficiently process l-operand instructions in which the source operand is limited to a specific attributing mode on a pipeline. purpose.

[Means for Solving the Problems] A data processing device according to the present invention includes means for generating a processing unit of a source operand that is implicitly indicated at the time of instruction decoding when processing a pop instruction, and a destination that is a register. In some cases, a means is provided for processing a destination operand processing unit and a source operand processing unit to generate one processing unit before executing an instruction.

[Operation] In the data processing device of the present invention, a processing unit is also generated for the operand implied in the preprocessing part on the pipeline, data at the top of the stack is briefetched, and the data at the destination is If the nation is a register, processing related to the destination operand is performed. [Embodiments of the Invention] The present invention will be described in detail below with reference to drawings showing embodiments thereof.

(1) “Instruction format of the data processing device of the present invention”
The instructions of the data processing device of the present invention have a variable length in units of 16 bits, and instructions with an odd number of bytes are not used.

The data processing device of the present invention has an instruction format system specially devised for the purpose of making high opening degree instructions into a short format. For example, for 2-operand instructions, there is a general format that basically has a configuration of 4 bytes + 10 bits and all addressing modes can be used, and only frequently used instructions and addressing modes are used. There are two possible abbreviated formats.

The meanings of the symbols appearing in the instruction format of the data processing device of the present invention are as follows.

-: Part where operation code is entered #; Part where literal or immediate value is entered Ea: Part where operands are specified in 8 mini 8-bit addressing mode Sh: Part where operands are specified in 6-bit abbreviated addressing mode Rn: Register The partial formant that specifies the above operand by register number is 1. on the right side as shown in FIG. It is on the sB side and has a high address. The instruction format cannot be determined without looking at the two bytes of address N and address N+1, but this means that, as mentioned above, instructions are always fetched and decoded in units of 16 bits (2 bytes). This is because i Q.

In the data processing device of the present invention, l! of each operand in any format. The a or sh extension is always placed immediately after the halfword containing the Ea or sh base. This overrides any immediate data or extensions of the instruction implicitly specified by the instruction. Therefore,
For instructions of 4 bytes or more, the operation code of the instruction may be divided by the extension part of Ea.

Furthermore, as will be described later, even if an extension part is added to the extension part of Ea in the multi-stage indirect mode, that part is given priority over the next instruction operation code.
Halfword contains Eal, second halfword contains Ea
Consider the case of a 6-byte instruction containing 2 and up to the third halfword. Since the multi-stage indirect mode is used for 1Eal, assuming that the multi-stage indirect mode extension part is attached in addition to the normal extension part, the actual instruction bit pattern is
halfword (contains the base of Eat), extension of Bal, multi-indirect mode extension of Eal, second halfword of instruction (contains base of Ea2) + extension of Eal, third halfword of instruction The order is as follows.

(1,1) r Shortened Two-Operand Instruction" FIGS. 13 to 16 are schematic diagrams showing the shortened form of a two-operand instruction.

FIG. 13 is a schematic diagram showing the formant of an operation instruction between memory registers. This format includes L-format, where the source operand side is memory, and S-rort, where the destination operand side is memory.
There is mat.

In the L-format, sh is the specification field of the source operand, Rn is the specification field of the destination operand register, and RR is the specification of the sh operand size. Fixed to humans. Sign extension is performed when the size of the register side and the memory side are different and the size of the source side is small.

In 54or+wat, sh represents the destination operand designation field, Rn represents the source operand register designation field, and IIR represents the sh operand size designation. The size of the source operand located on the register is fixed at 32 bits. If the size of the register side and the memory side are different and the size of the source side is large, the overflow portion is truncated and an overflow check is performed.

FIG. 14 is a schematic diagram showing the format (R-format) of an inter-register operation instruction. Rn is a destination register designation field, and Rm is a source register designation field. The operand size is only 32 bits.

Figure 15 shows the format y of literal-memory operation instructions.
FIG. ■ is the destination operand size specification field,
(1) 1 is a literal source operand specification field, and sh is a destination operand specification field.

Figure 16 shows the formant (1
-format). Sh is a field specifying the operand size (common for source and destination), and Sh is a field specifying the destination operand. The size of the immediate value of I-rortmat is 8.16.32 bits, which is the same as the size of the destination operand, and zero extension and sign extension are not performed.

(1, 2) r-hull shape l operand command” Figure 17 shows l
(Gl-for
FIG. Open is a field specifying the operand size. Some G1-format instructions have extensions in addition to the Ea extension. There are also instructions that do not use open.

(1, 3) r-Ship-shaped 2-operand instruction" FIGS. 18 to 20 are schematic diagrams showing the 1-ship format of the 2-operand instruction. This format includes 8
This is an instruction with a maximum of two operands in single-ship addressing mode specified by bits. The total number of operands itself may be three or more.

FIG. 18 is a schematic diagram showing the format (G-format) of an instruction whose first operand requires memory reading. EaM is a destination operand designation field, Open is a destination operand size designation field, EaR is a source operand designation field, and RR is a source operand size designation field. In some G-format instructions, Ea
There are extensions other than those of M or EaR.

FIG. 19 is a schematic diagram showing the format (E-format) of an instruction whose first operand is an 8-bit immediate value.

EaM is a destination operand specification field, ◯ is a destination operand size specification field, and . . . is a source operand value.

Although E-4ormat and I-format are similar in function, they are very different in terms of concept. Specifically, E-format only has two operands.
It is a derivative of the G-4 format, with the source operand size being fixed at 8 bits and the destination operand size being selectable from 8/16/32 bits. That is, the E-for set assumes an operation between different sizes, and the 8-bit source operand is zero-extended or sign-extended to match the size of the destination operand. On the other hand, Lformat is
This is a shortened form of the immediate value pattern that is often used in transfer instructions and comparison instructions in particular, and the size of the source operand and destination operand are equal.

FIG. 20 is a schematic diagram showing the format of an instruction whose first operand is only address calculation (GA-for+aat). Eall is a destination operand designation field, 4 is a destination operand size designation field, and EaA is a source operand designation field. The execution address calculation result itself is used as the source operand.

FIG. 20 is a schematic diagram showing the format of a short branch instruction. cccc is a branch condition specification field, and disp:8 is a displacement specification field with respect to the jump destination. In the data processing y1 device of the present invention, when specifying a displacement in 8 bits, double the specified value in Vinoto Bakun. Let it be a displacement value.

(1, 4) r Addressing Mode The method of specifying the addressing mode of the data processing device of the present invention includes a short form in which the addressing mode is specified in 6 bits including registers, and a general form in which it is specified in 8 bits.

If an undefined addressing mode is specified, or if a semantically inappropriate combination of addressing modes is specified, a reserved instruction exception will occur in the same way as when an undefined instruction is executed. , exception handling is triggered.

This applies, for example, when the ``stainability'' is in the immediate value mode, or when the immediate value mode is used in the addressing mode designation field that should involve address calculation.

The meanings of the symbols used in the format diagram are as follows.

Rn: Register specificationseem EA: Memory contents of the address indicated by EA (Sh): Specification method in G-bit abbreviated addressing mode (Ea): Specification method in 8-bit general addressing mode Broken line in the format diagram The area surrounded by indicates an extension.

(1, 4, 1,) rM Book Addressing Mode” The data processing device of the present invention supports various addressing modes. Among these, the basic addressing modes supported by the data processing device of the present invention include register direct mode, register indirect mode, register relative indirect mode, immediate mode, absolute mode, PC (program counter) relative indirect mode, and stack pop. There are two modes: mode and stack mode.

In register direct mode, the contents of the register are used as operands. A schematic diagram of the format is shown in Figure 22.
Rn indicates the number of a general-purpose register.

In register indirect mode, the operand is the contents of the memory whose address is the contents of the register. A schematic diagram of the format is shown in FIG. Rn indicates the number of a general-purpose register.

In register relative indirect mode, the displacement value is 1.
There are two types depending on whether it is 6 bits or 32 bits. 16 bits or 32 bits for register contents, respectively.
The operand is the contents of the memory whose address is the value plus the bit displacement value. A schematic diagram of the format is shown in Figure 24. Rn indicates the general-purpose register number, disp: 16 and dtsp: 32.
represent a 16-bit displacement value or a 32-bit displacement value, respectively, and the displacement values are treated as signed.

In the immediate value mode, the focus pattern specified in the instruction code is treated as a binary number and used as an operand. A schematic diagram of the format is shown in FIG.

ism-data indicates an immediate value.* The size of ism-data is specified in the instruction as the operand size.

In absolute mode, the address value is indicated by 16 bits or 32
There are 2 types depending on what is indicated by the bit. Each operand is the contents of the memory whose address is a 16-bit or 32-bit bit pattern specified in the instruction code. A schematic diagram of the format is shown in Figure 26.
abs:16 and abs:32 indicate a 16-bit or 32-bit address value, respectively.

When an address is indicated by abs:16, the specified address value is sign-extended to 32 bits.

There are two types of PC relative indirect mode, depending on whether the displacement value is 16 bits or 32 bits - in each case, the operand is the contents of memory whose address is the program counter contents plus the 16-bit or 32-bit displacement value. do.

A schematic diagram of the format is shown in Figure 27.
: 16 and disp : 32 respectively indicate a 16-bit displacement value or a 32-bit displacement value. The displacement value is treated as signed. In PC relative indirect mode, the referenced program counter value is its operand. This is the start address of the instruction containing the . When the value of the program counter is referenced in the multi-stage indirect addressing mode, the first address of the instruction is similarly used as a PC-relative reference.

The stack pump mode uses the contents of the memory whose address is the contents of the stack pointer (SP) as the operand.

After accessing the operand, increment the stack box by the operand size.

For example, when fetching 32-bit data, it is possible to specify stack pop mode for operands of size B and H, in which the SP is updated (incremented) by 4 after the operand is accessed, and the SP is the target for each. ,÷
FIG. 28 shows a schematic diagram of the format in which the stack pop mode is updated (incremented) by 2. A reserved instruction exception is generated for operands for which the stack pop mode has no meaning.

Specifically, the reserved instruction exception is the stack pop mode specification for the write operand and read-modify-write operand.

In stack bush mode, the operand is the contents of the memory whose address is the contents obtained by decrementing the contents of the stack pointer by the operand size. In stack bush mode, the stack pointer is decremented before operand access.For example, when handling 32-bit data, SP is updated (decremented) by -4 before operand access. It is also possible to specify the stacked bush mode for the operand, and a schematic diagram of the formant in which SP is updated (decremented) by -1 and -2 is shown in Figure 29. For those that have no meaning, a reserved instruction exception is generated. Specifically, the reserved instruction exception is the read operand, r
This is the stack bush mode specification for the ead-modify-write operand.

(1, 4, 2) Multi-stage indirect addressing mode No matter how complex addressing is, it is basically broken down into a combination of addition and indirect reference. Therefore, if the operations of addition and indirect reference are given as addressing primitives and can be combined arbitrarily, any complex addressing mode can be realized. @? is an addressing mode based on this idea. This addressing mode is particularly useful for inter-module data references or AI (artificial intelligence) language processing systems.

When specifying the multi-stage indirect addressing mode, the basic addressing mode specification field specifies one of three types of specification methods: register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute hash multi-stage indirect mode.

The register-based multi-stage indirect mode is an addressing mode that uses the register address as a base value for multi-stage indirect addressing that expands. A schematic diagram of the format is shown in FIG. 30, where Rn indicates the number of the general-purpose register.

The PC-based multi-stage indirect mode is an addressing mode in which the value of the program counter is used as the base value for multi-stage indirect addressing. A schematic diagram of the format is shown in the third section.
Shown in Figure 1.

The absolute base multi-stage indirect mode is an addressing mode that uses zero as the base value of extended multi-stage indirect addressing. A schematic diagram of the format is shown in FIG.

The multi-stage indirect mode specification field to be expanded has a unit of 16 bits, and this is repeated any number of times.

One-stage multi-stage indirect mode allows addition of displacement and scaling of index registration (Xll
2. ×4+X8) and performs memory indirect reference. A schematic diagram of the format of the multi-stage indirect mode is shown in FIG. Each field has the meaning shown below.

E; O E++1: Continuation of multi-stage indirect mode] End of Luss calculation tap ==> address or opera
nd! =0: No memory indirect reference tap 4 disp 4 RX t 5cale =
=> Lap■・l: Memory indirect reference ■em tmp + disp + Rx umbrella 5cale
=->LipM=O: Use <Rx> as index; Special index <RX>・0 Do not add index value (RX
=O) RX>・1 Use program counter as index value (Rx=PC) <Rx>=2= reserved port・O: Displace by multiplying the value of 4-bit field d4 in multi-stage indirect mode by 4. d4 is treated as a signed value and is always multiplied by 4 regardless of the size of the operand.D=l: di specified in the extension part of multi-stage indirect mode
spx (16/32 bit days is the displacement value, and the size of the extension section to which this is added is specified in the d4 field. d4 = o001 dispx is 16 bits (・d4・
0010 dispx is 32 bits xx=scale of index (scale=1/2/4/8) X2. X4. If scaling of No. Do not specify scaling for the program counter.

Variations in instruction formats in the multi-stage indirect mode are shown in FIGS. 34 and 35.

FIG. 34 shows variations on whether the multi-stage indirect mode continues or ends.

FIG. 35 shows variations in displacement size.

If a multi-stage indirect mode with an arbitrary number of stages can be used, there is no need for the compiler to differentiate between cases based on the number of stages, which has the advantage of reducing the burden on the compiler. This is because even if the frequency of multiple indirect references is very low, the compiler must always be able to generate correct code. Therefore, any number of stages is possible in the format.

(1, 5) Exception Handling” The data processing device of the present invention has abundant exception handling functions to reduce the software load. In the data processing device of the present invention, exception handling involves re-executing instruction processing (except )
They are divided into three types and named: , those that complete instruction processing (traps), and interrupts. Furthermore, in the data processing apparatus of the present invention, these three types of exception handling and system failure are collectively referred to as EIT.

(2) "Configuration of Functional Blocks" FIG. 1 is a block diagram showing the configuration of the data processing device of the present invention.

Functionally, the inside of the data processing device of the present invention can be roughly divided into an instruction fetch unit 101. instruction decoding unit 102,
PC calculation section 103. Operand address calculation unit 104゜Micro ROM unit 105. Data calculation unit 106. It is divided into an external path interface section 107.

In addition, in FIG. 1, an address output circuit 10B for outputting an address to the outside of the CPU, and a data input/output circuit 109 for inputting and outputting data to and from the outside of the CPU are shown separately from other functional blocks.

(2, 1) r Instruction fetch unit J The instruction fetch unit 101 includes a branch buffer, an instruction queue and its control unit, and determines the address of the next instruction to be fetched and fetches the instruction from the branch buffer or memory outside the CPII. 7 times. It also registers instructions to the branch buffer.

Since the branch buffer is small, it operates as a selective cache. Details of the operation of the branch buffer are disclosed in Japanese Patent Laid-Open No. 63-56731.

The address of the next instruction to be fetched is stored in the instruction queue 30.
When a 0 branch or jump, which is calculated by a dedicated counter as the address of an instruction to be input to 1, occurs, the address of a new instruction is transferred from the PC calculation unit 103 or the data calculation unit 106.

When fetching an instruction from a memory external to the CPU, the address of the instruction to be fetched is sent from the address output circuit 10B to the CPU through the external bus interface unit 107.
u is output to the outside, and the instruction code is fetched from the data input/output circuit 109. Then, among the buffered instruction codes, the instruction code to be decoded next is output to the instruction decoding unit 102.

(2, 2) r Instruction Decode Unit” The instruction decode unit 102 basically decodes instruction codes in units of 16 bytes (halfwords). This block includes an FH-decoder that decodes the operation code included in the []th halfword, an NFHW decoder that decodes the operation code included in the second + third halfwords, and an addressing mode decoder that decodes the addressing mode. These FIIW decoder, NFHW decoder, and addressing mode decoder are collectively referred to as a first decoder 303.

A second decoder 305 further decodes the output of the FH-decoder or NFH-decoder to calculate the entry address of the micro ROM, a branch prediction mechanism that predicts the branch of a conditional branch instruction, and a pipeline conflict prevention mechanism when calculating the operand address. Also included is an address calculation conflict checking mechanism.

The instruction decode unit 102 reads the instruction code input from the instruction fetch unit 101 every two clocks (one step).
~Decode 6 bytes at a time. Among the decoding results, information regarding the calculation in the data calculation unit 106 is stored in the micro ROM.
Information related to the operand address calculation is output to the operand address calculation section 104, and information related to the PC calculation is output to the PC calculation section 103.

(2, 3) ``Micro ROM section'' The micro ROM section 105 mainly includes a data calculation section 106.
It includes a micro ROM, a micro sequencer, a micro instruction decoder, etc. in which a micro program for controlling the micro program is stored. A microinstruction is read from the microROM once every two clocks (l step). In addition to the sequence processing indicated by the microprogram, the microsequencer accepts processing of exceptions, interrupts, and traps (these three are collectively referred to as 61 pieces) using hardware.

The microphone port ROM section 105 also manages the store server and file manager. The micro ROM unit 105 receives flag information based on interrupts or operation results that do not depend on instruction codes, and outputs from the instruction decoding unit such as the output from the second decoder 305. The output of the micro-decoder is mainly output to the data calculation unit 106, but some information, such as other preceding processing stop information due to execution of a jump instruction, is also output to other blocks.

(2, 4) r Operand Address Calculation Unit The operand address calculation unit 104 is hard-wired controlled by information related to operand address calculation output from the address decoder of the instruction decoding unit 102, etc. This block performs most of the processing related to operand address calculation. A check is also made to see if the memory access address and operand address for memory indirect addressing fall into the memory mapped I10 area.

The address calculation result is sent to the external bus interface section 107.
sent to. The general purpose register and program counter values necessary for address calculation are input from the data calculation section.

When performing a memory indirect adreno song, the address output circuit 108 outputs the memory address to be referenced to the outside of the CPU through the bus interface section 107, and the indirect address value input from the data input/output section 109 is sent through the instruction decoding section 102. fetch

(2, 5) rPC Calculation Unit” The PC calculation unit 103 is hard-wired controlled by information related to PC calculation output from the instruction decoding result 102, and calculates the pc value of the instruction. The data processing device of the present invention has a variable length instruction (), and the length of the instruction cannot be known unless the instruction is decoded.
The C calculation unit 103 creates the pc value of the next instruction by adding the instruction length output from the instruction lever 1 unit 102 to the pc value of the instruction being decoded, and the instruction decoding unit 102 decodes the branch instruction. When instructing a branch at the decode stage, the pc value of the branch destination instruction is calculated by adding the branch displacement to the pc value of the branch instruction instead of the instruction length. In the data processing apparatus of the present invention, branching is referred to as branching.

This Bribranch method is described in Japanese Patent Application Laid-Open No. 635963.
0 and JP-A-63-55639.

The calculation result of the P(J calculation unit 103 is output as the pc value of each instruction together with the decoding result of the instruction, and at the time of branching, it is output to the instruction fetch unit 101 as the address of the next instruction to be decoded. , is also used as an address for branch prediction of the instruction to be decoded next by the instruction decoding unit 102.

The branch prediction method is disclosed in detail in Japanese Patent Laid-Open No. 175934/1983.

(2,6) r data i'! The data calculation unit 106 is controlled by a microprogram, and uses registers and processors to execute operations necessary to realize the functions of each instruction according to the output information of the microROM unit 105. When the operand to be operated on is an address or an immediate value, the address or immediate value calculated by the operand address calculation unit 104 is passed through the external bus ink face unit 107 and obtained. In addition, when the operan 1' to be calculated is in the memory outside the CPU, the bus ink face unit outputs the address calculated by the address calculation unit +04 from the address output circuit 108 and fetches it from the memory outside the CPU. The operand is obtained from the data input/output circuit 109.

The equipment includes an ALU3+3, a barrel shifter, a priority encoder or counter, and a shift lane star. The registers and the main arithmetic unit are connected by three buses, and one microinstruction instructing one register-to-register operation is processed in two clocks (l steps).

When it is necessary to access memory outside the CPU during data calculation, the address is output from the address output circuit 108 to the outside of the CPU through the external bus interface section 1.07 according to instructions from the microprogram, and the address is output to the outside of the CPU through the data output circuit 109. Fetch data.

When storing data in a memory external to the CPU, an address is output from the address output circuit 108 through the external bus interface section 107, and at the same time, data is output from the data output circuit 109 to the outside of the CPU. In order to efficiently store operands, the data calculation unit 106
is equipped with a 4-byte store buffer.

When the data calculation unit 106 obtains a new instruction address by processing a jump instruction or exception handling, etc., this is transferred to the instruction fetch unit 101 and the PC calculation unit 103 (2, 7).
r External Bus Interface Unit The external bus interface unit 107 controls communication on the external bus of the data processing apparatus of the present invention. All memory accesses are performed in clock synchronization, with a minimum of 2 clock cycles (1 step)
It can be done with

Access requests to memory are made by the instruction file etch section 101.
, operand address calculation unit 104 and data calculation unit 1
Occurs independently from 06. External bus interface section 1
07 arbitrates these memory access requests. Furthermore, when accessing data at a memory address that straddles a 32-bit (1 word) aligned boundary, which is the data bus size that connects the memory and the CPU, it is automatically detected within this block that it straddles a word boundary. This is done by breaking it down into multiple memory accesses.

It also performs conflict prevention processing when the pre-fetch operand and store operand overlap, and bypass processing from the store operand to the fetch operand.

(3) “Pipeline mechanism” The pipeline processing function of the data processing device of the present invention is
As schematically shown in the figure.

The instruction fetch stage (IF
Stage) 201. Decode stage (D stage) 202 for decoding instructions. Operand address calculation stage (＾ stage) that calculates the address of the operand
203. Micro ROM access (especially R stage 20
Operand fetch stage (F stage) 204 . A five-stage configuration of an execution stage (E stage) 205 for executing instructions is the basis of pipeline processing.

E stage 205 has a 1-stage store buffer,
Some of the high-performance instructions pipeline the instruction execution itself, so there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and in theory the five stages operate completely independently.

Each stage can perform one process with a minimum of two clocks (one step). Therefore, ideally 2 clonks (
Pipeline processing progresses one after another for each step (1 step).

The data processing device of the present invention has some instructions that cannot be processed with just one basic pipeline process, such as memory-to-memory operations or memory indirect addressing, but the data processing device of the present invention can handle these processes. It is designed to perform pipeline processing as balanced as possible. An instruction having a plurality of memory operands is decomposed into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands, and pipeline processing is performed.

For information on how to decompose pipeline processing units, see Japanese Patent Application Laid-open No. 1983.
It is disclosed in detail in No.-89932.

The information passed from the IP stage 201 to the D stage 202 is the instruction code 211 itself. D stage 2
There are two types of information passed from 02 to the A stage 203: information related to the operation specified by the instruction (referred to as 0 code 212), and information related to operand address calculation (referred to as A code 213).

The information passed from the A stage 203 to the F stage 204 is an R code 214 that includes the microprogram entry address or microprogram parameters, and an F code 215 that includes the operand address and access method instruction information. .

The information passed from the F stage 204 to the E stage 205 is two types: an E code 216 including arithmetic control information and literals, and an S code 217 including operands or operand addresses.

An EIT detected at a stage other than the E stage 205 is a BIT until the code reaches the E stage 205.
Only instructions processed in the E stage 205 that do not start processing are instructions in the execution stage, and are not executed in the IF stage 203.
This is because the instructions being processed between F stage 204 and F stage 204 have not yet reached the execution stage. Therefore, when an EIT is detected at a stage other than the E stage 205, the fact that it has been detected is recorded in the step code and only transmitted to the next stage.

(3,1) r Pipeline Processing Unit" (3,1,1) r Instruction Code Field Classification" The pipeline processing unit of the data processing device of the present invention is determined using the formant characteristics of the instruction set. ing.

As described in section (1), the instructions of the data processing device of the present invention are variable length instructions in 2-byte units, and basically consist of a 2-byte instruction basic part and 0 to 4-byte addressing extension part. An instruction is constructed by repeating ~3 times.

In most cases, the basic instruction part has an operation code part and an addressing mode specification part, and if an index address song or memory indirect attlefsing is required, a "2-byte multi-stage indirect mode specification part" is used instead of the addressing extension part. Addressing extension section + 0 to 4 bytes of addressing extension are optionally added, and 2 or 4 byte
An instruction-specific extension of bytes is appended at the end.

The instruction basic part includes the instruction operation code, basic addressing mode, literal, etc. Addressing extensions include displacement, absolute address,
Either an immediate value or a displacement of a branch instruction. Instruction-specific extensions include a register map, immediate value specification for I-forsaL instructions, and the like. FIG. 35 is a schematic diagram showing the characteristics of the basic instruction formant of the data processing device of the present invention.

(3, 1, 2) Decomposition of instructions into r-step codes The data processing device of the present invention performs pipeline processing that takes advantage of the characteristics of the above-mentioned instruction formants.

In the D stage 202, ``2-byte instruction basic parts 〇 to 4
A byte atranging extension", "multi-stage indirect mode specification section atranging extension", or an instruction-specific extension are processed as one decoding unit. The decoding result of each time is called a step code, and from the A stage 203 onwards, this step code is used as a unit of pipeline processing. The number of step codes is unique for each instruction, and if the multi-stage indirect mode is not specified, one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes. When the multi-stage indirect mode is specified, the step code increases accordingly. However, as will be described later, this is only the decoding stage.

(3, 1, 3) r Program counter management J There is a possibility that all the step codes existing on the pipeline of the data processing device of the present invention are for different instructions,
Therefore, the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction that the step code is based on. The program counter value that is attached to the step code and flows through each stage of the pipeline is called a program counter (SPC). The SPC is passed between pipeline stages one after another.

(3, 2) r Processing of each pipeline stage The input/output step codes of each pipeline stage are named for convenience as shown in FIG. Further, the step code performs processing related to the operation code, and there are two series: a series that becomes the entry address of the microprogram and parameters for the E stage 205, and a series that becomes the operand for the microinstruction of the E stage 205.

(3, 2, 1) r Instruction fetch stage The instruction fetch stage (11' stage) 201 fetches instructions from the memory or branch buffer and stores them in the instruction queue 3.
01 and outputs the instruction code to the D stage 202. The input of the instruction queue 301 is an aligned 4-bye!・Do it in units. Fetching an instruction from memory requires a minimum of 2 clocks (l steps) per 4 aligned bytes.

If the branch buffer is hit, it can be fetched in 1 clock per aligned 4 bytes. The output unit of the instruction queue 301 is variable every 2 bytes, and up to 6 bytes can be output during 2 clocks. Immediately after a branch, the instruction queue 301 is bypassed and the instruction basic unit 2
It is also possible to transfer the bytes directly to the instruction decoder.

Control of registering and clearing instructions in the branch buffer,
The IF stage 201 also manages the address of the pre-fetch destination instruction and controls the instruction queue.

BITs detected in the IF stage 201 include bus access exceptions when fetching instructions from memory, address translation exceptions due to memory protection violations, and the like.

(3, 2, 2) r instruction decode stage” The instruction decode stage (D stage) 202 is the IF stage 201
Decodes the instruction code input from. Decoding is performed once every two clocks (one step) using the first decoder 303, which is a combination of the FIIW decoder, NFHW decoder, and addressing mode decoder of the instruction decoding unit 102. Byte of instruction code is consumed (instruction code is not consumed in output processing of step code including the return destination address of RET instruction, etc.), A stage 203 is consumed with one decoding.
A control code and address modification information, which are A code 213 as address calculation information, and a control code and 8-bit literal information, which are D code 212 as the intermediate decoding result of the operation code, are outputted.

The D stage 202 also performs control of the PC calculation unit 103 for each instruction, branch prediction processing, prebranch processing for prebranch instructions, and instruction code output processing from the instruction queue 301.

EITs detected at the D stage 202 include reserved instruction exceptions and odd address jump traps during pre-branch. Further, various BITs transferred from the IF stage 201 are encoded into step codes and transferred to the A stage 203.

(3, 2, 3) r operand address calculation stage”
Operand address calculation stage (A stage) 203
The processing functions are broadly divided into two. One is a process in which the second decoder 305 of the instruction decoding unit 102 is used to decode the operation code at a later stage, and the other is a process in which the operand address calculation unit 104 calculates an operand address.

The subsequent decoding process fl of the operation code receives the D code 212 and outputs the R code 214, which includes register and memory write reservations, the entry address of the microprogram, and parameters for the microprogram. Note that writing reservations for registers or memory are used to prevent incorrect address calculations due to the contents of registers or memory referenced in address calculations being rewritten by instructions that precede them on the pipeline. . In order to avoid deadlock, write reservations for registers and newts are made for each instruction rather than for each step code.Reservations for writing to registers and newts are described in detail in Japanese Patent Application No. 144394/1982.

The operand address calculation process takes A:1-F213 as input, performs address calculation in the operand address calculation unit 104 in accordance with the A code 213 by combining addition or memory indirect reference, and outputs the calculation result as the F code 215. At this time, a conflict check is performed when reading registers and memory during address calculation, and if a conflict is indicated because the preceding instruction has not finished writing to the register or memory, the preceding instruction executes the writing process at E stage 205. Wait until it finishes. Also,
It is also checked whether the operand address and the memory indirect reference address fall into the I10 area mapped to memory.

The EIT detected in the A stage 203 includes a reserved instruction exception,
In particular, there is a ``debug tranov'' using operand breakpoint hints during single instruction exceptions, bus access exceptions, address conversion exceptions, and memory indirect addressing.Please indicate that the D code 212 or A code 213 itself caused an EIT. For example, the A stage 203 does not perform address calculation processing on the code, but transmits the EIT to the R code 2]4 and the F code 215.

(3, 2, 4) r Micro ROM access stage
The operand fetch stage (F stage) 204 is also roughly divided into two processes. Is one Micro I? This is OM access processing, and is particularly referred to as R stage 206.

The other is operand prefetch processing, particularly referred to as OF stage 207. The R stage 206 and the OF stage 207 do not necessarily operate simultaneously, but operate independently depending on whether memory access rights can be acquired or not.

Micro ROM access processing, which is the processing of the R stage 206, is performed by sending the E code 216, which is an execution control code used for execution in the next E stage 205, to the R code 214.
These are micro ROM access and micro instruction decoding processing to generate the . When processing for one R code 214 is decomposed into two or more microprogram steps, the old microinstruction is used in the E stage 205, and the next R code 214 waits for access to the micro ROM. Micro ROM access to R code 214 occurs during the last micro instruction execution in the previous E stage 205. In the data processing device of the present invention, most basic instructions are executed in one microprogram step, so in reality, micro ROM accesses to the R code 214 are often executed one after another.

There is no new EIT detected in the R stage 206.

When the R code 214 indicates an instruction processing re-execution type BIT, the microprogram for that EIT processing is executed, so the R stage 206
Fetch the microinstruction according to 4.

If R code 214 indicates an odd address jump trap, R stage 206 sends it to E code 216.
convey by. This is for Bribranch,
In the E stage 205, if a branch does not occur in the E code 216, the branch is used to generate an odd address jump trap.

(3, 2, 5) r Operand Fetch Stage The operand fetch stage (OF stage) 207 performs operand prefetch processing of the above two processes performed in the F stage 204.

Operand briefetch takes F code 215 as input,
The fetched operand and its address are sent to S code 21.
Output as 7. One F code 215 specifies operand fetch of 4 bytes or less, although it may span word boundaries. The F code 215 also includes a designation as to whether or not to access the operand, and the A stage 203
When transferring the operand address itself or the immediate value calculated in , to the E stage 205, the operand prefetch is not performed, and the contents of the F code 215 are transferred as the S code 217. If the operand to be pre-fetched matches the operand to be written by the E stage 205, the operand pre-fetch is not performed from memory but is bypassed. Also, operand pre-fetch is delayed for the 70 area, and operand fetch is performed after waiting until all preceding instructions are completed.

EITs issued once in the OF stage 207 include bus access exceptions, address translation exceptions, and debug traps caused by breakpoint hits for operand briefetches. When F code 215 indicates a BIT other than debug tramp, transfer it to S code 217 and do not perform operand brief edge, F code 21
When 5 indicates a debug trap, the F code 215 is processed in the same way as if it does not indicate an EIT, and a debug trap is transmitted to the S code 217.

(3, 2, 6) r Execution Stage” The execution stage (E stage) 205 operates with the E code 216 and the S code 217 as input. This E stage 205 is a stage for executing instructions, and all processing performed in stages before the F stage 204 is preprocessing for the E stage 205. If a jump instruction is executed at E stage 205 or εIT processing is started,! All processes from F stage 201 to F stage 204 are invalidated. E stage 20
5 is controlled by a microprogram, R code 21
The instructions are executed by executing a series of microprograms starting from the microprogram entry address shown in 4.

Reading of the micro ROM and execution of micro instructions are performed in a pipelined manner. Therefore, when a branch occurs in a microprogram, one microstep becomes available. In addition, the E stage 205 includes the data calculation section 106
It is also possible to perform pipeline processing of operand store within 4 bytes and execution of the next microinstruction using the store buffer located in the .

In the E stage 205, the write reservation for registers and memory made in the A stage 203 is canceled after the operand is written.

Furthermore, if a conditional branch instruction issues a branch at the E stage 205, the branch prediction for that conditional branch instruction was incorrect, so the branch layer is rewritten.

EITs detected in the E stage 205 include bus access exceptions, address translation exceptions, debug traps, odd address jump traps, reserved function exceptions, illegal operand exceptions, reserved stack format exceptions, divide-by-zero traps, unconditional traps, and conditional traps. There are , delayed context traps, external interrupts, delayed interrupts, reset interrupts, and system failures.

All BITs detected in E stage 205! ! The 81 guns detected between IP stage 201 and F stage 204 before the E stage and reflected in the R code 214 or S code 217 are not necessarily subjected to the BIT process, although they are subjected to the IT process. 201
All EITs that are detected between F stage 204 and F stage 204 but do not reach E stage 205 due to reasons such as a jump instruction being executed at E stage 205 are canceled. This means that the instruction that caused the BIT was never executed in the first place.

External interrupts and delayed interrupts are processed at E stage 20 at the end of instructions.
5 is directly accepted, and the necessary processing is executed by the microprogram. Other various EIT processes are performed by microprograms.

(3, 3) rState control of each pipeline stage Each stage of the pipeline has an input launch and an output latch, and basically operates independently of other stages. Each stage finishes the previous processing and transfers the processing result from the output lunch to the input lunch of the next stage, and when all the input signals necessary for the next processing are available at the input lunch of the stage, the next start processing.

In other words, in each stage, all input signals for the next process output from the previous stage are valid, the current processing result is transferred to the input lunch of the next stage, and when the output latch becomes empty, the next process starts. Start.

All input signals must be available at the clock timing immediately before each stage starts operating. If the input signals are not ready, the stage becomes ambush B (waiting for input). When transferring from the output launch to the input latch of the next stage, the input latch of the next stage must be free, and even if the input latch of the next stage is not free, the pipeline stage will wait. The processing itself at each stage will be delayed if the pipeline enters the state (waiting for output), cannot acquire the necessary memory access rights, inserts a wait into the memory access being processed, or if other pipeline conflicts occur.

(4) Processing sequence of POP instruction: In the data processing device as described above, how the POP instruction is processed on the pipeline, when the destination is memory specified and when the destination is specified by Regisf. This will be explained in more detail separately with reference to the drawings.

A more detailed configuration of the data processing apparatus of the present invention is shown in the block diagram of FIG.

The instruction queue 301 is located in the instruction fetch unit 101,
Involved in the processing of the IF stage 201.

The first decoder 303 is located in the instruction decoding unit 102 and is involved in the processing of the D stage 202.

The second decoder 304 and the TMP register 310 are located in the instruction decoding unit 102 and are involved in the processing of the A stage 203. The ATMP register 310 is used to hold data read by memory access during memory indirection.

Address adder 305. AOIIT register 306. B
ASE register 307. The INDEX register 308, DISPI, and register 309 are located in the operand address calculation unit 104 and are involved in the processing of the A stage 203. BASE register 307°INDEX L, register 3
08. Ill5P L and register 309 are registers for holding a base value, an index value, and a displacement value, respectively. RASE Regis 9301
．． INDEX register 308. Adding the values of DISP L and register 309 at the same time is address addition 3114i.
It is i305. AOUT register 306 is a register for holding the output of address adder 305.

The ^SP register 311 is located in the stack pointer calculation unit and is involved in the processing of the A stage 203.

In order to prevent SP value conflicts due to pop operations from the stack, push operations to the stack, etc., the A stage 203 manages the ASP value, which is the SP value of the A stage, prior to the sp value of the E stage 205. . SP values accompanying pop and bush operations are updated by controlling A S P (!!) in the A stage 203. Therefore, by referring to ASP4fi, SP values can be updated even immediately after normal pop and bush operations. Processing can proceed without delay in stem code processing due to SP value conflicts.The ASP register 311 holds this ASP value.The method for managing SP values is disclosed in a patent application. 1986-14
It is disclosed in detail in No. 5852.

Micro l? A micro 10M unit 105 including an OM, a micro sequencer, a micro instruction decoder, etc. is involved in the processing of the R stage 206.

General-purpose register file 312. ALU313. The SO register 314 and the Do register 315 are
Located in 06, OF stage 207 and E stage 205
involved in the processing of The SD register 314 is a register for holding data read by memory access during operand fetching. DO Regisc 315 is E
This is a register for holding target data when the stage 205 reads or stores data in memory access.

IA register 316. FA register 317. The SA register 318 and the AA register 319 are part of the external bus interface section 107. The IA register 316 is a register that stores an address when the A stage 208 performs memory access during memory indirection.
The FA register 317 is a register that stores an address when the OF stage 207 performs memory access when fetching an operand. AA Regisc 319 is
The E stage 205 is a register that sets an address when reading or storing data in memory access.

The OF stage 207 sends the address together with the data fetched by the operand to the E stage 205, and the SA register 318 is a register for holding the address to be sent at this time. This SA register 318 is used not only to send an address but also to send an immediate value.

Note that the bus of the data processing device of the present invention includes a DD bus 2.
0. DISP bus 321. A bus 322. ^0 bus 3
23. ^A bus 324, Sl bus 325. S2 bus 3
26. There is Do Babasu 27.

The simplified configuration of the D stage 202 is shown in the block diagram of FIG.

The D stage 202 mainly includes the first decoder 303, as described above. This first decoding 30
3 is PLA (Programsable Logic
Array). When the instruction code 211 is input to the D stage 202, the first decoder 303
decoded by D code 212 and A code 21
3 is generated and output.

The D code 212 is given to a portion of the instruction decoding section 102 that performs the processing of the A stage 203, and the A code 213 is given to the portion of the operand address calculation section 104 that performs the processing of the A stage 203.

Note that 401 is an internal state holding latch.

The configuration of the portion of the instruction decoding unit 102 that performs the processing of the A stage 203 is shown in the block diagram of FIG.

This part is processed by the second decoder 304. Right register number generation unit 501. Left register number generation unit 502. Register number generation unit 503. It is composed of a size adjustment section 504 and the like. Note that the second decoder 304 is constructed of PLA similarly to the first decoder 303.

The input D code 212 is composed of the intermediate decoding result of the operation code, right register number information, left register number information, right register size -1, left register size -5, and the like.

The right register number information and the left register number information are input to a right register number generation unit 501 and a left register number generation unit 502, respectively, to generate a right register number R1 and a left register number R4, respectively. The right register number information includes information indicating whether the operand is the value on the register 1, the literal 1 value on the memory, or m (It).The left register number information includes information indicating whether the operand is the value on the register or Contains information indicating whether it is a literal.

The right register number R8 and the left register number RL are respectively associated with the first register specification part and the second register specification part in the instruction format, and the register numbers are used to specify the first and second operands, respectively.
Specifies the storage location of the operand. - Taking the R-FORMAT instruction shown in FIG. 14 as an example, Rn is the first register specification part and corresponds to the right register number;
s+ is the second register designation part and corresponds to the left register number.

On the instruction formant, it is not uniquely determined which of the first operand specification part and the second operand specification part is the source or destination.
Therefore, the second decoder 3 determines which of the right register number R5 and the left register number RL will be the source register number Rs and which will be the destination register number R0.
The register number generation unit 503 determines the register number control signal that is the output of the register number control signal 04.

In addition, the size generation unit 504 to which the size control signal that is the output of the second decoder 304 is applied, generates right register number information, which is the data size of the register indicated by the right register number R1, and data of the register indicated by the left register number RL. The left register size -L, which is the size, is determined by the source size -8 and the destination size 6, respectively.

In the F stage 204, the R code 21
4 and the F code 215 are sent to the F stage 204.

FIG. 6 and FIG. 7 show the register number generation unit 503, respectively.
and a circuit diagram showing the configuration of a size generation unit 504.

Input signals RCI, 1lc2 . RC3,R
C4 is the register number 'I output by the second decoder 304
This is a 4I+1 signal. In addition, the input signal S in FIG.
CI, SC2° SC3, SC4 are the second decoder 304
This is the size control signal output by

601.602,603,604,701,702,7
03 and 704 are N-channel transmission gates (TG), 605 are P-channel transmission gates (TG), and 606 are respectively
, 607 is an inverter, and 608 is an OR gate. Each circuit is composed of a launch whose input gate is a selector. Also, the circuit 610 has a P channel ↑
G605. Inverter 606. Inverter 607 and O
It is composed of an R gate 608.

The circuits 611, 710, and 711 are all connected to the circuit 610.
The configuration is equivalent to .

Note that in FIGS. 6 and 7, a circuit for one bit is shown for simplification. However, since the signal indicating the register number and the signal indicating the size are 5 bits and 2 bits, respectively, they are actually composed of circuits each having the corresponding number of bits.

FIG. 8 is a table showing the contents of the R code/F code output control signal, the register number control signal, and the size m signal output from the second decoder 304 shown in FIG. 5 at the time of the POP command.

Figure 9 Ta1. fbl is PO on the pipeline
3 is a flowchart showing a processing sequence of a P instruction.

FIG. 9(a) shows a flowchart when the destination memory designates memory. Also, Figure 9 Ta
1 is a flowchart when the destination is specified as a register.

Figure 10 fal, lb1. fcl, fdl, po
FIG. 7 is a schematic diagram showing the flow of step code processing in stages after the D stage when processing a p instruction. In the figure, the vertical axis represents time, and one scale corresponds to two clocks (one step).

Figures 10 (cat) and (bl) show the flow of step code processing when the destination is memory specified and register specified, and there is no wait state on the pipeline.

In Figure 1O, tc+ and fdl indicate that the destination is memory specified and register specified, respectively, and POP
E stage 205 is used to process the step code immediately before the instruction.
It takes 6 clofuku (3 steps) in
It shows the flow of step code processing when a wait state occurs in the step code of a P instruction.

FIG. 9 Ta1, (bl is a schematic diagram showing the instruction format of the POP instruction. I) The instruction format of the OP instruction is Gl-FORMAT shown in FIG. 17. FIG. 37(5) shows the case of register indirect addressing. General-purpose register number Rn specified here
indicates the referenced general-purpose register. Further, FIG. 37 fbl shows the case of register direct addressing. The general-purpose register number specified here indicates the destination general-purpose register.

The POP instruction is an instruction for transferring data on the top of the stack to a memory or register, and is therefore substantially equivalent to a transfer instruction between memory registers or between memory and memory. Therefore, the data processing device of the present invention generates a step code for processing the source operand section even though there is no source operand specification section, and performs all necessary preprocessing before the E stage. It is configured.

Below, Fig. 9 Ta1. This will be explained with reference to the fbl flowchart.

(4, 1) When the r destination specifies memory” First, the IF stage 201 fetches a POP instruction from memory and inputs it to the instruction queue 301, and the D stage 202
The instruction code 2+1 of the POP instruction is output for the POP instruction.

In the D stage 202, the POP instruction fetched by the IF stage 201 is decoded by the first decoder 303.

The instruction code 211 of the POP instruction is input to the first decoder 303 and decoded, and the first step code (1-1) of the POP instruction is generated. A part of the decoded result is held in internal state holding latch 401 as an internal state signal.

In the next decoding cycle, the internal state holding lunch 40
1, the first decoder 303
generates the second step code (1-2) of the POP instruction without taking in the instruction code 211 from the IP stage 201. In this way, as shown in FIG.
Two step codes are generated.

Although there is no source operand specification part in the POP instruction, it is implied that the source operand is the top of the stack as a function of the instruction. Therefore, in the data processing apparatus according to the present invention, a step code <1-2) for pre-processing a source operand is generated at the stage of decoding a POP instruction.

Each step code output by the D stage 202 is composed of an A code 21.3 and a D code 212. A code 213 in the same step code
and the D code 212 are sent to the A stage 203 at the same time. The step code generated from the pop instruction is A
The steps are sent to stage 203 in the order of step food (11) and step code (1-2).

Processing in subsequent stages will be explained for each step code.

(4, 1, 1) r Processing of the first step code (1-1) of the POP instruction” The A stage 203 inputs the A code 213 and the D code 212.

When the A code 213 is input to the A stage 203, the A
At stage 203, address calculation is performed under the control of the control signal of A code 213. The value in the referenced general-purpose register of the general-purpose register file 312 is transferred from the A bus 322 to the BASE register 307 based on the referenced register information.
is stored in A code 2 of step code (1-1)
The rNI)EX register 308 and the DISP register 309 are cleared by the control signal contained in the register 13.

The values of these three registers are added by address adder 305 and the result is stored in AOUT register 306. Further, the value in the AOut register 306 is sent to the FA register 317 via the ^O bus 23. F.A.
The value from the referenced general-purpose register in the register 317 is added to the F code 21 along with a portion of the output of the second decoder 304.
It becomes 5.

As shown in FIG. 8, the second decoder 304
When the intermediate decoding result of step 2 is input, a microprogram entry address or various control information is generated.

Further, the right register number information and the left register number information axis in the D code 212 are respectively stored in the right register number generation unit 501.
and is input to the left register number generation unit 502, which generates the right register number R9 and the left disc number RL. p
In the step code (1-1) of the op instruction, only the right register number R1 has meaning and indicates the S register 318, and the right register size h indicates a word.

The control information output by the second decoder 304 includes a register number control signal and a size control signal.

The register control signal indicates that the right register number corresponds to the destination register number R11, and the size control signal indicates that the right register size 6 corresponds to the destination register size W.

Register number control signals RCL, RC2, RC3, RC4
Among them, only RC3 is enabled, and N-channel TG
Only 603 is held as ONL, and right register number R11 is held as destination register number 11+. Also, among the size control signals SCI, SC2, SC3, and SC4, only SC3 is enabled, and N channel τG7
Only 03 is held as 01, and right register size 6 is held as destination register size W0.

In this way, in step code (1-1), destination register number Rob! SD register 318 and destination register size W.

indicates a word.

An R code 214 is generated from the entry address and register number of these microprograms.

R code 214 and F code 21 generated in this way
5 is sent to the F stage 204 at the same time.

When the R code/F code valid 1ε is enabled, the R stage 206 inputs the R code 214 and accesses the micro ROM 105 using the entry address of the micro program included in the R code 214. The output of the microphone 0RQF 1105 is decoded and becomes an E code 216 along with the register number and the like. This E code 216
destination register number R.

The register indicated by is the SD register 314, and the destination register size -9 is a word.

When the R code/F code valid signal is enabled, the OF stage 207 inputs the F code 215, and the value in the FA register 317, which is a part of the F code 215, is SA.
It is transferred to register 31B. The value in S^register 318 is sent to E stage 205 as S code 217.

When the E code 216 and S code 217 are input to the E stage 205, a process is performed in which the value in the SA register 318 is stored in the AA register 219. In this case, the register indicated by the destination register number R is the SD register 314, but this value has no meaning since it is a write operand. Therefore, the value in SA register 318 is only transferred to ^A register 3+9.

As described above, the step code (1-1) is sequentially processed on the pipeline.

(4, 1, 2) r Processing of second step code (1-2) of POP instruction” The A stage 203 inputs the A code 213 and the D code 212.

When the A code 213 is input to the A stage 203, the address calculation is performed in the forward stage 203 under the control of the control signal in the A code 213. A value is output from the SP register 311, which is the stack pointer of the A stage 203, onto the A bus 322 and stored in the BASE register 307. INDEX register 308 and DIS
P register 309 is cleared. RASε register 3
The values of the 07° INDEX register 308 and DISPI register 309 are added by the address adder 305, and the result is stored in the AOUT register 306. By this operation, the contents of the ASP register 311 are transferred to the 00 register 306. At the same time, ASP register 31
1 is incremented by +4. Additionally, the value in the AO[JT register 306 is sent via the ^0 bus 323 to the FA register 31.7.

The ASP value in the FA register 317 is sent to the second decoder 3.
It becomes F code 215 along with a part of the output of 04.

As shown in FIG. 8, the second decoder 304
When the intermediate decoding results of step 2 are input, the entry address of the microprogram and various control jB information are generated.

Further, the right register number information and the left register number information in the D code 212 are respectively generated by the right register number generation unit 50.
1 and left register number generation unit 502, and a right register number R1 and a left register number RL are generated.
In the second step code (12) of the POP instruction, only the right register number has meaning, and the SD register 51
4, right register size 6 indicates word.

This right register number information is not specified in the instruction formant, but in this step code (1, -2).
It is generated in the D stage 202 at the time of generation.

The control information output by the second decoder 304 includes register number control information and size control information. Register number system f: The Jl signal indicates that the right register number R, corresponds to the source register number R. In addition, the size control signal is such that the right register size h is the source register size h
Indicates that it corresponds to

Renostar number system wholesale signal RC1, RC2, RC3, RC
4, only RCI is enabled, and N channel T
Only G601 is ON, right register number +1. is held as source register number R3. The destination register number Ro remains the number held during processing with step code (1-1). Also, among the size control signals SCI, SC2, SC3, and SC4, only SCI is enabled, and only N channel TG701 is ONL.
, right register size 6 is held as source register size 6.

Thus, in the step code (+-2), the source register number Rs indicates the SD register 314, and the source register size -3 indicates a word.

R code 21.4 is generated from the entry address and register number of these microprograms.

The R code 214 and F code 215 generated in this way are simultaneously sent to the F stage 204.

When the R code/F code enable signal is enabled, the R stage 206 inputs the R code 214 and accesses the micro ROM 105 using the entry address of the micro program included in the R code 214. The output of micro RO old 05 is decoded and becomes E code 216 along with the register number etc. This step code (1-
The register indicated by the source register number R8 in 2) is the SD register 314, and the source register size is a word.

OF stage 207 inputs F code 215 when the R code/F code enable signal is enabled. The value of FA register 3+7, which is part of the F code 215, is the SP value of this instruction. Then, using the value of the FA register 317 as an address value, the external lotus interface unit 10
7 to the top of the stack. In this access to the top of the stack, the briefetched value is read into the data processing device of the present invention via the external bus interface section 107 and transferred from the DO bus 20 to the SD register 314.
is maintained.

The value in the S register 314 is sent to the E stage 205 as part of the S code 217.

E stage 205 has E code 216 and S code 21
When 7 is input, processing is performed to transfer the value in the register indicated by the source register number R1 using the value of the A^ register 319 as the destination address. In this case, the register indicated by source register number R5 is SD
This is a register 314. Therefore, the first two clocks (l
S prefetched from the top of the stack at step)
The value in the D register 314 is transferred from the AL bus 325 to the
Sent to υ313 and sent to 00 bus 327 without being calculated.
It is transferred to the DO register 315 from above.

The data sent to the DO register 315 in the next two clocks (1 step) is sent to the external bus interface unit 107 using the value in the ^A register 319 held by the processing of step code (1-1) as the destination address.
stored via.

At E stage 205, basically the second ASP instruction
Step code (1-2) requires 4 clocks (2 steps) to process. However, since data calculation and storage are pipelined, processing of the next instruction may start during the data storage process, and in this case, only two clocks (l steps) are required for processing. .

As described above, step codes (1-2) are sequentially processed on the pipeline mechanism.

In the data processing device of the present invention, as shown in FIG. , the load distribution of each stage is sufficient when processing a POP instruction (4, 2)
r When destination is specified as a register” Atregi 7
When the sing mode is the register direct mode, processing regarding the destination operand can be simplified because the destination is a general-purpose register.

In the following, it will be explained in detail how the processing regarding the destination operand is simplified when the registering mode of the POP instruction is the register direct mode.

It is assumed here that the register number of the general-purpose register serving as the destination is R3. Therefore, Fig. 37 (
The general-purpose register number Rn of bl is R1.

First, the IF stage 201 fetches a POP instruction from memory and inputs it into the instruction queue 211, and then the D stage 20
2, the instruction code 211 of the POP instruction is output.

In the D stage 202, the POP instruction fetched by the IF stage 201 is decoded by the first decoder 303.

The instruction code 211 of the POP instruction is input to the first decoder 303 and decoded to generate the first step code (2-1) of the POP instruction. A part of the decoded result is held in internal state holding latch 401 as an internal state signal.

In the next decoding cycle, the internal state holding latch 40
In response to the internal state signal from IF stage 201, first decoder 303 does not take in the instruction code 211 from IF stage 201 and generates the second step code (2-2) of the POP instruction. In this way, two step codes are generated as shown in FIG. 9tb).

Although there is no source operand specification part in the instruction, it is implied that the source operand is the top of the stack as a function of the instruction. In the data processing device of the present invention, P
At the stage of decoding the OP instruction, a step code (2-2) is generated to perform processing related to the source operand in advance.

Each step code output from the D stage 202 is composed of an A code 213 and a D code 212. A code 213 in the same step code
and the D code 212 are sent to the A stage 203 at the same time. The step code generated from the pop instruction is A
The step code (2-1>) is sent to the stage 203 in the order of step code (2-2).

Processing in subsequent stages will be explained for each step code.

(4, 2, 1) r Processing of the first step code (2-1) of the POP instruction” The A stage 203 inputs the A code 213 and the D code 212. However, A code 213 is A stage 20
3, address calculation processing is not performed because it is in register direct mode.

As shown in FIG. 8, the second decoder 304
When the intermediate decoding results of step 2 are input, the microprogram entry address and various control information are generated.

Further, the right register number information and the left register number information in the D code 212 are respectively generated by the right register number generation unit 501.
and is input to the left register number generation unit 502, and a right register number R11 and a left register number RL are generated.
In the step code (2-1) of the pop instruction, only the right register number Re has meaning and indicates general-purpose register R1 in the general-purpose register file, and the right register size h indicates a word.

The control information output by the second decoder 304 includes register number control information and size control information. The register number control signal indicates that the right register number R8 corresponds to the destination register number R, and the size control signal indicates that the right register size also corresponds to the destination register size -8.

Register number control signals RCI, RC2, l? C3,RC
Only RC3 is enabled in I, and N channel T
Only G603 is held as ONL, and the right register number is held as destination register number R. Also, among the size control signals SCI, SC2, SC3, and SC4, S
Only C3 is enabled, only N channel TG 703 is ONL, and right register size W8 is held as destination register size.

As described above, in the step code (2-1), the destination register number R0 indicates the general-purpose register R4, and the destination register size 6 indicates a word.

Since the addressing mode is register direct addressing, the second decoder 304 does not enable the R code/F code enable signal.

Therefore, the F stage 204 is a step code (2 to l)
In other words, step code (2-1) is A
It disappears at stage 203.

Destination register number R, and destination register size G. continues to be retained to be passed to the step code (22).

If the addressing mode is other than register direct mode, the step code (2-1) that performs processing regarding the destination operand is E stage 2.
05, the destination address value is saved in the A^ register 219. However, since it is in register direct mode, there is no need to perform this process.
Therefore, in the data processing apparatus of the present invention, when processing a POP instruction whose addressing mode is register direct mode, the step code (2-1) is deleted.

(4, 2, 2) r Second step of POP instruction, processing of decoding (2-2)” The A stage 203 inputs the A code 213 and the D code 212. When the A code 213 is input to the A stage 203, the A stage 203 performs address calculation under the control of the control signal in the A code 213.

The value is output from the ASP register 311, which is the stack pointer of the A stage 203, onto the A bus 322, and
It is stored in the ASE register 307. INDEX register 308 and old SP register 309 are cleared.

BASE register 307. INDEX register 308
and the value of the DISP register 309 is the address adder 30
5 and the result is stored in the AOIJT register 306. By this operation, the contents of the ASP register 311 are transferred to the 〇〇T register 306. At the same time A
SP register 311 is incremented by +4. Further, the value in the AOtlT register 306 is sent to the FA register 317 via the AO bus 23. FA register 3
asP(a in 1.7 becomes the F code 215 together with a part of the output of the second decoder 304.

As shown in FIG. 8, the second decoder 304
When the intermediate decoding results of step 2 are input, the microprogram entry address and various control information are generated.

Further, the right register number information and the left register number information in the D code 212 are respectively generated by the right register number generation unit 501.
and is input to the left register number information section 502, and the right register number and left register number 1. is generated. POP
In the step code (2-2) of the instruction, only the right register number R6 has meaning and indicates the SO register 314, and the right register size h indicates a word. The register number information is not specified in the instruction formant, but is generated at the D stage 202 when this step code (2-2) is generated.

The control information output by the second decoder 304 includes register number control information and size control information. The register number 1til control signal indicates that the right register number R# corresponds to the source register number R5, and the size control signal indicates that the right register size h corresponds to the source register size 6.

Register number control signal 1? cl, l? c2. R.C.
3. Among RC4, only RCl is enabled, only N channel TG 601 is held as ONL, and right register number R1 is held as source register number R8. The destination register number plate is the step code (2-3)
The number retained during processing remains the same. Also, among the size control signals SCI, SC2, SC3, and SC4, SC
Only I is enabled, only N channel TG 701 is ON, and right register size 6 is held as source register size -3. The destination register size j1m remains the size held during processing in step code (2-1).

In this way, in the step code (2-2), the destination register number R, indicates general-purpose register R1,
Source register number R8 indicates SD register 3!4,
Also, the destination register size -D indicates a word, and the source register size U indicates a word. Therefore, part of the information in the step code (2-1) is absorbed into the step code (2-2). .

Further, in the register direct mode, the second decoder 304 inverts and outputs the lower one pin of the entry address of the microprogram. Therefore, the microinstruction processing is different depending on whether the destination address is a register or not.

An R code 214 is generated from the entry address and register number of these microprograms.

The R code 214 and F code 215 generated in this way are simultaneously sent to the F stage 204.

When the R code/F code enable signal is enabled, the R stage 206 inputs the R code 214 and accesses the micro ROMI (15) at the entry address of the micro program contained therein.
The output of 105 is decoded and sent to E along with the register number etc.
The code becomes 216. The register indicated by the source register number R3 of this step code (2-2) is the SD register 314, and the register indicated by the destination register number R is the general-purpose register R1. Also, the source register size and the destination register size. are both words.

OF stage 207 inputs F code 215 when the R code/F code enable signal is enabled. The value in FA register 317, which is part of F code 215, is the SP value of this instruction. Using the value in the FA register 317 as an address, an operand is prefetched to the top of the stack via the external bus interface unit 107. By accessing this stack top, the value briefetched is transferred to the external bus interface unit 107.
is read into the data processing device of the present invention via the DO
It is held in the SD register 314 from the bus 20. S
The value in D register 314 is sent to E stage 205 as part of S code 217.

When the E stage 205 receives the E code 216 and the S code 217, processing is performed to transfer the value in the register whose source register number P is not indicated to the register indicated by the destination register number R.

In this case, the register indicated by destination 1/register number R8 is a general-purpose register, and the register indicated by source register number Rg is the SD register 314. Therefore, the value in the SO register 314 briefetched from the top of the stack is sent from the Sl bus 325 to the ALU 313, and transferred from the DO bus 27 to the general-purpose register R5 without being operated.

As described above, the step code (2-2) is sequentially processed on the pipeline mechanism.

In the data processing 'JAW' of the present invention, if there is no waiting state on the pipeline mechanism, the step code (2-1) and step code (2-2) of the POP instruction are During this time, the step code (2-1)) disappears at the A stage 203, and only the necessary information is absorbed into the step code (2-2), as shown in FIG. a
As shown in l and fbl, there is no waiting state on the pipeline mechanism, and data storage in the E stage 205 is different between when one of the step codes of the POP instruction is absorbed and when no step code is absorbed. Except for the motion, the number of steps required for the process is the same.

Here, the step code (
4-1) requires three steps to process at the E stage 205, so consider a case where the step code of the POP instruction enters a two-step wait state at the F stage 204.

Figure 1O (C1 shows the case where the step code of the POP instruction is not absorbed, and Figure 1O (d+ shows the case where one of the step codes of the POP instruction is absorbed).

As understood from Fig. 1Ofd+, the step code (
2-1> has been absorbed, the number of step codes to be processed in the E stage 205 is reduced, and as a result, the number of steps required for the entire process is reduced.

In this way, absorbing unnecessary step code (2-1) on the pipeline mechanism reduces the number of steps required for processing when a wait state occurs on the pipeline mechanism. There is great potential to improve the processing speed of data processing devices.

[Effects of the Invention 1] As detailed above, according to the data processing device of the present invention, a processing unit related to the source operand implied by the POP instruction is generated, and that processing unit is subjected to pipeline processing. Very balanced pipeline processing is possible when processing POP instructions, and the overall processing speed is improved.

In addition, POP, which is a register direct addressing mode,
Since the configuration is configured to eliminate processing units that do not need to be performed in the execution stage when processing instructions, if a wait state occurs on the pipeline mechanism, the processing steps required when executing a P-order instruction in register direct mode are The number of execution stages is reduced, the time occupied by the execution stage for the processing is reduced, and the processing speed of the data processing device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data processing device of the present invention, and FIG. 2 is a pipeline i of the data processing device of the present invention.
FIG. 3 is a block diagram showing a more detailed structure of the data processing device of the present invention, and FIG. 4 is a block diagram showing the structure of the decoding (0) stage of the data processing device of the present invention. FIG. 5 shows instruction lever 1 at the operand address calculation (A) stage of the data processing device of the present invention.
Figure 6 is a circuit diagram showing the configuration of the register number generation unit in Figure 5, and Figure 7 is a circuit diagram showing the configuration of the size generation unit in Figure 5. 8 shows the R code/F code valid signal which is the output of the second decoder in FIG. 5, and the register number system? 11
The contents of the signal and size control Tg signal are shown (, Figure 9 fat, (bl is a flowchart showing the processing sequence of the POP instruction on the pipeline mechanism, Figure 10 (al, ibl, (cl,
((11 is a schematic diagram showing the flow of step code processing in stages after the D stage of the pop instruction, FIG. 11 is a block diagram showing the configuration of the pipeline mechanism in a conventional data processing device, and FIG. A schematic diagram showing a typical format of the instruction format of the data processing device of the invention, FIG. 13 is a schematic diagram showing the abbreviated format of an inter-memory-register operation instruction, and FIG. 14 is an abbreviated format of an inter-register operation instruction. Schematic diagram showing 1st
Figure 5 is a schematic diagram showing the shortened format of a literal-to-memory operation instruction, Figure 16 is a schematic diagram showing the shortened format of an immediate-memory operation instruction, and Figure 17 is a schematic diagram of the one-ship format of an l-operand instruction. FIG. 18 is a schematic diagram showing a single-ship format of an instruction in which the first operand of a two-operand instruction requires a memory read,
FIG. 19 is a schematic diagram showing a one-ship format in which the first operand of a two-operand instruction is an 8-bit immediate value instruction.
Figure 20 is a schematic diagram showing the single-ship format in which the first operand of a two-operand instruction is an instruction that only performs address calculation, Figure 21 is a schematic diagram showing the short branch instruction format, and Figure 22 is addressing mode specification. Figure 23 is a schematic diagram showing a format in which the addressing mode designation part is in register direct mode, Figure 24 is a schematic diagram showing a format in which the addressing mode designation part is in register relative indirect mode. FIG. 25 is a schematic diagram showing a format in which the addressing mode specification section is the immediate value mode. FIG. 26 is a schematic diagram showing a format in which the addressing mode specification section is in the absolute mode. Figure 27 is a schematic diagram showing a format in which the addressing mode designation part is PC relative indirect mode, Figure 28 is a schematic diagram showing a format in which the addressing mode designation part is Stankbop mode, and Figure 29 is an addressing mode. A schematic diagram showing a format in which the designation part is in stacked bush mode, FIG. 30 is a schematic diagram showing a format in register pace multi-stage indirect mode, and FIG.
A schematic diagram showing a C-based multi-stage indirect mode formant,
Figure 32 is a schematic diagram showing the format of the absolute base multi-stage indirect mode, and Figure 33 is a schematic diagram showing the format of the one-stage multi-stage indirect mode, including addition of displacement IIt, direct scaling and addition of index I, and memory indirect reference. FIG. 34 is a schematic diagram showing the designation field; FIG. 34 is a schematic diagram showing variations on whether or not the multi-stage indirect mode continues; FIG.
The figure is a schematic diagram showing variations in the size of the displacement unit I, FIG. 36 is a schematic diagram showing the basic command format of the data processing device of the present invention, and FIG. 37 (8)
, (bl is a schematic diagram showing the instruction format 77 of the POP instruction. 201... Instruction fetch stage 202... Memory decode stage 203... Operand address calculation stage 204... Operand fetch stage 205. ...Execution stage 211...Instruction code 212...D code 213...A code 30
3...Seventeenth coder 304...Second decoder Note that the same reference numerals in each figure indicate the same or corresponding parts. diagram

Claims (1)

[Scope of Claims] 1. A memory system comprising a mechanism for pipeline processing of instructions through a plurality of stages including a first stage for decoding the instructions and a second stage for processing subsequent to the first stage; In a data processing device having a pop instruction that writes the value of a first operand read from a predetermined area above to an arbitrarily specifiable second operand, when the pop instruction is input to the first stage. a first unit processing code including information for decoding this and processing the second operand;
1. A data processing device comprising decoding means for generating a second unit processing code including information for processing an operand of and outputting the generated second unit processing code to the second stage. 2. A plurality of stages including a first stage for decoding an instruction, a second stage for processing following the first stage, and a third stage for processing following the second stage; In the data processing device, the first stage is equipped with a mechanism for pipeline processing, and has a pop instruction that writes the value of a first operand read from a predetermined area on memory to an arbitrarily specifiable second operand. a first unit processing code including information for decoding the pop instruction and processing the second operand when the pop instruction is input;
a first decoding means for generating a second unit processing code including information for processing an operand and outputting it to the second stage; when the second operand is a specific register;
The present invention further includes a second decoding means for processing the first and second unit processing codes inputted to the second stage to generate one unit processing code and outputting the same to the third stage. Characteristic data processing device.