JPH0769808B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is a data device that realizes a high processing capacity by efficiently operating a multi-stage pipeline processing mechanism by a branch instruction processing mechanism that reduces disturbance of the pipeline. It is about.

[Conventional technology]

FIG. 5 shows an example of a pipeline processing mechanism used in a conventional data processing device. (11) is the instruction fetch stage (IF stage), (12) is the instruction decode stage (D
Stage), (13) is an operand address calculation stage (A stage), (14) is an operand fetch stage (F stage), and (15) is an instruction execution stage (E stage).

The IF stage (11) fetches the instruction code from the memory and outputs it to the D stage (12). D stage (12) is IF
The instruction code input from the stage (11) is decoded and the decoding result is output to the A stage (13). The A stage (12) calculates the effective address of the operand specified in the instruction code, and outputs the calculated operand address to the F stage (14). The F stage (14) fetches the operand from the memory according to the operand address input from the A stage (13). The fetched operand is output to the E stage (15). The E stage (15) executes the operation specified in the instruction code on the operand input from the F stage (14).
If necessary, the calculation result is stored in the memory.

By the above pipeline processing mechanism, the process designated by each instruction is decomposed into five, and the designated process is completed by sequentially executing the five processes. Each of the five processes can be operated in parallel for different instructions. Ideally, if the above five-stage pipeline processing mechanism processes five instructions at the same time, and pipeline processing is not performed. Compared to this, it is possible to obtain a data processing device having a maximum processing capacity of 5 times.

[Problems to be Solved by the Invention]

The pipeline processing technology has the potential to significantly improve the processing capacity of the data processing device as described above.
Widely used in high-speed data processing equipment.

However, pipeline processing also has some drawbacks,
Instructions are not always processed in ideal conditions.
One of the problems in pipeline processing is the execution of branch instructions that disturb the sequence of instructions.

In the conventional data processor having the pipeline processing mechanism shown in FIG. 5, the branch instruction is processed by the E stage (15) and then the branch target instruction is processed by the IF stage (11). The pipeline is significantly disturbed. FIG. 6 shows a state of an instruction flowing in a pipeline when a branch instruction is executed in a conventional data processing device. In FIG. 6, instruction 3 and instruction 12 are branch instructions. When the instruction 3 is executed, the instruction 4, the instruction 5, the instruction 6, and the instruction 7 which are already pipelined are canceled, and the instruction 11 is newly processed from the IF stage (11). Instruction 3 is E stage (15)
The time corresponding to the processing of four instructions is wasted until the instruction 11 is executed at the E stage (15) after being executed at. Similarly, for the instruction 12, the time for processing four instructions is wasted. This dead time is because the fetch of the instruction to be processed after the execution of the branch instruction is performed after the completion of all the pipeline processing for the branch instruction, and the larger the number of stages of the pipeline processing, the longer the dead time.

It has been pointed out that the processing of branch instructions is one of the key points for improving the processing capability of a data processing device that performs pipeline processing, and various measures have already been taken. Some ideas for processing branch instructions include JK
F. Lee, AJ Smith, `` Branch Prediction Strategies and
Branch Target Buffer Design '', IEEE Computer, Vo1.1
7, NO.1.January, 1984. However, any of the devises require a large amount of hardware to realize,
There were still many drawbacks, such as the effect only on some branch instructions.

[Means for Solving the Problems]

In order to solve the above-mentioned drawbacks, the data processor of the present invention has an instruction decoding mechanism capable of predicting a branch depending on a history of conditional branch instructions and an instruction code of other instructions, and a branch destination. It has a program counter value calculation mechanism capable of calculating an address and an operand address calculation mechanism capable of adding the instruction length of a branch instruction and the program counter value of a branch instruction.

[Action]

In the data processing device of the present invention, the conditional branch instruction depends on the history and the other instructions depend on the instruction code, and an instruction decoding mechanism capable of predicting a branch and a branch destination address are calculated. An unconditional branch instruction, a conditional branch instruction, a subroutine branch instruction, and a loop are provided by a program counter value calculation mechanism that is capable of calculating and a operand address calculation mechanism that can add the instruction length of a branch instruction and the program counter value of a branch instruction. The control instruction is subjected to branch processing at the instruction decoding stage to reduce disturbance in pipeline processing.

Example of Invention

(1) Instruction format of the data processing device of the present invention The instruction of the data processing device of the present invention has a variable length in units of 16 bits, and there is no instruction of odd byte length.

The data processor of the present invention has a particularly devised instruction format system in order to make a high-frequency instruction into a short format. For example, for a two-operand instruction, there are basically two formats: a general format that has a structure of 4 bytes and an extension part and can use all addressing modes, and a short format that can use only frequently used instructions and addressing modes. There is a format.

The meanings of the symbols appearing in the instruction format of the data processor of the present invention shown in FIGS. 8 to 17 are as follows.

-: Part containing opcode #: Part containing literal or immediate value Ea: Part specifying operand in 8-bit general addressing mode Sh: Part specifying operand in 6-bit short addressing mode Rn: Register The partial format that specifies the above operand by the register number is the LSB side on the right side, as shown in Fig. 8.
And the address is high. The instruction format cannot be distinguished unless the two bytes of the address N and the address N + 1 are seen. This is because it is premised that the instruction is fetched and decoded in units of 16 bits (2 bytes). .

In the data processor of the present invention, the extension of Ea or Sh of each operand is always placed immediately after the halfword including the basic part of Ea or Sh in any format. This takes precedence over immediate data implicitly specified by the instruction and the extension of the instruction. Therefore, for an instruction of 4 bytes or more, the operation code of the instruction may be divided by the extension part of Ea.

Also, as will be described later, the multi-stage indirect mode
Even if the extension part of Ea has an extension part, that part has priority over the next instruction opcode. For example, consider the case of a 6-byte instruction with Ea1 in the first halfword, Ea2 in the second halfword, and up to the third halfword. Since the multistage indirect mode is used for Ea1, the extension part of the multistage indirect mode shall be attached in addition to the ordinary extension part. At this time, the actual instruction bit pattern is the first halfword of the instruction (including the basic part of Ea1), the extension part of Ea1, and Ea1.
Multistage indirect mode extension of 1, second halfword of instruction (E
a2 including the basic part), Ea2 extension, the third halfword of the instruction, in that order.

(1.1.) Short two-operand instructions are shown in Figures 9-12. It is a shortened format of a two-operand instruction.

FIG. 9 shows the format of the arithmetic instruction between memory registers. This format has an L-format in which the source operand side is the memory and an S-format in which the destination operand side is the memory.

In the L-format, Sh represents the designation field of the source operand, Rh represents the designation field of the register of the destination operand, and RR represents the designation of the operand size of Sh. The size of the destination operand placed in the register is fixed at 32 bits. Sign extension is performed when the size of the register side is different from that of the memory side and the size of the source side is small.

In S-format, Sh represents the destination operand specification field, Rh represents the source operand register specification field, and RR represents the Sh operand size specification.
The size of the source operand placed on the register is 32.
It has been fixed to a bit. When the size of the register side is different from that of the memory side and the size of the source side is large, the overflow portion is truncated and overflow chuck is performed.

FIG. 10 shows the format (R-format) of a register-register operation instruction. Rn is a designation field of the destination register Rm is a designation field of the source register. Operand size is only 32 bits.

FIG. 11 shows the format (Q-format) of a literal-memory operation instruction. MM is a destination operand size specification field, # is a literal source operand specification field, and Sh is a destination operand specification field.

Figure 12 shows the format of the immediate-memory operation instruction (I-fo
rmat). MM is an operand size specification field (common to the source and destination), and Sh is a destination operand specification field. I-form
The size of the immediate value of at is 8,16,32 bits in common with the size of the operand on the destination side, and zero extension,
No sign extension is performed.

(1.2) General-purpose 1-operand instruction Figure 13 shows the general-purpose format of the 1-operand instruction (G1-f
ormat). MM is a field for specifying the operand size. Some G1-format instructions have an extension part other than the extension part of Ea. Also, some instructions do not use MM.

(1.3) General type two-operand instruction Figures 14 to 16 show the general format of the two-operand instruction. Included in this format are instructions that have up to two operands in the general addressing mode specified by 8 bits. The total number of operands themselves may be three or more.

FIG. 14 shows the format (G-format) of the instruction in which the first operand requires memory reading. EaM is the destination operand specification field, MM is the destination operand size specification field, EaR
Is a source operand specification field, and RR is a specification field of the source operand size. Some G-format instructions have extensions other than the extensions of EaM and EaR.

FIG. 15 shows an instruction format (E-format) in which the first operand is an 8-bit immediate value. EaM is the destination operand specification field, MM is the destination operand size specification field, and # is the source operand value.

E-format and I-format are functionally similar, but
There is a big difference in the way of thinking. The E-format is a derivative of the 2-operand general type (G-format), and the size of the source operand is fixed at 8 bits and the size of the destination operand is selected from 8/16/32 bits. In other words, assuming arithmetic between different sizes,
The 8-bit source operand is zero-extended or sign-extended according to the size of the destination operand. On the other hand, the I-format is a shortened form of an immediate value pattern that is frequently used especially for transfer instructions and comparison instructions, and the source operand and the destination operand have the same size.

FIG. 16 shows the format (GA-format) of the instruction whose first operand is only address calculation. EaW is a destination operand specification field, WW is a destination operand size specification field, and EaA is a source operand specification field. The execution address calculation result itself is used as the source operand.

FIG. 17 shows the format of the short branch instruction.
cccc is a branch condition designation field, disp: 8 is a displacement designation field with a jump destination, and 8 in the data processing device of the present invention.
When the displacement is designated by a bit, the designated value in the bit pattern is doubled to obtain the displacement value.

(1.4) Addressing Mode The addressing mode designating method of the data processing device of the present invention includes a shortened form that is designated by 6 bits including a register and a general form that is designated by 8 bits.

If an undefined addressing mode is specified, or if a combination of addressing modes that is obviously strange in terms of meaning is specified, a reserved instruction exception is generated and exception processing is started, as when an undefined instruction is executed. To do.

This corresponds to the case where the destination is the immediate mode, the case where the immediate mode is used in the addressing mode designation field which should accompany the address calculation, and the like.

The symbols used in the diagrams of the formats shown in FIGS. 18 to 28 are as follows.

Rn register specification (Sh) Specification method in 6-bit shortened addressing mode (Ea) Specification method in 8-bit general type addressing mode The part enclosed by the dotted line in the format diagram indicates the extension part.

(1.4.1) Basic Addressing Mode The data processing device of the present invention supports various addressing modes. Among them, basic addressing modes supported by the data processing device of the present invention include register direct mode, register indirect mode, register relative connection mode, immediate mode, absolute mode, PC relative indirect mode,
There are stack pop mode and stack push mode.

In the register direct mode, the contents of the register are directly used as the operand. The format is shown in FIG. Rn indicates the general register number.

In the register indirect mode, the content of the memory whose address is the content of the register is the operand. Format is first
Shown in Figure 19. Rn indicates the general register number.

There are two types of register relative indirect, depending on whether the displacement value is 16 bits or 32 bits. Each of them uses the contents of the memory whose address is a value obtained by adding a displacement value of 16 bits or 32 bits to the contents of the register as an operand. The format is shown in Fig. 20. Rn indicates the general register number. disp: 16 and disp: 32 represent a 16-bit displacement value and a 32-bit displacement value, respectively. The displacement value is treated as signed.

In the immediate mode, the bit pattern specified in the instruction code is regarded as a binary number as it is and is used as an operand. The format is shown in FIG. imm-data indicates an immediate value. imm-da
The size of ta is specified in the instruction as the operand size.

There are two types of absolute modes depending on whether the address value is indicated by 16 bits or 32 bits. The contents of the memory with the 16-bit or 32-bit bit pattern specified in the instruction code as an address are used as operands. The format is shown in FIG. abs: 16 and abs: 32 are
16-bit and 32-bit address values are shown, respectively. abs:
When the address is indicated by 16, the specified address value
Sign extend to 32 bits.

There are two types of PC relative indirect mode depending on whether the displacement value is 16 bits or 32 bits. The contents of the memory whose address is a value obtained by adding a displacement value of 16 bits or 32 bits to the contents of the program counter are used as operands. The format is shown in FIG.

disp: 16 and disp: 32 represent a 16-bit displacement value and a 32-bit displacement value, respectively. The displacement value is treated as signed. PC
The value of the program counter referred to in the relative indirect mode is the start address of the instruction including the operand. Even when the value of the program counter is referenced in the multi-stage indirect addressing mode, the address at the beginning of the instruction is used as the PC-relative reference value in the same manner.

In the stack pop mode, the content of the memory whose address is the content of the stack pointer (SP) is the operand. After the operand is accessed, SP is incremented by the operand size. For example, when handling 32-bit data,
SP is updated by +4 after operand success. B, H
It is also possible to specify stack pop mode for operands of size, and SP is updated by +1, +2 respectively. The format is shown in Fig. 24. If the stack pop mode has no meaning for the operand, a non-reserved instruction is generated. Specifically, what is outside the reserved instruction is the stack pop mode specification for the write operand and the read-modify-write operand.

In the stack push mode, the contents of the memory whose address is the contents of SP decremented by the operand size are the operands. In stack push mode, SP is decremented before operand access. For example, when handling 32-bit data, SP is updated by -4 before operand access. It is also possible to specify the stack push mode for operands of sizes B and H, and SP is updated by -1 and -2, respectively. The format is shown in Fig. 25. If the stack push mode has no meaning for the operand, a non-reserved instruction is generated. Specifically, what is outside the reserved instruction is the stack push mode specification for the read operand and the read-modify-write operand.

(1.4.2) Multi-stage indirect addressing mode Basically, complicated addressing can be decomposed into a combination of addition and indirect reference. Therefore, if complicated addition and indirect reference operations are given as addressing primitives and they can be arbitrarily combined, any complicated addressing mode can be realized. The multi-stage indirect addressing mode of the data processing device of the present invention is an addressing mode based on such a concept. Complex addressing modes are especially useful for data references between modules and AI language implementations.

When specifying the multi-stage indirect addressing mode, in the basic addressing mode specification field, select one of three types of register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute base multi-stage indirect mode.
Specify one.

The register-based multistage indirect mode is an addressing mode in which a register value is used as a base value for expanding multistage indirect addressing. The format is shown in FIG. Rn
Indicates the general register number.

In the PC-based multi-stage indirect mode, the value of the program counter is
This is an addressing mode that is used as a base value for expanding multistage indirect addressing. The format is shown in Figure 27.

The absolute base multi-stage indirect mode is an addressing mode in which zero is used as a base value for expanding multi-stage indirect addressing. The format is shown in Fig. 28.

The multistage indirect mode specification field to be expanded has 16 bits as a unit, and this is repeated any number of times. Addition of displacement, scaling of index register (× 1, × 2, × 4, ×
8) and addition, indirect reference of memory. The format of the multi-stage indirect mode is shown in FIG. Each field has the following meaning.

E = 0: Multi-stage indirect mode continued E = 1: Address calculation end tmp ==> address of operand I = 0: No memory indirect reference tmp + disp + Rx * Scale ==> tmp I = 1: Memory indirect reference mem [tmp + disp + Rx * Scale ] ==> tmp M = 1: Use <Rx> as index M = 2: Special index <Rx> = 0 Do not add index value (Rx = 0) <Rx> = 1 Use program counter as index value (Rx = PC) <Rx> = 2 to reserved D = 0: The value of the 4-bit field d4 in the multi-stage indirect mode is multiplied by 4 to be a displacement value, which is added. d4 is treated as signed, and it is always multiplied by 4 regardless of the operand size.

D = 1: dispx (16 /
(32 bits) is used as the displacement value and this is added.

The size of the extension is specified in the d4 field.

d4 = 0001 dispx is 16 bits d4 = 0010 dispx is 32 bits XX: Index scale (scale = 1/2/4/8) When the program counter is scaled by × 2, × 4, × 8 Has an indeterminate value as the intermediate value (tmp) after the processing of that stage is completed. The effective address obtained by this multistage indirect mode has an unpredictable value, but no exception occurs. Do not specify scaling for the program counter.

A variation of the instruction format in the multi-stage indirect mode is shown in FIGS. 30 and 31. FIG. 30 shows a variation in which the multistage indirect mode continues or ends. FIG. 31 shows variations in displacement size.

If the multi-stage indirect mode with an arbitrary number of stages can be used, it is not necessary to divide the case depending on the number of stages in the compiler, which has the advantage of reducing the load on the compiler. This is because the compiler must be able to generate correct code even if the frequency of multiple indirect references is extremely low. Therefore, an arbitrary number of stages is possible in terms of format.

(1.5) Exception Processing In the data processing device of the present invention, a wide variety of exception processing functions are provided to reduce the software load. In the data processing device of the present invention, exception processing re-executes instruction processing (exception), One that completes instruction processing (trap), interrupt 3
The names are given separately for each type. Further, in the data processing device of the present invention, these three types of exception processing and system failures are collectively referred to as EIT.

(2) Functional Block Configuration FIG. 2 shows a block diagram of the data processing apparatus of the present invention.
Functionally roughly dividing the inside of the data processing device of the present invention, an instruction fetch unit (51), an instruction decoding unit (52), a PC calculation unit (53), an operand address calculation unit (54), and a micro ROM unit (55). , A data calculation unit (56) and an external bus interface unit (57). In Figure 2, CP
U Address output circuit (58) that outputs the address to the outside and C
Data input / output circuit (59) for inputting / outputting data to / from the outside of the PU
Are shown separately from other functional block parts.

(2.1) The instruction fetch unit (51) has a branch buffer,
There is an instruction queue and its control unit, etc., which determines the address of the next instruction to be fetched and
Fetch instructions from external memory. It also registers instructions in the branch buffer.

Since the branch buffer is small, it operates as a selective cache. The details of the operation of the branch buffer are described in detail in Japanese Patent Application No. 61-202041 .

The address of the instruction to be fetched next is calculated by a dedicated counter as the address of the instruction to be input to the instruction queue. When a branch or jump occurs, the address of the new instruction is transferred from the PC calculation unit (53) or the data calculation unit (56).

When fetching an instruction from the memory outside the CPU, the address of the instruction to be fetched is output from the address output circuit (58) to the outside of the CPU through the external interface unit (57), and the data input / output circuit (59) is output. Fetch the instruction code.

Of the buffered instruction codes, the instruction decoding unit (52) outputs the instruction code to be decoded next to the instruction decoding unit (52).

(2.2) Instruction decoding unit The instruction decoding unit (52) basically decodes the instruction code in 16-bit (halfword) units. This block includes an FHW decoder that decodes the operation code included in the first halfword, an NHFW decoder that decodes the operation code included in the second and third halfwords, and an addressing mode decoder that decodes the addressing mode.

Furthermore, the decoder 2 that further decodes the output of the FHW decoder or NHFW decoder to calculate the entry address of the micro ROM, the branch prediction mechanism that performs branch prediction of conditional branch instructions, the address that checks pipeline conflicts when calculating operand addresses A calculation conflict check mechanism is also included.

The instruction code input from the instruction fetch unit is decoded for 0 to 6 bytes every 2 clocks. Among the decoding results, the information about the operation in the data operation unit (56) is in the micro ROM unit (55), the information related to the operand address calculation is in the operand address calculation unit (54), and the information related to the PC calculation is in the PC calculation unit. Output to (53) respectively.

(2.3) Micro ROM section The micro ROM section (55) stores a micro program that mainly controls the data calculation section (56).
Includes M, micro sequencer, micro instruction decoder, etc. Micro instructions are read from the micro ROM once every two clocks. In addition to the sequence processing indicated by the microprogram, the micro-sequencer accepts exception, interrupt, and trap (these three are collectively called EIT) processing by hardware. The micro ROM section also manages the store buffer. Flag information based on an interrupt or an operation execution result that does not depend on an instruction code and the output of the instruction decoding unit such as the output of the decoder 2 are input to the micro ROM unit. The output of the microdecoder is mainly output to the data operation unit (56), but some information such as other preceding process stop information due to execution of the jump instruction is also output to other blocks.

(2.4) Operand Address Calculation Unit The operand address calculation unit (54) is hard-wired controlled by the information related to the operand address calculation output from the address decoder of the instruction decoding unit (52). In this block, most of the processing for calculating the address of the operand is performed. It is also checked whether the memory access address or operand address for memory indirect addressing falls within the I / O area mapped in the memory.

The address calculation result is the external bus interface (57)
Sent to. The values of general-purpose registers and program counters required for address calculation are input from the data calculation unit.

When performing memory indirect addressing, the memory address to be referred to outside the CPU is output from the address output circuit (58) through the external bus interface unit (57), and the indirect address value input from the data input / output unit (59) is instructed. The decoding unit (52) is passed as it is and fetched.

(2.5) PC calculator The PC calculator (53) is output from the instruction decoder (52).
It is hard-wired controlled by the information related to PC calculation,
Calculate the PC value of the instruction. The data processor of this patent has a variable length instruction set, and the length of the instruction cannot be known unless the instruction is decoded. The PC calculation unit (53) adds the instruction length output from the instruction decoding unit (52) to the PC value of the instruction being decoded to generate the PC value of the next instruction. Also, when the instruction decoding unit (52) decodes a branch instruction and instructs branching at the decoding stage, by adding the branch displacement instead of the instruction length to the PC value of the branch instruction, the PC value of the branch destination instruction is added. To calculate. The branching of a branch instruction at the instruction decoding stage is called a pre-branch in the data processor of the present invention. The method of pre-branching is described in detail in Japanese Patent Application Nos. 61-204500 and 61-200557 .

The calculation result of the PC calculation unit (53) is output as the PC value of each instruction together with the instruction decode result, and at the pre-branch time, it is output to the instruction fetch unit as the address of the instruction to be decoded next.

It is also used as an address for branch prediction of an instruction to be decoded next by the instruction decoding unit (52). The branch prediction method is described in detail in Japanese Patent Application No. 62-8394 .

(2.6) Data operation unit The data operation unit (56) is controlled by the micro program, and executes the operations required to realize the function of each instruction with the register, operation and operation unit according to the output information of the micro ROM unit (55). To do. If the operand to be operated is an address or an immediate value, the address or immediate value calculated by the operand address calculation unit (54) is used as the external bus interface unit (5
Get through 7). When the operand to be operated is data in the memory outside the CPU, the bus interface unit (57) outputs the address calculated by the address calculation unit (54) from the address output circuit (58),
The operand fetched from the memory outside the CPU is obtained from the data input / output circuit (59).

There are ALUs, barrel shifters, priority encoders, counters, shift registers, etc. as computing units. The registers and main arithmetic units are connected by three buses, and one microinstruction for instructing one inter-register operation is processed in two clock cycles.

When it is necessary to access the memory outside the CPU during data operation, the address output circuit (5
The address is output to the outside of the CPU from 8) and the target data is fetched through the data input / output circuit (59).

When storing data in the memory outside the CPU, the address is output from the address output circuit (58) through the external bus interface section (57), and at the same time, the data is output from the data input / output circuit (59) to the outside of the CPU. 4 in the data operation unit (56) for efficient operand store
There is a store buffer of bytes.

When the data operation unit (56) obtains a new instruction address by performing a jump instruction process or an exception process, the data operation unit outputs the instruction address to the instruction fetch unit (51) and the PC calculation unit (53).

(2.7) The external bus interface section (57) controls communication on the external bus of the data processing device of this patent. All memory accesses are clock-synchronized and can be performed in a minimum of two clock cycles.

The memory access request is sent to the instruction fetch unit (51),
It occurs independently from the address calculator (54) and the data calculator (56). The external bus interface section (57) arbitrates these memory access requests. Furthermore, when accessing data at a memory address that crosses a 32-bit (word) aligned boundary that is the size of the data bus connecting the memory and the CPU, it is detected twice that the word boundary is automatically crossed within this block, and the data is accessed twice. The memory access is decomposed into

When the operands to be prefetched overlap, the conflict prevention process and the bypass process from the store operand to the fetch operand are also performed.

(3) Pipeline Mechanism The bipline processing of the data processing apparatus of the present invention has the configuration shown in FIG. Instruction fetch stage (IF stage (31)) that prefetches instructions, decode stage (D stage (32)) that decodes instructions Operand address calculation stage (A stage (33)) that calculates address of operand, micro ROM Access (especially R
A stage (36)), an operand fetch stage (F stage (34)) for prefetching operands (specifically called an OF stage (37)), and an execution stage (E stage (35)) for executing instructions. The stage configuration is the basis of pipeline processing. In the E stage (35), there is a one-stage store buffer, and since some high-performance instructions pipeline the instruction execution itself, there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and theoretically five stages operate completely independently. Each stage is 1
It is possible to perform the processing once with a minimum of two clocks. Therefore, ideally, pipeline processing proceeds every two clocks.

The data processing device of the present invention includes a memory-memory operation,
Although there are instructions that cannot be processed by only one basic pipeline processing such as memory indirect addressing, the data processing apparatus of the present invention is designed so that pipeline processing can be performed in a balanced manner as much as possible. . For an instruction having a plurality of memory operands, the pipeline processing is performed by decomposing into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands. The method of disassembling the pipeline processing unit is described in detail in Japanese Patent Application No. 61-236456 .

The information passed from the IF stage (31) to the D stage (32) is the instruction code itself. From D stage (32) to A
There are two types of information passed to the stage: information related to the operation designated by the instruction (called the D code (41)) and information related to the address calculation of the operand (called the A code (42)). Information passed from the A stage (33) to the F stage includes an R code (43) including an entry address of a microprogram routine and parameters to the microprogram, and an F code including an operand address and access method instruction information. There are two. F stage (3
The information passed from the 4) to the E stage (35) is an E code (45) including operation control information and literals, and an S code (46) including operands and operand addresses.
Is one.

The EIT detected at a stage other than the E stage (35) does not start the RIT processing until the code reaches the E stage (35). Only the instructions processed in the E stage (35) are in the execution stage, and the instructions processed in the IF stage (31) to F stage (34) have not yet reached the execution stage. Therefore, the EIT detected at a stage other than the E stage (35) is only recorded in the step code and transmitted to the next stage.

(3.1) Pipeline processing unit (3.1.1) Classification of instruction code field The pipeline processing unit of the data processing device of the present invention is determined by utilizing the characteristics of the format of the instruction set. As described in the section (1), the instruction of the data processing device of the present invention is a variable length instruction in units of 2 bytes, and basically (2 byte instruction basic part + 0 to 4 byte addressing extension part). The instruction is configured by repeating 1 to 3 times.

In many cases, the instruction basic part has an opcode part and addressing mode specification part. When index addressing or memory indirect addressing is required, instead of the addressing expansion part (2 bytes multi-stage indirect mode specification part + 0 to 4 bytes addressing expansion Parts) are attached arbitrarily. In addition, depending on the instruction, a 2- or 4-byte instruction-specific extension is added at the end.

The instruction basic part includes an opcode of an instruction, a basic addressing mode, and a literal. The addressing extension unit is one of displacement, absolute address, immediate value, and displacement of branch instruction. The instruction-specific expansion part includes a register map and immediate value specification of I-format instructions. First
FIG. 32 shows the characteristics of the basic instruction format of the data processor of the present invention.

(3.12) Decomposition of instruction into step code The data processing apparatus of the present invention performs pipeline processing that makes the most of the characteristics of the above instruction format. In the D stage (32), (2-byte instruction basic part + 0 to 4-byte addressing extension part), (multistage indirect mode designating part + addressing extension part) or an instruction-specific extension part is processed as one decoding unit. The result of decoding each time is called a step code, and this step code is used as a unit of pipeline processing after the A stage (33). The number of step codes is peculiar to each instruction. When the multi-stage indirect mode is not specified, one instruction is at least one and maximum is three.
It is divided into individual step codes. If there is a multistage indirect mode specification, the step code will increase accordingly. However, this is only the decoding stage as described later.

(3.1.3) Management of Program Counter All step codes existing on the pipeline of the data processing device of the present invention may be for different instructions, and the value of the program counter is managed for each step code. Every step code has the program counter value of the instruction that caused the step code. The program counter value attached to the step code and flowing through each stage of the pipeline is called a step program counter (SPC). SPCs are handed over to the pipeline stages one after another.

(3.2) Processing of each pipeline stage The input / output step code of each pipeline stage is named for convenience as shown in FIG. The step code performs processing related to the operation code, and there are two series of series which become the entry address of the micro ROM and parameters for the E stage (35) and the series which become the operand for the micro instruction of the E stage (35).

(3.2.1) Instruction fetch stage The instruction fetch stage (If stage (31)) fetches an instruction from the memory or branch buffer, inputs it to the instruction queue, and outputs an instruction code to the D stage (32). Input to the instruction queue is performed in aligned 4-byte units. 4 aligned when fetching instructions from memory
It requires a minimum of 2 clocks per byte. When the branch buffer is hit, it is possible to fetch the aligned 4 bytes in 1 clock. The output unit of the instruction queue is 2
It is variable for each byte, and up to 6 bytes can be output in 2 clocks. Immediately after branching, it is possible to bypass the instruction queue and directly transfer the two bytes of the basic instruction portion to the instruction decoder.

Controls such as registering and clearing instructions in the branch buffer,
The IF stage (31) also manages the prefetch destination instruction address and controls the instruction queue.

The EIT detected in the IF stage (31) includes a bus access exception when fetching an instruction from memory and an address translation exception due to a memory protection violation.

(3.2.2) Instruction decode stage The instruction decode stage (D stage (32)) decodes the instruction code input from the IF stage (31). Decoding is performed using the FHW decoder, NFHW decoder, and addressing mode decoder of the instruction decoding unit (52).
It is performed once for each clock unit, and is 0 in one decoding process.
-Consumes 6-byte instruction code (does not consume instruction code when outputting step code including return address of RET instruction). A stage by decoding once (33)
On the other hand, the A code (42) which is the address calculation information, the control code of about 35 bits, the maximum 32 bits address modification information, and the D code (41) which is the D code result which is the intermediate decoding result of the operation code. It outputs a 50-bit control code and 8-bit literal information.

In the D stage (32), control of the PC calculation unit (53) for each instruction,
Branch prediction processing, pre-branch processing for pre-branch instructions, and instruction code output processing from the instruction queue are also performed.

The EIT detected in the D stage (32) includes a reserved instruction exception and an odd address jump trap during pre-branch.
Further, various EITs transferred from the IF stage (31) are encoded in the step code and transferred to the A stage (33).

(3.2.2) Operand address calculation stage Operand address calculation stage (A stage (33))
Is roughly divided into two processes. One is a process of performing the subsequent decoding of the operation code by using the decoder 2 of the instruction decoding unit (52), and the other is a process of calculating the operand address in the operand address calculation unit (54).

The subsequent decoding process of the operation code receives the D code (41) as input, and outputs the R code (43) including the write reservation of the register and the memory and the entry address of the microprogram and parameters for the microprogram. Note that the register or memory write reservation is for preventing the contents of the register or memory referred to in the address calculation from being rewritten by the preceding instruction on the pipeline and causing incorrect address calculation. In order to avoid deadlock, write reservation of registers and memory is performed not for each step code but for each instruction. The write reservation of registers and memory is described in detail in Japanese Patent Application No. 62-144394 .

In the operand address calculation process, an A code (42) is input, and according to the A code (42), the operand address calculation unit (54) combines address addition and memory indirect reference to perform address calculation, and the calculation result is the F code (44). Output as. At this time, a conflict check is performed at the time of reading the register or memory associated with the address calculation, and if the conflict is instructed because the preceding instruction has not completed the writing process to the register or memory, the preceding instruction is written at the E stage (35). Wait until the process is completed. It also checks whether the operand address or memory indirect reference address falls within the I / O area mapped in memory.

The EIT detected in the A stage (33) includes a non-reserved instruction, a privileged instruction exception, a bus access exception, an address translation exception, and a debug trap due to an operand breakpoint hit at memory indirect addressing. If the D code (41) and the A code (42) indicate that the EIT has occurred, the A stage (33) does not perform address calculation processing on the code, and the EIT is converted to the R code (43). And F
Tell the code (44).

(3.2.4) Micro ROM access stage The operand fetch stage (F stage (34)) is also roughly divided into two processes. One is a micro ROM access process, which is particularly called an R stage (36). The other is the operand prefetch process, which is particularly called the OF stage (37). The R stage (36) and the OF stage (37) do not always operate simultaneously, but operate independently depending on whether or not a memory access right can be acquired.

The micro ROM access process, which is the process of the R stage (36), is an execution control code used for execution at the next E stage for the R code. It is a micro ROM access and a micro instruction decoding process for creating an E code. When the processing for one R code is decomposed into two or more microprogram steps, the micro ROM is used in the E stage (35), and the next R code (43) waits for the micro ROM access. The micro ROM access to the R code (43) is performed at the last micro instruction execution in the E stage (35) before that. In the data processor of the present invention, most of the basic instructions are carried out by one microprogram step, so in practice, micro ROM access to the R code (43) is often carried out one after another.

There is no new EIT detected in the R stage (36). When the R code (36) indicates the EIT of the instruction processing re-execution type, the micro program for the EIT processing is executed, so the R stage (36) fetches the micro instruction according to the R code (43). . When the R code (43) indicates an odd address jump trap, the R stage (3
6) conveys it to the E code (45). This is for a pre-branch. In the E stage (35), if no branch occurs in the E code (45), the pre-branch is validated and an odd address jump trap is generated.

(3.2.5) Operand fetch stage Operand fetch stage (OF stage (37)) is F
Operand prefetch processing is performed among the above two processing performed in the stage (34).

Operand prefetch uses F code (44) as input,
The fetched operand and its address are S code (4
6) Output as. One F code (44) may cross word boundaries, but specifies an operand fetch of 4 bytes or less. The F code (44) also contains a designation as to whether or not to access the operand. When the operand address itself or the immediate value calculated in the A stage (33) is transferred to the E stage (35), the operand prefetch is Instead, the contents of the F code (44) are transferred as the S code (46). When the operand to be prefetched and the operand to be written by the E stage (35) match, the operand prefetch is not performed from the memory but bypassed. Operand prefetch is delayed for the I / O area, and the operand fetch is performed after waiting for all the preceding instructions.

The EIT detected at the OF stage (37) includes a bus access exception, an address translation exception, and a debug trap due to a breakpoint hit for operand prefetch. When the F code (44) indicates an EIT other than the debug trap, it is transferred to the S code (46) and operand prefetch is not performed. When the F code (44) indicates a debug trap, the same processing as when the F code (44) does not indicate EIT is performed and the debug trap is transmitted to the S code (46).

(3.2.6) Execution stage The execution stage (E stage (35)) is the E code (45),
Operates by inputting the S code (46). The E stage (35) is a stage for executing an instruction, and all the processing performed in the stages before the F stage (34) is preprocessing for the E stage (35). When the jump instruction is executed in the E stage (35) or the EIT process is activated, all the processes from the (IF) stage (31) to the F stage (34) are invalidated. The E stage (35) is controlled by the microprogram, and executes an instruction by executing a series of microprograms from the entry address of the microprogram indicated by the R code (45).

The reading of the micro ROM and the execution of the micro instructions are pipelined. Therefore, when a branch occurs in the microprogram, there is a space of 1 microstep. Further, the E stage (35) can use the store buffer in the data operation unit (56) to pipeline the operand store within 4 bytes and the next microinstruction execution.

In the E stage (35), the write reservation for the register and memory made in the A stage (33) is canceled after writing the operand.

Further, when the conditional branch instruction causes a branch at the E stage (35), the branch prediction for the conditional branch instruction was incorrect, so the branch history is rewritten.

EIT detected in E stage (35) includes bus access exception, address translation exception, debug trap, odd address jump trap, reserved function exception, illegal operand exception, reserved stack format exception, divide by zero trap, unconditional trap, condition There are traps, delayed context traps, external interrupts, delayed interrupts, reset interrupts, and system failures.

All EITs detected in E stage (35) are processed by EIT, but detected between IF stage (31) to F stage (34) before E stage and R code (43) or S code (46).
The EIT reflected in is not always processed by EIT. An EIT that was detected between the IF stage (31) and the F stage (34) but did not reach the E stage (35) due to a preceding instruction such as a jump instruction being executed at the E stage (35). All canceled. The instruction that caused the EIT was not executed in the first place.

External interrupts and delayed interrupts are E stages at instruction breaks (35)
Is directly received by and the required processing is executed by the microprogram. Other various EITs are also processed by microprograms.

(3.3) State control of each pipeline stage Each stage of the pipeline basically has an input latch and an output latch and operates independently of other stages. Each stage completes the previous processing, transfers the processing result from the output latch to the input latch of the next stage, and when the input latch of the own stage has all the input signals necessary for the next processing, The process of is started.

In other words, in each stage, when all the input signals for the next processing output from the previous stage become valid, the current processing result is transferred to the input latch of the subsequent stage and the output latch becomes empty, the next Start processing.

All input signals must be available at the clock timing one clock before the operation of each stage. If the input signals are not complete, the stage enters the waiting state (waiting for input). When transferring from the output latch to the input latch of the next stage, the input latch of the next stage must be empty, and even if the input latch of the next stage is not empty, the pipeline stage waits. (Waiting for output). If the necessary memory access right cannot be acquired, a wait is inserted in the memory access being processed, or other pipeline conflict occurs, the processing itself of each stage is delayed.

(4) Processing of branch instruction Since the data processing device of the present invention employs the multi-stage pipeline processing as described above, the overhead when executing the branch instruction is large. Dynamic branch prediction processing is performed to reduce this overhead. The dynamic branch prediction process aims at fetching a branch target instruction as early as possible by performing a branch at the decode stage instead of a branch at the execution stage.

Not only the data processing device of the present invention, but in the data processing device, the branch instruction is generally executed at a high frequency, and the performance improvement effect by the dynamic branch prediction process is large.

(4.1) Kind of branch instruction In the data processing device of the present invention, an instruction that performs dynamic branch prediction processing is called a pre-branch instruction. The pre-branch instruction also includes an instruction that always branches regardless of dynamic prediction, such as an unconditional branch instruction.

The branch instructions included in the data processing device of the present invention can be classified into a total of four types depending on whether the branch condition is static or dynamic and whether the branch destination is static or dynamic. The data processing device of the present invention is classified into the following two types. The executed instruction is a pre-branch instruction.

The first type of branch instruction is a static instruction in both branch condition and branch destination. This kind of instruction includes an unconditional branch instruction (BRA) and a subroutine call instruction (BSR). The second type of branch instruction is an instruction whose branch condition is dynamic and whose branch destination is static. This kind of instruction includes a conditional branch instruction (Bcc) and a loop control instruction (ACB).

(4.2) Functional Configuration of Branch Instruction Processing Circuit FIG. 1 shows the configuration of the branch instruction processing circuit of the data processing device of the present invention. FIG. 1 shows an instruction fetch section (51), an instruction decode section (52), a PC calculation section (53), an operand address calculation section (54), a data calculation section (56), and an external bus interface section (57). Partial detailed view of the circuit included in, address output circuit (58), data input / output circuit (5
9) consists of.

The instruction decode (111) is connected to the input side of the PC adder (132) and the input side of the address adder (124) by a DISP bus (100) that transfers displacement values and displacement values of branch instructions. Instruction decode (111) and address adder (1
The input side of 24) is also connected to the correction value bus (101) that transfers the instruction code length used for step code generation and the pre-decrement value in the stack push mode. The instruction decoder (111) and the input side of the PC adder (132) are also connected to an instruction length bus (101) for transferring the instruction code length used for step code generation. The register file (144) and the address adder (124) input side transfer the address value stored in the register file (144) A
It is connected by bus (103).

An instruction code is input from the instruction queue (112) to the instruction decoder (111), and a branch prediction bit is input from the branch prediction table (113). At the output unit of the instruction decoder (111), the branch prediction result is used to select whether to output the branch condition designation field of the conditional branch instruction to the E stage (35) as it is or invert the condition designation and output. There is a branch condition generation circuit (114).

Output of the added value selection circuit (131) that selects and inputs either the value of the instruction length bus (101) or the value of the DISP bus (100) and the PC value of the instruction decoded in the D stage (32) , Or a TPC (134) that holds a working PC value for each break in the step code, is input to a PC adder (132). The output of the PC adder (132) is output to the CA bus (104) and PO bus (105) through the PC adder output latch (133). PO bus (105) is latched TPC (13
4), Latch DPC (135), P of the instruction being processed at the A stage
It is also connected to a latch APC (136) that holds the C value and a branch prediction table (113). The TPC (134) also has an input path from the CA bus (103) for inputting a new instruction address when a branch or jump occurs in the E stage (35).

The output of the correction value bus (102) and the output of the DISP bus (100) are input to the displacement selection circuit (122), one of which is input to the address adder (124), and the output of the DISP bus (100) and A The output of the bus (103) is input to the base address selection circuit (123), and one of them is input to the address adder (124). The address adder (124)
Output of displacement selection circuit (122), output of base address selection circuit (123), and A bus (103)
By shifting the value input more, 1 times, 2
Index value generation circuit (12x, 4x, 8x)
The output of 1), three values in total, are input, and three-value addition is performed. The output value of the address adder (124) is output to the AO bus (106) through the address adder output latch (125). The AO bus (106) uses the address output circuit (5) through the AA bus (107) when performing memory indirect addressing.
8) When an address value is output from the CPU to the outside of the CPU, the latch IA (126) that holds the address value and the operand output from the address output circuit (58) to the outside of the CPU through the AA bus (107) during operand prefetch in the F stage When the address value is output, it is connected to the latch FA (127) that holds the operand address.

The FA (127) also has an output path to a latch SA (141) that holds an operand address value in order to use the operand address calculated by the address adder (124) in the E stage (35). The SA (141) has an output path to the S bus (109) which is a general-purpose data bus of the data calculation section (56).
The CA bus (104) that transfers the address of the instruction is the PC addition output latch (133), the TPC (134), and the instruction fetch unit (5
1) A counter QINPC (115) for managing the address of the instruction code prefetched by 1) and an address for the instruction fetch from the address output circuit (58) via the AA bus (107) to the C
Latch AA (14
2) and a latch EB (143) which inputs a new instruction address from the S bus (109) when a branch or jump occurs in the E stage (35). The APC (136) has an output path to the A bus (103) and the latch EPC (137) that holds the PC value of the instruction being processed in the F stage (34). EPC (1
37) has an output path to a latch CPC (138) which holds the PC value of the instruction being processed in the E stage (35). The CPC (138) has an output path to the S bus (109) and a latch OPC (139) that holds the value of the least significant byte of the PC value for branch history rewriting. The register file (144) consists of general-purpose registers and work registers, and has an S bus (109) and A bus (10).
It has an output path to 3) and an input path from the D bus (110). The data calculator (145), which is the calculation mechanism of the data calculator (56), has an input path from the S bus (109) and an output path to the D bus (110).

(4.3) Branch prediction method In the data processing device of the present invention, the unconditional branch instruction BRA, the subroutine branch instruction BSR, the loop control instruction ACB, and the three instructions are always used regardless of the branch prediction bit output from the branch prediction table. This prediction is always correct for BRA and BSR that are predicted to branch.

The ACB is an instruction that adds a specified value to a loop control variable and determines whether or not the result satisfies a loop end condition, branches if the loop end condition is not satisfied, and does not branch if the loop end condition is satisfied. Therefore, in most software, this prediction method is correct for ACB with a considerable probability. Also,
If the software is created in consideration of the characteristic processing of the data processing apparatus of the present invention for the ACB, it is possible to create a more efficient program than when the software is not created.

Whether or not the conditional branch instruction Bcc is branched is determined according to the past history. The history is recorded based on the lower 8 bits of the address of the instruction executed immediately before the Bcc instruction. Branch prediction follows 1 branch history only
Indicated in bits.

(4.4) Configuration of Branch Prediction Table FIG. 4 shows the details of the branch prediction table (113). The 7-bit input from the PO bus (105) and the 7-bit input from the OPC (139) are passed through the selector (151) to the decoder (152).
Entered in. In the decoder (152), 7 bits are decoded into 128 bits, and one of the 128-bit branch history latches (153) is used as a branch prediction value.
Output to 4). When the clear signal (157) is input, the 128-bit branch history latch (153) simultaneously sets the value to zero, indicating "no branch". The branch side output latch (154) has its contents inverted by a prediction inversion circuit (155) and is connected to a branch prediction update latch (156).

In the data processor of the present invention, the branch prediction table (113) is based on the lower 8 bits of the address of the instruction decoded in the D stage (32) immediately before the instruction to be decoded in the D stage (32). To predict branching. The branch prediction is registered by the direct mapping method according to only the past history. In the data processor of the present invention, the least significant bit (right-side bit) of the instruction address is always zero, and thus the branch prediction table is composed of 128 bits.

The branch prediction bit is effectively used only when decoding the Bcc instruction, but the branch prediction bit is input to the instruction decoder together with the instruction codes of all instructions regardless of whether or not it is used. Therefore, the reference to the branch prediction table (113) is lower than the PC value of the immediately preceding instruction output from the PC adder (132) when the instruction immediately before the instruction to be decoded is being decoded. It is performed in 1 byte (the least significant bit is unnecessary). As a result, the branch prediction bit is input to the instruction decoder (111) by the beginning of the next D stage processing.

The branch history of the branch prediction table (113) is clear signal (15
By 7), all initial values can be set to "not branch". The branch prediction is updated when the Bcc instruction branches at the E stage (35). When the Bcc instruction causes a branch at the E stage (35), it means that the branch prediction at the D stage (32) was incorrect. At this time, E stage (35)
Updates the branch prediction (inverts the wrong branch history). In the E stage (35), the contents of the OPC (139) are transferred to the decoder (152), and the contents of the branch history latch (153) corresponding to the decoding result are transferred to the branch prediction output latch (15).
Read to 4). Next, the contents of the branch prediction update latch (156) in which the contents of the branch prediction output latch (154) are inverted are
Branch history latch (15), also indicated by the value of OPC (139)
Write back to 3).

Since the branch prediction is performed based on the PC value of the decoded instruction before the target Bcc instruction is decoded, the update of the branch prediction table (113) is also one of the Bcc instructions at the E stage (35). Based on the PC value of the previously executed instruction. For this reason, the E stage (35) has an OPC (139) that stores the lower 1 byte (the least significant bit is unnecessary) of the PC value of the instruction executed immediately before the currently executing instruction, and the branch prediction table This value is used to update (113). Since the branch history is updated only when the Bcc instruction causes a branch in the E stage (35), the reference operation of the branch prediction table (113) in the D stage (32) is updated in the E stage (35). There is no hindrance. Immediately after the branch occurs in the E stage (35), the D stage (32) waits for the instruction code from the IF stage (31). Rewriting of the branch history is performed during this instruction code waiting state.

(4.5) Operation of PC calculation unit When the PC calculation unit decodes the instruction code in the D stage (32), the length information of the instruction code that was previously decoded and the instruction code that was decoded immediately before that The start address of the instruction code being decoded is calculated from the start address of.
The PC calculator holds the PC value of the instruction, which is the address of the instruction break, in the DPC (135), and manages the address of the step code break in the TPC (134). The DPC (135) is rewritten only when the instruction break address is calculated. TP
C (134) is rewritten at the address of the break of the step code, that is, every instruction decoding process. Since the PC value of the step code processed in the pipeline requires the PC value of the instruction that caused the step code, DPC
The value of (135) is transferred to APC (136), EPC (137), and CPC (138).

Instruction decoding is performed in step code units as described in section (3.1.2), and 0 to 6 byte instruction codes are consumed in one decoding process. The length of the instruction code used at that time, which is found for each instruction decoding process, is output from the instruction decoder (111) to the instruction length bus (101).

If the pre-branch is not performed, the D stage (32) decodes the next succeeding instruction, and at the same time, the PC calculator (5
To calculate the PC value of the next instruction that follows in 3), use TPC (13
The value in 4) is added to the length of the instruction code consumed by decoding transferred from the instruction length bus (101), and the addition result is written back to the TPC (134). That is, the start address of a step code is calculated when the step code is generated by the decoding process. The instruction code to be decoded except the pre-branch is the instruction queue (112)
It is not necessary to know the start address of the code at the decoding start stage, since it is output one after another. D stage (3
When the step code generated in 2) is the last step code of the instruction A, the output of the PC adder (132) calculated during the decoding process of the next instruction B is the start address of the instruction B. Since it is the PC value of B, the PC value of the instruction B output from the PC adder (132) is TPC (13) from the PO bus (105).
4) and written to both DPC (135). At this time, if the A stage (33) is waiting for an input code and the APC (136) is urgently needed, the APC (13) from the PO bus (105).
The PC value of instruction B is also written in 6).

When pre-branching, the D stage (32) outputs the last step code of the pre-branch instruction, then stops the processing of the instruction decoder (111) and calculates the PC value of the branch destination instruction. The value and the branch displacement transferred from the DISP bus (100) are added. Furthermore, IF stage (31)
The initialization instruction to the PC value of the branch instruction
While writing to TPC (134) and DPC (135), CA bus (10
Also output to 4) and write to QINPC (115), CAA (142).

When calculating the branch destination instruction address by the pre-branch, an odd address jump trap is also detected, and the result is shown as a parameter in the D code (41). In the E stage (35), the odd address jump trap is activated when the pre-branch is found to be correct. When the pre-branch is wrong and the branch occurs again at the E stage (35), the odd address jump trap detected in the pre-branch is ignored. Therefore, the odd address jump trap detected at the D stage (32) is not
It is treated differently from. Further, in the E stage (35), the value of the odd instruction address is required for the activation processing of the odd address jump trap. Therefore, when the D stage (32) detects an odd address jump trap, a special step code (OAJT step code) with the odd address value as a PC value is generated. 33), F stage (34)
Tells the code to the next stage. E stage (3
5) determines that the pre-branch is correct, and when the pre-branch detects an odd address jump trap, it uses the PC value of the OAJT step code that is transferred next through CPC (138) to detect the odd address. Performs jump trap startup processing.

When a branch occurs at the E stage (35), the branch destination address is transferred from the EB (143) to the TPC (134) via the CA bus (104). The PC calculation unit (53) adds this value and zero and outputs the result from the PO bus (105) to the TPC (134) and DPC (13
Write in 5). This completes the initialization of the PC calculator (53). This initialization processing overlaps with the first unit decoding processing in which the branch occurs in the E stage (35). For QINPC (115) and CAA (142), the CA bus (10
The same value is set when the value is taken into TPC (134) from 4).

(4.7) Operation of operand address calculation unit for pre-branch instruction If the D stage (32) does not perform pre-branch processing for the pre-branch instruction, the operand address calculation unit (54) causes the branch destination address of the pre-branch instruction. To calculate. The branch destination address is calculated by adding the value of the APC (136) transferred from the A bus (103) and the branch displacement value transferred from the DISP bus (100) by the address adder (124). Be seen. The calculated branch destination address is transmitted to the E stage (35). A stage (33)
In the calculation of the branch destination address using the operand address calculation unit (54), the odd address jump trap is not detected. Odd address jump trap information is transmitted because the branch destination address transferred to the E stage (35) is odd.> If the D stage (32) performs pre-branch processing, Bcc
For instructions and ACB instructions, the A stage (33) PC of the next instruction at the address following the pre-branch instruction
Calculate the value. The calculation result is transmitted to the E stage (35) and used as a branch destination address again when the pre-branch is wrong. D stage (3
For the instruction decoded into the 1-step code in 2), the instruction length of the Bcc instruction transferred from the correction value bus (102) is added to the value of APC (136) transferred from the A bus (104). Add and add the result from AO bus (106) to FA (127)
Write in. For the ACB instruction that has a format in which the step code is divided into two or more, from the value of TPC (134) which is the start address of the last step code transferred from the DISP bus (100) and the correction value bus (102) Add the length of the instruction code used for decoding the last transferred step code, and add the result from the AO bus (106) to F
Write to A (127).

The pre-branch is always correct for the BSR instruction, but since the address of the BSR instruction is required as the return address, the operand address calculation unit (54) calculates the address. The format of the BSR instruction is shown in FIG. number 3
In Figure 3, #ds is an instruction that is decoded into one step code in the BSR D stage (32), which is a field that specifies the branch displacement of BSR with a 32-bit binary number, and is the same as Bcc from the A bus (103). The value of the transferred APC (136) and the instruction length of the BSR transferred from the correction value bus (102) are added. The return address calculation method for BSR instructions is also used for TRAP (unconditional trap) instructions and TRAP / cccc (condition trap) instructions.

The TRAPA instruction and the TRAP / cccc instruction are also instructions that are decoded into a one-step code in the D stage (32), and the operand address calculation unit (54) does not wait for the addressing mode specification field like Bcc, and the operand address calculator (54) Is not calculated. The formats of the TRAPA instruction and TRAP / cccc instruction are shown in FIG. In Figure 34, (301) is TRAPA.
Instruction format, (302) is the format of the TRAP / cccc instruction. In Figure 34, # d4 is the vector value specification field of the TRAPA instruction, cccc (303) is the top condition specification field TRAPA, and TRAP / cccc does not calculate the operand address, but the PC value of these instructions. The APC (136) and the instruction length of these instructions transferred from the correction value bus (102) are added.

(4.8) Details of Processing Method for Each Branch Instruction The instructions for which the data processing device of the present invention performs pre-branching are summarized here.

(4.8.1) BRA instruction The BRA instruction is an unconditional branch instruction and always causes a branch when executed.

Since the BRA instruction always causes a branch, the D stage (32) determines that the branch always occurs regardless of the branch prediction bit and performs pre-branch processing. A stage (33), F stage (3
In 4), the BRA instruction is transferred again, and only the flag indicating whether EIT is detected and the PC value are in the E stage (35).
Will be transferred to. Transferred to the E stage (35). In E stage (35), BRA is not branched.

(4.8.2) BSR instruction The BSR instruction is a subroutine branch instruction, and when it is executed, B
Pushes the PC value of the instruction at the address next to SR onto the stack and always causes a branch. The instruction format is shown in FIG.

Since the BSR instruction always causes a branch, in the D stage (32), it is determined that the branch always occurs regardless of the branch prediction bit and the pre-branch processing is performed. In A stage (33) with APC (136)
Calculate the return address from the subroutine by adding the BSR instruction length. The calculated return address is BSR
Is passed to the E stage (35) as an operand of. At the E stage (35), the return address for the BSR instruction is pushed onto the stack and branch processing is not performed.

(4.8.3) Bcc instruction The Bcc instruction is a conditional branch instruction, and the instruction format is shown in FIG. The branch condition ccc (304) has a 4-bit format. As for the branch condition, the branch condition is set to the opposite depending on whether the least significant bit of the branch condition cccc (304) in FIG. 35 is "0" or "1". #Ds is a field that specifies the branch displacement by a 32-bit binary number.

Since the branch probability of the Bcc instruction greatly depends on the past execution history, the branch prediction table (113) is used in the D stage (32).
It is determined whether to branch according to the value of the branch prediction bit output from. Regarding the execution history dependency of the branch probability of the Bcc instruction, the above JKFLee, AJ Smith, "Branch Pre
diction Strategies and Branch Target Buffer Desig
h ”, IEEE Computer, Vo 1.17, No. 1, January, 1984.

D if the branch prediction bit indicates "branch"
Perform pre-branch processing in stage (32). When pre-branching is performed, the branch condition generation circuit (114) performs the third branch.
Since the least significant bit of the branch condition cccc (304) in Fig. 5 is inverted and passed to the E stage (35), regardless of whether pre-branch processing was performed in the D stage (32) in the E stage (35). , Bcc instruction should be executed according to the passed branch condition. If the Bcc instruction causes a branch at the E stage (35), it means that the branch prediction at the D stage (32) was incorrect, so the branch prediction table (11
3) is accessed to invert the branch prediction history at the location indicated by OPC (139). The branch history is updated at the E stage (3
Since it is executed only when the Bcc instruction causes a branch in 5), the reference operation of the branch prediction table (113) of the D stage (32) is not hindered by the update of the E stage (35). Immediately after the branch occurs in the E stage (35), the D stage (32) waits for the instruction code from the IF stage (31). Rewriting of the branch history is performed during this instruction code waiting state.

If the Bcc instruction detects an odd address jump trap at the pre-branch and the E stage (35) does not cause a branch, the odd address jump trap is activated. Even if the Bcc instruction detects an odd address jump trap during the pre-branch, the detection of the odd address jump trap during the pre-branch is ignored when the branch occurs again at the E stage (35). Owing to this function, the odd address jump trap will not be detected by executing the Bcc instruction without branch processing.

(4.8.4) ACB instruction The ACB instruction is an instruction used as a primitive of a loop. ACB is an instruction that increases the loop control variables, compares them, and performs a conditional jump. ACB format is third
Shown in Figure 6. In Fig. 36, EaR is a field that specifies the value to be added to the loop control variable in the general form addressing mode, EaRX is a field that specifies the comparison target value of the loop control variable in the general form addressing mode, and RgMX is the existence of the loop control variable. # Ds8 is a field for designating a general-purpose register number to be stored, and # ds8 is a field for designating a branch displacement by an 8-bit binary number. ACB is an instruction that is decomposed into 3 step codes or more in the D stage (32) and flows on the pipeline.

Since the ACB instruction has a high probability of branching, the data processing apparatus of the present invention performs pre-branch processing on this instruction regardless of the branch prediction bit, judging that the instruction will branch.

Since this instruction has three or more step codes (three if the multi-stage indirect addressing mode is not included), pre-branching processing is performed when the final step code is output from the D stage (32). ACB on D stage (32)
Contents of DPC (135) which is the PC value of and instruction decoder (111)
The pre-branch processing is performed by adding the branch displacement output from the device through the DISP bus (100). In the A stage (33), when the pre-branch is wrong, when calculating the PC value of the address instruction next to the ACB instruction, the last step code transferred from the TPC (134) through the DISP bus (100) The start address of the instruction code used for decoding and the length of the instruction code used for decoding the last step code transferred through the correction value bus (102) are added.

Since pre-branching is always performed for this instruction in the D stage (32), the judgment of the branch condition is always reversed in the E stage (35). If the pre-branch processing is incorrect, a branch occurs at the E stage (35). However, since this instruction does not pre-branch according to the branch prediction table (113), the branch history is not rewritten even if the pre-branch is wrong.

Or, if an odd address jump exception is detected during pre-branching in the D stage (32) for this instruction, the detection is performed with the E stage (3
5). The odd address jump trap transmitted to the E stage (35) is still E as with the Bcc instruction.
It will not be activated when a branch is taken at stage (35),
Fires when no branch is taken. With this function, the odd address jump trap will not be detected by executing the ACB instruction without branch processing.

(5) Other Embodiments of the Present Invention In the above embodiments, the decoder (111) to the PC calculator (5
In order to transfer the length of the instruction code used for instruction decoding to 3) and the operand address calculation unit (54), two buses, a correction value bus (102) and an instruction length bus (101), are used. For example, correction value bus (102) to PC calculation unit (53)
The instruction length bus (101) may be eliminated by providing an input path to the.

Further, in the above-described embodiment, T
The example of transferring the value of PC (134) to the operand address calculator (54) through the DISP bus (102) was described.
The value of C (134) may be transferred by the A bus (103).

〔The invention's effect〕

In the data processor of the present invention, the BRA instruction, the BSR instruction, the Bcc instruction which are processed by the one-step code as described above, and the ACB instruction having a plurality of step codes are branched at the D stage (32). Therefore, the disturbance of pipeline processing can be reduced for many branch instructions.

FIG. 7 shows a state of an instruction flowing in the pipeline when a pre-branch instruction is executed in the data processing device of the present invention which performs pre-branch. In FIG. 7, command 3 and command
Reference numeral 12 is a branch instruction, which is a target of pre-branch processing of the data processing device of the present invention.

When the instruction 3 is decoded in the D stage (32) and it is determined to be pre-branched, the PC value of the branch destination instruction is calculated in the PC calculation unit (53) in the D stage (32). Next, the branch target instruction is fetched by the IF stage (31), and the pipeline processing target is switched to the instruction 11 early. Command 4 is canceled. While the D stage (32) and the IF stage (31) are performing the pre-branch processing, the instruction 1 and the instruction 2 preceding the pipeline continue processing. As a result, after the instruction 3 is processed in the E stage (35), the instruction 11 is processed in the E stage (35) two time after the processing. This is because the data processing apparatus of the present invention reduces the dead time by half as compared with the conventional data processing apparatus which does not perform the pre-branch processing as shown in FIG. Means that

As described above, pre-branching is a very effective technique for increasing the speed of the data processing device, and it is important to perform pre-branching for as many branch instructions as possible. In the present invention,
By adding a little hardware to the PC calculation unit (54) and operand address calculation unit (54), even for BRA and Bcc instructions processed in one step code The pre-branch processing is also possible, and the processing speed is significantly increased.

Also, the branch prediction table can be rewritten for the Bcc instruction by E.
When a branch is made in the stage (35), it is possible to update the branch history until the branch prediction table (113) needs to be accessed in the next D stage (32).
The D stage (32) and the E stage (35) can prevent the processing speed of the data processing device from being lowered due to the delay of the pipeline processing due to the access competition of the branch prediction table (113).

[Brief description of drawings]

FIG. 1 is a diagram of a branch instruction processing circuit of a data processing device of the present invention, FIG. 2 is an overall block diagram of the data processing device of the present invention, and FIG. 3 is a schematic diagram of a pipeline stage of the data processing device of the present invention. FIG. 4 is a detailed view of a branch prediction table of the data processor of the present invention, FIG. 5 is a schematic diagram of a pipeline stage of the conventional data processor, and FIG. 6 is a state of branch instruction processing in the conventional data processor. FIG. 7 is a diagram showing a state of branch instruction processing in the data processing device of the present invention,
FIG. 8 is a diagram showing the arrangement of instructions on the memory of the data processing device of the present invention, FIGS. 9 to 17 are diagrams of the instruction format of the data processing device of the present invention, and FIGS. 18 to 31 are FIG. 32 is an explanatory diagram of an addressing mode of the data processing device of the present invention, FIG. 32 is a diagram showing characteristics of an instruction format of the data processing device of the present invention, FIG. 33 is a format diagram of BSR instruction, FIG. 34 is TRAPA, TRAP / cccc instruction format diagram,
FIG. 35 is a format diagram of the Bcc instruction, and FIG. 36 is a format diagram of the ACB instruction. (52) is an instruction decoding unit, (53) is a PC calculation unit, (54) is an operand address calculation unit, (56) is a data calculation unit,
(100) shows the DISP bus, (102) shows the correction value bus, and (103) shows the A bus.

Claims (3)

[Claims] 1. A decoding mechanism that receives an instruction code, decodes the instruction code, and receives information about updating a program counter from the decoding mechanism, calculates a program counter value of an instruction code next to the instruction code, A data processing device comprising: a first calculation mechanism that holds a start address of an instruction code; and a second calculation mechanism that receives information related to operand address calculation from the decoding mechanism and calculates an operand address. In the above, when the conditional branch instruction is decoded, the first calculation mechanism fetches the branch destination instruction to fetch the start address of the conditional branch instruction and the branch displacement of the conditional branch instruction from the decoding mechanism. To generate a branch destination address, and the second calculation mechanism If not, in order to fetch the instruction code next to the conditional branch instruction, the start address of the conditional branch instruction calculated by the first calculation mechanism and the instruction length of the conditional branch instruction from the decoding mechanism And a sum of them to generate a start address of an instruction code next to the conditional branch instruction. 2. A decoding mechanism that divides a conditional branch instruction into a plurality of unit decoding processes of two or more times and decodes it, and a first mechanism that holds the address value of the break of the instruction code that the decoding mechanism performs the unit decoding process. A latch, a second latch that holds the program counter value of an instruction decoded by the decoding mechanism, and an addition that selectively uses the contents of either the first latch or the second latch as the first input. A first calculating mechanism for receiving a program counter update information from the decoding mechanism and calculating a program counter value; and receiving an operand address calculation information from the decoding mechanism,
In a data processing device having a second calculation mechanism for calculating an operand address, the first calculation mechanism decodes the last instruction code of the conditional branch instruction by the decoding mechanism to fetch a branch destination instruction. The second displacement mechanism receives the contents of the second latch and the branch displacement of the conditional branch instruction from the decoding mechanism, adds them, and generates a branch destination address. If no branch occurs,
In order to fetch the next instruction of the conditional branch instruction, the contents of the first latch and the instruction code length of the last instruction code of the conditional branch instruction are received by the decoding mechanism, they are added, A data processing device characterized by generating a start address of an instruction code next to a conditional branch instruction. 3. A branch history table for holding a branch history of a conditional branch instruction, instruction decoding, and a first branch process for the conditional branch instruction according to the output of the branch history table or the first branch processing. A first pipeline stage having a function of performing either of the branch processing and the second branch processing according to a branch condition for the conditional branch instruction. A second pipeline stage having a function of performing an operation of performing or not performing, and a function of performing a pipeline operation of the second pipeline stage, wherein the second pipeline stage executes the second branch processing. When the second pipeline stage is accessed, the second pipeline stage has priority over the first pipeline stage to access the branch history table to update the branch history. When the processing has not been performed, the second pipeline stage, the data processing apparatus characterized by not access the branch history table.