JPH0253990B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a synchronization separation circuit for a television receiver.

In a television receiver (hereinafter abbreviated as TV), a broadcast radio signal received by an antenna is converted into a composite video signal through a tuner, a video intermediate frequency amplification circuit, and a video detection circuit. Such a signal is supplied to a video signal and chroma signal processing circuit and an audio signal processing circuit, and is also supplied to a synchronization separation circuit,
Its output synchronizes the horizontal and vertical oscillation frequencies and phases with the radio signal. Conventionally, synchronous separation circuits use circuits whose thresholds are set to a voltage slightly below the peak value due to self-biasing by elements with rectifying characteristics, and separation based on the voltage difference between the synchronous voltage level and the video signal level is performed. is being carried out. This method tracks steady differences in the magnitude of the synchronization signal well, but in composite video signals, the magnitude of the synchronization signal may change due to sag, etc.
Due to ghosts, the synchronization signal cannot fully follow fast changes such as when the magnitude of the synchronization signal differs horizontally and vertically, resulting in malfunctions and synchronization errors.

FIG. 1 shows an example of a conventional base time constant type synchronous separation circuit. 1 is a composite video signal source, and 2 is its internal resistance, which is actually the video detection stage or the first video amplification stage and its output impedance. When the synchronization signal in the composite video signal is input, conduction occurs between the base and emitter of transistor 5, and internal resistance 2
The capacitor 3 is charged according to the magnitude of the synchronizing signal voltage. In a portion of the composite video signal other than the synchronization signal, the transistor 5 becomes non-conductive, and the charge in the capacitor 3 is slowly discharged via the resistor 4.
Therefore, a DC voltage is generated in the capacitor 3 that causes the transistor 5 to be reverse biased. However, since the average charges and discharges of the capacitor 3 during steady state are the same, the value of the reverse bias voltage is self-set to a voltage that makes the average charges and discharges of the capacitor 3 equal. This allows voltage separation between the synchronous component and other parts. For example, if you reduce the value of resistor 4, the discharge current will increase, so to compensate for this, the self-bias will become shallower, the threshold for the sync signal section will become relatively lower, and the charging current for the sync signal section will increase. . Depending on whether the transistor 5 is conductive or non-conductive,
A synchronizing signal with the video component removed is obtained at both ends of the load resistor 6, and is applied as it is to the horizontal AFC circuit (H.AFC), and is also applied to the vertical oscillation circuit (V.OSC) via the low-pass filter 8. Terminal 7 is a power supply terminal to which power supply voltage Vcc is applied.

The response of this circuit is that although the self-bias responds well to steady deviations in the magnitude of the synchronization signal, it is particularly difficult to respond to rapid responses due to vertical sag, ghosting, fading, etc. There was a drawback that the self-bias could not catch up with the direction of sudden decrease, resulting in a lack of synchronization. On the other hand, if the constants are set to make the self-bias shallower, the threshold for the synchronization signal will be lowered and the lack of synchronization mentioned above can be addressed, but on the contrary, conduction will occur not only at the synchronization tip but also at the pedestal part. This had the disadvantage of shifting the start of the horizontal cycle.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above drawbacks and provide a synchronization separation circuit that is resistant to vertical sag, ghosting, fading, and the like.

The synchronization separation circuit according to the present invention supplies a composite video signal to the emitter of a transistor whose base is biased at a constant voltage via a capacitor, and from the collector of this transistor passes the horizontal and It is characterized by extracting a vertical synchronization signal.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 is a circuit diagram showing a circuit which is a prerequisite for the present invention, and the same parts as in FIG. 1 are given the same numbers. Each of elements 9 to 12 corresponds operationally to elements 3 to 6, respectively. Therefore, if the constants are exactly the same, the operation will not be any different from that shown in FIG. However, in FIG. 2, the value of resistor 4 is made smaller to lower the threshold voltage, and the value of resistor 10 is made larger to make the threshold voltage higher. In this case, the threshold voltage for the vertical synchronization signal is low, making it resistant to synchronization loss. In the case of vertical signals, even if the pedestal portion of the horizontal synchronizing signal is affected, there is no problem because it is sufficiently attenuated by the low-pass filter 8. Further, since the threshold voltage is high for the horizontal synchronizing signal, synchronization will not be lost at the pedestal portion. Note that the horizontal synchronization signal is prone to synchronization loss, but since the horizontal is controlled by the AFC circuit, even if the synchronization signal is slightly lost, the AFC time constant circuit does not immediately cause synchronization loss, so there is no problem.

FIG. 3 is a circuit diagram showing another circuit which is a prerequisite for the present invention, and the same parts as in FIG. 1 are given the same numbers. Here, the resistor 4 is set to a large value and the threshold value is selected high. Therefore, as mentioned above, there is no problem with the horizontal synchronization output. Further, the comparator 13 compares it with a reference voltage 14 (which is selected to be lower than the base-emitter forward voltage of transistor 5 of about 0.7 V), and its output is applied to the vertical oscillation circuit via the low-pass filter 8. In this way, a low threshold value can be achieved for the vertical synchronization signal, resulting in a circuit that is resistant to loss of synchronization, as described above. In addition, Figure 3 shows that when integrated into an IC, only the capacitor 3 needs to be externally connected, which is the same as the conventional example.
The total cost increase is small.

The above is a case of positive synchronization, but FIG. 4 shows an embodiment of the present invention that deals with negative synchronization. 1st to 3rd
Components that are the same as those in the figure are given the same numbers. In the case of FIG. 4, the polarity of the input composite video signal 1 is in the synchronous negative direction, which is opposite to that of FIGS. 1-3. Therefore, during the period of the synchronous component in the composite video signal, the emitter current of the transistor 5 whose base is connected to the bias voltage source 17 flows to charge the capacitor 3, and during other periods, the capacitor 3 is discharged via the resistor 4. Although not shown, a constant current source may be used instead of the resistor 4). Therefore, although the operation is of opposite polarity to that in Figs. 1 to 3, there is basically no difference.

Since the synchronously separated output appears on the resistor 6 when the collector current of the transistor 5 is conductive, a threshold voltage that is shallower (operates with a small voltage drop across the resistor 6) is set by the first reference voltage 14. The output of the first comparator 13 is connected to the vertical oscillation circuit via the low-pass filter 8, and the output of the comparator 15, which has a significantly deeper threshold voltage set by the second reference voltage 16, is connected to the horizontal AFC circuit. By guiding, it is possible to realize a synchronization separation circuit that is resistant to sags and ghosts, similar to the circuits shown in FIGS. 2 and 3.

As described above, according to the present invention, by using a same base separation circuit with a high threshold for horizontal synchronization and a sync separation circuit with a low threshold for vertical synchronization,
The objective is to realize a synchronization separation circuit that is resistant to sags and ghosts. In addition to the methods described above, the threshold voltage can be controlled by, for example, changing the value of resistor 2 in Figures 2 and 3 (by changing the internal resistance of the signal source and adding a further resistor in series as necessary). Good too. Furthermore, it is clear that each component of the present invention can be modified as appropriate.

[Brief explanation of the drawing]

Figure 1 shows a conventional synchronous separation circuit, Figures 2 and 3
The figure is a prerequisite circuit of the present invention, and FIG. 4 is a circuit diagram of a synchronous separation circuit showing an embodiment of the present invention. 1...Composite video signal source, 2...Resistor, 3, 9...
...Capacitor, 4,10...Resistor, 5,11...
Transistor, 6, 12... Load resistance, 7... Power supply, 8... Low pass filter, 13, 15... Comparator, 14, 16... Reference voltage, 17... Bias voltage source.

Claims (1)

[Claims] 1. A composite video signal in which the polarity of the sync signal is sync-negative is supplied via a capacitor to the emitter of a transistor whose base is biased with a constant voltage and whose emitter is connected to a current source, and the collector output of this transistor is a first comparator having a threshold of 1 and a second comparator having a second threshold deeper than the first threshold, and receiving vertical and horizontal synchronization signals from the first and second comparators; A synchronous separation circuit characterized by obtaining the following.