JPS58173982A - Channel selection device - Google Patents
Channel selection deviceInfo
- Publication number
- JPS58173982A JPS58173982A JP57055425A JP5542582A JPS58173982A JP S58173982 A JPS58173982 A JP S58173982A JP 57055425 A JP57055425 A JP 57055425A JP 5542582 A JP5542582 A JP 5542582A JP S58173982 A JPS58173982 A JP S58173982A
- Authority
- JP
- Japan
- Prior art keywords
- afc
- voltage
- circuit
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/50—Tuning indicators; Automatic tuning control
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Receiver Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、テレビ受信機に使用される選局装置に関し、
特にP L L周波数シンセサイザ一方式を用いた選局
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device used in a television receiver,
In particular, the present invention relates to a channel selection device using one type of PLL frequency synthesizer.
P L L 周波数シンセサイザ一方式を用いた選局装
置では、固定分周器あるいは可変分周器により定められ
た分周比にしたがってチューナの局部発振周波数が決定
される。このため、希望チャンネル周波数が正規の周波
数よりずれている場合、たとえばCATV等のオフセッ
ト信号を受信する場合、あるいはVTRやビデオゲーム
をテレビ受信機に接続する場合、この周波数ずれが問題
となるこのだめ、このような方式においては、自動的に
その周波数ずれを補正することが出来る自動微調機能を
備えた選局装置が使用される。In a tuning device using one type of PLL frequency synthesizer, the local oscillation frequency of the tuner is determined according to a frequency division ratio determined by a fixed frequency divider or a variable frequency divider. Therefore, if the desired channel frequency deviates from the regular frequency, for example, when receiving an offset signal such as from CATV, or when connecting a VTR or video game to a TV receiver, this frequency deviation may cause a problem. In such a system, a tuning device is used that has an automatic fine adjustment function that can automatically correct the frequency shift.
しかしながら従来の方式では、AFC回路の出力電圧特
性により制御範囲が制限され充分広い自動微調が行なえ
ないという欠点がある〇本発明の目的は、上記した従来
技術の問題点をなくし、自動微調の引き込み範囲を広く
する選局装置を提供するにある。However, in the conventional method, the control range is limited by the output voltage characteristics of the AFC circuit, and a sufficiently wide automatic fine adjustment cannot be performed. The purpose of the present invention is to provide a channel selection device that widens the range.
本発明は、AFC回路の出力中点電圧を、第1のスレッ
シュホールド電圧より高く設定し、水平同期信号の有無
を検知する信号検知回路により、信号がない場合、第2
のスレッシュホールド電圧より低くなるようにAFC出
力電圧を下げて、自動微調の範囲を広げるようにしたも
のである。The present invention sets the output midpoint voltage of the AFC circuit higher than the first threshold voltage, and uses a signal detection circuit that detects the presence or absence of a horizontal synchronizing signal to detect the presence of a horizontal synchronizing signal.
The AFC output voltage is lowered so that it is lower than the threshold voltage of , thereby widening the range of automatic fine adjustment.
以下、本発明を第1図〜第4図を用いて説明する。The present invention will be explained below using FIGS. 1 to 4.
第1図は、本発明による選局回路の一実施例を示すブロ
ック図である。同図において、1はチューナ、2は映像
中間周波増幅器、3は同期分離及び水平発振回路を含む
偏向回路、4はAFC回路、5は水平同期信号と水平帰
線パルスにより信号を検知する検知回路、6はAFC出
力電圧の逆S字のHレベルを検知するためのスレッシュ
ホールド電圧を有する第1の比較器7はAFC出力電圧
の逆S字のLレベルを検知スルだめのスレッシュホール
ド電圧を有する第2の比較器、8はチューナの局部発振
信号を分周する固定分周器、9は選局操作キー10より
により各チャンネルに対応した分周及び比較器45によ
って制御される可変分周器、11は基準周波数発振器、
12は位相比較器、13はチューナに同調電圧を与える
低域フィルターを示す。今、選局操作キー10により所
望のチャンネルを選択したとすると、そのチャンネルに
対応した分局比を、可変分周器9に設定し、チューナの
バンド設定がなされる。FIG. 1 is a block diagram showing an embodiment of a channel selection circuit according to the present invention. In the figure, 1 is a tuner, 2 is a video intermediate frequency amplifier, 3 is a deflection circuit including a synchronization separation and horizontal oscillation circuit, 4 is an AFC circuit, and 5 is a detection circuit that detects a signal using a horizontal synchronization signal and a horizontal retrace pulse. , 6 has a threshold voltage for detecting an inverted S-shaped H level of the AFC output voltage.A first comparator 7 has a threshold voltage for detecting an inverted S-shaped L level of the AFC output voltage. A second comparator; 8 is a fixed frequency divider that divides the frequency of the local oscillation signal of the tuner; 9 is a variable frequency divider that divides the frequency corresponding to each channel by using the channel selection operation key 10 and is controlled by the comparator 45; , 11 is a reference frequency oscillator,
12 is a phase comparator, and 13 is a low-pass filter that provides a tuning voltage to the tuner. Now, if a desired channel is selected using the channel selection operation key 10, the division ratio corresponding to that channel is set in the variable frequency divider 9, and the band of the tuner is set.
第2図は、第1図に示されているA F’ C回路4、
検知回路5.比較器6.7の具体例である。FIG. 2 shows the A F'C circuit 4 shown in FIG.
Detection circuit 5. This is a specific example of comparator 6.7.
14は受像機のAFC回路、 15.16はAFC出力
駆動用トランジスタ、 17. iaはAFC中点電圧
を決定する負荷抵抗、19.20はAFC電圧のリップ
ルを除去するフィルター、21は水平同期信号の入力端
子、22は水平帰線パルス入力端子。14 is an AFC circuit of the receiver, 15.16 is an AFC output driving transistor, 17. ia is a load resistance that determines the AFC midpoint voltage, 19.20 is a filter that removes ripples in the AFC voltage, 21 is a horizontal synchronizing signal input terminal, and 22 is a horizontal retrace pulse input terminal.
23は水平同期信号と水平帰線パルスの一致をとるナン
ド回路、 24.25.26はナンド回路23の出力電
圧を平滑するフィルタ、27はナンド回路の出力電圧に
よりオン・オフするスイッチ回路。23 is a NAND circuit that matches the horizontal synchronizing signal and the horizontal retrace pulse; 24, 25, and 26 are filters that smooth the output voltage of the NAND circuit 23; and 27 is a switch circuit that is turned on and off depending on the output voltage of the NAND circuit.
28はAF’C負荷抵抗比を変えるだめの抵抗、29゜
30.31は、第1の比較器62、第2の比較器34の
スレッシュホールド電圧を決める抵抗、66は、Hレベ
ル時に自動微調の分周比を上げるように制御する制御端
子、34は、Hレベル時に自動微調の分周比を下げるよ
うに制御する制御端子である。28 is a resistor for changing the AF'C load resistance ratio, 29°30.31 is a resistor that determines the threshold voltage of the first comparator 62 and the second comparator 34, and 66 is an automatic fine adjustment at H level. A control terminal 34 is a control terminal that controls the automatic fine adjustment frequency division ratio to be lowered when the frequency division ratio is at H level.
第2図のAFC回路の負荷抵抗17.18は一般的には
同じ値に選んでいるが、この場合、第3図(a)に示す
様に電源電圧の中心より上下に対称にAFC電圧の逆S
字特性が出来る0ここで第1のスレツショル)” VH
、M 2のスレッショルドVl、を設定すると、図の様
にAFC中心周波数f1に対しfz’+f3’の周波数
範囲、各々の比較器の出力が得られる。これより自動微
調範囲は12/〜fa’となり、f2′以下、137以
上、受信信号のオフセットがあると中心に自動微調が出
来な4 ・
いことになる。The load resistances 17 and 18 of the AFC circuit in Figure 2 are generally selected to have the same value, but in this case, the AFC voltage is symmetrically set above and below the center of the power supply voltage as shown in Figure 3 (a). Reverse S
0 (here is the first threshold)” VH
, M2, the output of each comparator is obtained in a frequency range of fz'+f3' with respect to the AFC center frequency f1 as shown in the figure. From this, the automatic fine adjustment range is 12/~fa', and if there is an offset of the received signal below f2' or above 137, automatic fine adjustment cannot be performed at the center.
ここで、本発明は、AFC回路の負荷抵抗17゜18の
比を1:2以上アンバランスさせることにより第4図(
a)に示すようにA F C中点電位をずらせることが
出来る0又同期信号と水平帰線パルスによるナンド回路
26の出力の平衡電圧は、同調周波数が高めに約500
kllz以上ずれると水平同期信号がなくなり、第4図
(d)に示すようになる。この信号により、トランジス
タ27をオンさせて、さらにAFC中点電位を せるこ
とにより、第4図(a)に示したように点線部分を実線
のように下げることができる。Here, in the present invention, by unbalancing the ratio of the load resistances 17°18 of the AFC circuit to 1:2 or more, as shown in FIG.
As shown in a), the balanced voltage of the output of the NAND circuit 26 due to the zero synchronization signal and the horizontal retrace pulse, which can shift the AFC midpoint potential, is approximately 500% when the tuning frequency is high.
If the deviation exceeds kllz, the horizontal synchronization signal disappears, as shown in FIG. 4(d). By turning on the transistor 27 with this signal and further raising the AFC midpoint potential, the dotted line portion can be lowered as shown by the solid line as shown in FIG. 4(a).
この特性からもわかる様に、従来のAFC回路の出力電
圧に比べ、AFC中点電圧を上げかつ、信号がなくなる
ところではAFC電圧を下げた逆S字特性が得られる。As can be seen from this characteristic, compared to the output voltage of a conventional AFC circuit, an inverted S-shaped characteristic is obtained in which the AFC midpoint voltage is raised and the AFC voltage is lowered where the signal disappears.
ここで第1のスレッショルド電圧IVu I i 2の
スレッショルド電圧をvLの様に選ぶことにより、自動
微調分周比を上げる様に制御する信号が第4図(b)、
又、下げるように制御する信号が(c)のように得られ
る。By selecting the threshold voltage of the first threshold voltage IVu I i 2 as vL, the signal for controlling the automatic fine adjustment frequency division ratio to be increased can be obtained as shown in FIG. 4(b).
Further, a signal for controlling the voltage to be lowered is obtained as shown in (c).
以上のように、従来の制御信号がf2′〜fa’に比べ
f2〜f3と拡大することが出来、これにより自動微調
範囲を広げることが出来る。As described above, the conventional control signal can be expanded to f2 to f3 compared to f2' to fa', thereby widening the automatic fine adjustment range.
第1図は、本発明による選局装置の一実施例を示すブロ
ック図、第2図は、その主要部の具体的回路図、第6図
、第4図は′酸圧波形図である。
17、1B、 19.28・・・抵抗
27・・・トランジスタ
代理人弁理士 薄 1)利゛5幸
Iζ 。
、)5、−、++
・ 7 ・
察 1 図
第 z 目FIG. 1 is a block diagram showing an embodiment of the channel selection device according to the present invention, FIG. 2 is a specific circuit diagram of the main part thereof, and FIGS. 6 and 4 are acid pressure waveform diagrams. 17, 1B, 19.28...Resistance 27...Transistor agent patent attorney Usui 1) Profitability Iζ. , ) 5, -, ++ ・ 7 ・ Inspection 1 Figure zth
Claims (1)
帰線パルス信号とにより信号を検知する検知回路、前記
AFC回路の逆S字出力のHレベルを検知するだめの第
1のスレッシュホールド電圧を有する第1の比較器、前
記逆S字出力のLレベルを検知するための第2のスレッ
シュホールド電圧を有する第2の比較器、第1゜2の比
較器の入力電圧が第1の比較器のスレッシュホールド電
圧より高い場合は、前記第1の比較器の出力によりチュ
ーナの受信周波数を下げるように制御し、第2の比較器
のスレッシュホールド電圧より低い場合はチューナの受
信周波数を上げるように制御し、第1.2の比較器のス
レッシュホールド電圧範囲にあるときは受信周波数を一
定に保つ制御手段、検知回路が信号検知したときAFC
回路の出力電圧を低下させる修正手段からなることを特
徴とする選局装置。It has an AFC circuit connected to the tuner, a detection circuit that detects signals based on the horizontal synchronization signal and the horizontal retrace pulse signal, and a first threshold voltage for detecting the H level of the inverted S-shaped output of the AFC circuit. a first comparator, a second comparator having a second threshold voltage for detecting the L level of the inverted S-shaped output; If the voltage is higher than the threshold voltage, the output of the first comparator is used to control the reception frequency of the tuner to be lowered, and if it is lower than the threshold voltage of the second comparator, the reception frequency of the tuner is controlled to be increased. When the voltage is within the threshold voltage range of the 1st and 2nd comparators, the control means keeps the receiving frequency constant, and when the detection circuit detects the signal, the AFC
A channel selection device comprising a correction means for lowering the output voltage of the circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57055425A JPS58173982A (en) | 1982-04-05 | 1982-04-05 | Channel selection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57055425A JPS58173982A (en) | 1982-04-05 | 1982-04-05 | Channel selection device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58173982A true JPS58173982A (en) | 1983-10-12 |
JPH0131756B2 JPH0131756B2 (en) | 1989-06-27 |
Family
ID=12998219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57055425A Granted JPS58173982A (en) | 1982-04-05 | 1982-04-05 | Channel selection device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58173982A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60257680A (en) * | 1984-06-04 | 1985-12-19 | Sharp Corp | Video signal reception decision circuit |
JPS6327174A (en) * | 1986-07-18 | 1988-02-04 | Sanyo Electric Co Ltd | Synchronism detection circuit |
US6625431B1 (en) | 1999-12-17 | 2003-09-23 | Funai Electronics, Co.. Ltd. | Tuner device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54135811U (en) * | 1978-03-15 | 1979-09-20 |
-
1982
- 1982-04-05 JP JP57055425A patent/JPS58173982A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54135811U (en) * | 1978-03-15 | 1979-09-20 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60257680A (en) * | 1984-06-04 | 1985-12-19 | Sharp Corp | Video signal reception decision circuit |
JPS6327174A (en) * | 1986-07-18 | 1988-02-04 | Sanyo Electric Co Ltd | Synchronism detection circuit |
JPH0533876B2 (en) * | 1986-07-18 | 1993-05-20 | Sanyo Electric Co | |
US6625431B1 (en) | 1999-12-17 | 2003-09-23 | Funai Electronics, Co.. Ltd. | Tuner device |
Also Published As
Publication number | Publication date |
---|---|
JPH0131756B2 (en) | 1989-06-27 |
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