JPH0253867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital signal demodulation method used in information recording and reproducing systems such as magnetic tapes and magnetic disk devices, which converts 4-bit data into 8-bit data. This is a type of 4-8 conversion modulation system for recording and reproducing data, and provides a demodulation method for the FEM-4 modulation system, which has already been proposed by one of the inventors of the present invention.

Conventional configurations and their problems In general, digital magnetic recording has the characteristics of being able to economically record large amounts of information and to store it stably over a long period of time.Many methods have been developed to improve recording density. has been proposed. In the early days RZ
(Return to Zero), RB (Return to Bias),
NRZ (Non Return to Zero), NRZI (Non Return to Zero)
Return to Zero I), FM (Frequency
Modulation), MFM (Modified Frequency)
Modulation), M ² FM (Modified MFM), and more recently 4/5MNRZI, 3PM
(3Position Modulation), ZM (Zero
Modulation) etc. have been proposed.

In digital magnetic recording, the detection window width T _W
is large, the minimum magnetization reversal interval T min is large,
The maximum magnetization reversal interval T max is small, and the ratio of the linear bit density to the maximum magnetization reversal interval DR (Density
Ratio) is large, and the minimum magnetization reversal interval T
It is considered desirable to use a modulation method in which the product of min and the detection window width T _W is large and which is capable of self-clocking.

The modulation method that has traditionally been widely used is MFM.
In the case of this MFM, if the data period is T, T min = T, T max = 2T, DR = 1,
It has a performance of T _W = 0.5T, and is a well-balanced system overall.

Then, a modulation method aimed at even higher density was developed.
3PM, and in this 3PM case, T min = 1.5T,
It can be seen that it has the performance of T max = 6T, DR = 1.5, and T _W = 0.5T, and is an improved method for higher density. However, in the case of this 3PM, T max has significantly fallen from 2T of MFM to 6T, and therefore the recording and reproducing circuit, especially the reproducing circuit, requires various additional circuits for low frequency guarantee. The problem was that it increased complexity, and that the control circuit became complicated because the digital circuit was processed using binary codes, and 3PM used a signal processing method in 3-bit increments.

For the above reasons, while maintaining the performance of 3PM,
Furthermore, the FEM-4 modulation method already proposed by one of the inventors of the present invention improves the drawback of the maximum inversion period of 6T. This FEM
divides the data bit into 4-bit units, and divides the data into 4-bit units.
When converting data bits in units of bits into 16 different 8-bit code words, there must be at least 2 or more bits ``0'' between the bits ``1'' in the code word sequence, and at most 8 bits. 4-8 conversion is performed to include the following, and then NRZI modulation is performed. In the case of this FEM-4, T min
= 1.5T, T max = 4.5T, DR = 1.5, T _W = 0.5T
It has the performance of T while maintaining the characteristics of 3PM.
The max has been significantly shortened from 6T to 4.5T,
Also, the conversion format is not 3-6 conversion like 3PM, but 4-8 conversion and is suitable for digital processing.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a demodulation method capable of demodulating the FEM-4 modulated signal described above with a simple circuit configuration and at high speed.

Structure of the Invention The demodulation method of the present invention converts FEM modulated signals into
After demodulating the NRZI and dividing the serialized time series data into 8-bit units, the 3rd, 4th, 5th, 2nd,
This method is characterized by performing inverse transformation in the first order.

DESCRIPTION OF EMBODIMENTS The demodulation method of the present invention will be described below with reference to drawings of embodiments. Before describing the demodulation method of the present invention, the FEM-4 modulation rules will be described.

The FEM-4 modulation method consists of five conversion rules. The first modulation rule () is to divide the input into 4-bit units and then convert it into 8-bit data corresponding to the first output corresponding to the 4-bit input according to the conversion table shown in Figure 1. . The third modulation rule () is based on the input numbers shown in Fig. 1, when the input No. 2 is followed by the input No. 0 or No. 1, and the input No. or
If input No. 1 follows, input No. 4 is followed by input No. 0 or No. 1, and input No. 8 is followed by input No. 0,
and when input No. 9 is followed by input No. 0 and No. 1, and input No. F is followed by input No. 0, the 8th bit of the output of the former and the third bit of the output of the latter is both set to "1".

The fourth modulation rule () is that in the input No. of Figure 1, when the input of No. 4 is followed by the input of No. 2 or No. 5, the output of the former No. 4 is output as the first output. to the second output.

The fifth modulation rule () is that in the input No. of FIG. 1, the No. 1 input, No. 7 input, No. D input, or No. E is followed by the No. 0 input, and Then input No. 6 or No. 9 or No. A
This is to change the output for center No. 0 from the first output to the second output when an input of , an input of No. E, or an input of No. F follows.

The second modulation rule () is that in two consecutive outputs, the 7th bit of the former is "1" and the 8th bit is "0", and the 1st bit of the latter is "0". 1”, the former 7th
The 8th bit is set to “0”, the 8th bit is set to “1”, and the 1st bit of the latter is set to “0”.
It is to change each.

After converting the 4-bit data into 8-bit data as described above, serialize the data in order starting from the first one, and then convert the serialized data into
It is subjected to NRZI modulation and then recorded onto a recording medium.

Next, the configuration of the present invention regarding demodulation of the signal modulated and recorded as described above will be explained.

First, FIG. 2 shows an overall block diagram of the present invention. In FIG. 2, a signal recorded on a recording medium 1 is reproduced through a magnetic head 2 and a reproduction amplifier 3, and converted into a digital signal. At this point
Although the NRZI modulation remains active, the digital signal is demodulated by the NRZI demodulation circuit 4 and at the same time the synchronization clock is extracted. On the other hand, the synchronization signal extraction circuit 5 detects a synchronization signal that has been inserted and recorded in advance into the data during recording, and the control signal generation circuit 6 generates a desired control signal, thereby controlling the synchronization clock and the control signal. Then, the digital signal is divided into predetermined 8-bit units by the serial/parallel conversion circuit 7, and the FEM-4 demodulation circuit 8
It is demodulated by

Since the steps from the recording medium 1 to the serial/parallel converter circuit 7 are already known, the details will be omitted, and the configuration of the FEM-4 demodulation circuit, which is the main part of the present invention, will be explained below. First, from the output from the serial-parallel conversion circuit 7, among the three consecutive data in units of 8 bits, the fifth bit _L5 and the eighth bit _L8 are selected from among the older data in chronological order. , the central 8-bit chronologically current data P ₁ ~
A total of 11 bits of data are obtained, including all of _P8 and the third bit _N3 of chronologically new future data. For FEM-4 demodulation, inverse transformation is performed in the order of →→→→ among the five modulation rules described above. First, in two consecutive pieces of data, if the 8th bit of the former and the 3rd bit of the latter are both "1", the third conversion rule () is applied, and both are set to "0" at the same time. ”. After this, the fifth data within one data
If the th bit and the 8th bit are both "1" at the same time, the fourth conversion rule () is applied and both are set to "0" at the same time. After this, the 8th bit of the past data and the 3rd bit of the 1st and 2nd bits of the current data
is "0" at the same time, and the fifth bit of the current data is "1", the fifth conversion rule ()
is applied, and the fifth bit of the current data is set to "0" and the seventh bit is set to "1". After this, if the 8th bit of the past or present data is “1”, the second conversion rule () is applied, and if the 8th bit of the past data is “1” , the first of the current data
If the 7th bit in the current data is 0 and the 8th bit is 1, the 7th bit is set to 1.
shall be. If the above conversion is performed, all special conversions corresponding to the second to fifth modulation rules are completed, and what remains is the inverse conversion from the first output to the input of the first conversion rule () shown in Figure 1. It only applies the rules. However, in this case, since the 8th bit is always "0", 7-4 conversion is actually performed, and demodulation is completed after this inverse conversion is completed.

FIG. 3 shows the flow of the above inverse conversion using logical symbols, and FIG. 4 shows a timing chart of the input/output relationship. However, in Figure 3, 1
1 to 17 are AND gates including inverters, 18
is a 4-input AND gate, 19 to 21 are OR gates,
9 is the matrix of 7-4 transformation, 10 is the above 7-4 transformation matrix.
This multiplexer multiplexes the parallel outputs of the four conversion matrices 9 and outputs them in series.

In addition, although the above example shows the case where this digital demodulation method is configured purely with combinational circuits, it can be easily realized using a commercially available general-purpose digital IC, and it is also possible to implement it using a commercially available general-purpose digital IC.
Programmable Logic Array) etc.
This can be realized with a simpler configuration. Commercially available FPLA
FIG. 5 shows an example of a configuration using "82S153". In this example, a two-stone FPLA is used, and in FPLA-1, 7-4 in Fig. 3 is used.
Immediately before the conversion, in FPLA-2, logical operations after the 7-4 conversion in FIG. 3 are performed. The input/output logical relational expressions for both FPLAs are shown below.
However, the variable symbols are as shown in FIG.

[FPLA-1] S ₁ = P ₁ + ₅・L ₈・₃ S ₂ = P ₂ S ₃ = P ₃・₈ S ₄ = P ₄ S ₅ = P ₅・( ₈ +N ₃ )・(P ₁ +P ₂ + L ₈ ) S ₆ = P ₆ S ₇ = P ₇ + ₁・₂・P ₅・₈ ( ₈ + N ₃ ) + ₅・P ₈・₃ [FPLA−2] X ₁ = _{1 3 4 5} S _{6 7} + _{1 2} S _{3 4 5 7} + _{1 2 3} S _{4 5 6} S ₇ + S _{1 2 3} S _{4 5 6 7} + _{1 2} S _{3 4 5 6} + S _{1 2 3 4} S _{5 6 7} X ₂ = _{1 2 3} S _{4 5 6 7} + _{1 2} S _{3 4 5
7} +S _{1 2 3 5 6} S ₇ + _{1 2} S _{3 4 5 6} +S _{1 2 3 4 5} S _{6 7} +S _{1 2 3 4} S _{5 6 7} X ₃ = ₁ S _{2 3 4 5 6} + _{2 3} S _{4 5 6} S ₇ + _{1 2} S _{3 4 5} S _{6 7} + ₁ S _{2 3 4 5 7} + S _{1 2 3 4 5} S _{6 7} + S _{1 2 3 4} S _{5 6 7} X ₄ = ₁ S _{2 3 4} S _{5 6 7} +S _{1 2 3} S _{4 5 6 7} +S _{1 2 3 4 5 6} S ₇ + _{1 2} S _{3 4 5 6} S ₇ + ₁ S _{2 3 4 5 6} S ₇ + ₁ S _{2 3 4 5} S _{6 7} +S _{1 2 3 4 5} S _{6 7} +S _{1 2 3 4} S _{5 6 7} SO=ABX ₁ +BX ₂ +AX ₃ +X _4Effects of the Invention As detailed above, the digital demodulation method of the present invention uses only pure combinational circuits. Because of its configuration, it has the characteristics of a simple hardware configuration and high-speed demodulation. Therefore, it has the advantage that it can be implemented as an IC much more easily than the conventional configuration using sequential circuits, and can also be used in high-speed processing equipment.

[Brief explanation of the drawing]

Figure 1 is a conversion table diagram of the FEM-4 modulation method.
FIG. 2 is a diagram showing the overall block of the present invention, FIG. 3 is a logic circuit diagram of the FEM-4 demodulation circuit which is the main part of the present invention, FIG. 4 is a timing chart of the same, and FIG.
The figure is a circuit diagram showing another embodiment of the FEM-4 demodulation circuit of the present invention. 8...FEM-4 demodulation circuit, 9...4-8 modulation matrix, 10...Multiplexer, 11~
17...AND gate including inverter, 18...
...4-input AND gate, 19-21...OR gate.

Claims (1)

[Scope of Claims] 1 Data bit is divided into 4-bit units, the 4-bit unit data bits are converted into 16 different 8-bit code words, and the minimum magnetization reversal interval T
min is 1.5T, maximum magnetization reversal interval T max is 4.5T,
Ratio of linear bit density to maximum magnetization reversal density DR
Demodulation of a digitally modulated signal modulated to include at least 2 bits or more and at most 8 or less bits between bits 1 and 1 of the code sequence so that the detection window width _T is 1.5 and the detection window width T is 0.5T. In this process, the modulated data is demodulated using NRZI, and a match detection signal is generated when each bit of continuous time-series codeword data in 8-bit units and a preset codeword completely matches the preset codeword. Then, using this coincidence detection signal, the time-series code word data is divided into desired 8-bit units, and is further converted into parallel data, so that among the three consecutive time-series signals in 8-bit units, the past 8 bits that are older in time series are The 5th and 8th data bits in the data, all of the chronologically central current 8-bit data, and the 3rd data bit in the chronologically new future 8-bit data. A total of 11 bits are obtained, and among this input 11-bit data, the 8th bit in the past data and the 3rd bit in the current data are simultaneously “1”.
If the 8th bit in the current data and the 3rd bit in the future data are 1 at the same time, the 8th bit in the current data After completing this process, if the 5th bit and the 8th bit in the past data are both “1”, the 8th bit in the past data is The 8th bit is set to "0", and if the 5th bit and the 8th bit in the current data are both "1", they are both set to "0" at the same time. After the end of the data, the 5th bit in the current data is "1", and the 1st, 2nd, and 8th bits in the past data are simultaneously "0". ”, the 5th bit in the current data is set to 0 and the 8th bit is set to 1, and after this processing is completed, the data in the past data is If the 8th bit is "1" and the 1st bit in the current data is "0", the 1st bit in the current data is set to "1", and the current data If the 7th bit of the current data is "0" and the 8th bit is "1", the 7th bit of the current data is set to "1", and this processing ends. rear,
A digital signal demodulation method characterized in that new 4-bit data is demodulated in accordance with a combination of the first to seventh bits of current data according to a preset next conversion algorithm. 00000010→0000 00000100→0001 00010000→0010 00100000→0011 01000000→0100 00010010→0101 10010010→0110 00100100→0111 01001000→10 00 10010000→1001 10000010→1010 00100010→1011 01000010→1100 01000100→1101 10000100→1110 10001000→1111 2 In advance 2. The digital signal demodulation method according to claim 1, wherein a code word corresponding to a synchronization signal of a binary code set to an integral multiple of 4 bits is used as the set code word.