JPH0253263A - Code converter and decoder - Google Patents

Abstract

PURPOSE:To eliminate an effect of low frequency noise by converting information languages, each having M bits into channel codes, each having N bits, where N>M, classifying them into specific 1st group - 4th group and making the 1st group and the 2nd group discriminatable with their added codes. CONSTITUTION:The information languages, each having M bits are converted into the channel codes, each having N bits, where N>M, and moreover they are classified into the 1st group - the 4th group, whereas the 1st group and the 2nd group having the same number of 1, while optional two out of the 3rd group and the 4th group have at least >= or <=3 in the number of 1 as compared with the 1st group and the 2nd group. Then, as to the 1st group, the information language of M bits or its one part is added with an appropriate code by a channel code generating means 1, while as to the 2nd group, what the information language of M bits is converted is added by a channel code generating means 2 with an appropriate code, thus enabling both groups to be discriminated by their added codes. By this method, the number of 1 contained in the regenerated channel code can be in a specified number, and hence an effect of low frequency noise, such as DC drift is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a code conversion device that converts any information word written in binary values of 1 and O into a channel code suitable for recording and transmission, and the channel code thereof. This invention relates to a decoding device that reversely converts the original information word.

BACKGROUND OF THE INVENTION In recent years, code conversion devices have become indispensable for digital recording and communication.

Hereinafter, an example of the above-mentioned conventional code conversion device will be described without reference to the drawings.

3 and 4 show the conversion rules in the conventional code conversion device, that is, according to the conversion rules shown in FIG.
(10110100011000011
) is the binary information word (01001000100100
000010000001000010000). This conversion method is called (2,7) conversion, and is a conversion method frequently used in magnetic recording and the like.

(For example, U.S. Patent No. 3,689.899) Problems to be Solved by the Invention However, in the above method, the number of 1's and the number of 0's in the channel code are generally not equal, so especially when using an optical disc, When this is directly recorded on a medium, there is a problem that DC drift occurs in the reproduced signal when it is reproduced after being recorded on the medium, and it is easy to make an error when determining whether it is 1 or O based on the reproduced signal. . In other words, the reproduction signal of an optical disc originally contains low-frequency noise components such as DC drift caused by differences in the reflectance of the medium surface and differences in recording sensitivity during recording, and these must be removed before demodulation. It is necessary to keep it.

However, in this (2,7) conversion method, since the reproduced signal itself also has low frequency components, it is difficult to separate the two. For this reason, it is susceptible to the influence of low frequency noise components and reading errors are likely to occur.

In view of the above problems, the present invention provides a code conversion device and a decoding device that are less susceptible to the effects of low frequency noise.

Means for Solving the Problems In order to solve the above problems, the code conversion device of the present invention converts an M-bit information word into an N-bit channel code where N>M, and the N-bit channel code is , the first group, the second group, the third group, and the fourth group.
All channel codes classified into groups 1 and 2 have an equal number of 1, and any two channel codes included in groups 3 and 4 have an equal number of 1 for group 1 or group 2.
The number of channel codes belonging to the first group is obtained by adding an appropriate code to the M-bit information word or a part thereof, and the channel code belonging to the second group is The channel code is obtained by adding an appropriate code to the converted M-bit information word, and the added code makes it possible to distinguish between the first group and the second group. .

Effect of the Invention With the above-described configuration, the present invention can set the number of 1's included in the repopulated channel code to a predetermined number, and as a result, the channel bits of the input channel code are sorted in descending order of likelihood. By determining only a predetermined number of bits as 1, it is possible to determine whether each channel bit is 1 or 0 without being affected by low-frequency noise such as DC drift, making it possible to read channel codes accurately. . Furthermore, the first group of channel codes can be generated by simply adding an N-M bit code to an M-bit information word, and the conversion requires less circuitry than when all information words are converted to all channel bits. The scale can also be small.

The basic concept of the present invention will be explained in detail below.

When converting an M-bit information word into an N-bit channel code where N>M, the number of 1's included in each channel code is always a predetermined number (i out
of N) If the conversion rules are determined, the channel code can be accurately read from the input channel signal. This is because a channel signal can be sampled for each channel bit, and a predetermined number of bits can be determined to be 1 from the sampled values in descending order of luminous intensity. In this way, sample values for each bit are relatively compared in channel code units, making it less susceptible to low frequency noise components.

Once the number of bits M of the information word is determined, the number N of bits of the channel code that allows such conversion is N Ci ≧ 2'
It is determined from combinations that satisfy ``.'' As an example, Table 1 shows the correspondence between M, N, and i.

Table 1 Table 2 shows an example of two cases separated by 3 or more, and each represented by i and j.

Table 2 Here, M, N, and i are determined as a combination that satisfies 80, ≧ 2''', and N is the minimum for each M.

On the other hand, the smaller the N7M ratio is, the more efficient the channel code transfer becomes. 1 included in the channel code
The value of N can be made even smaller than that shown in Table 1 if multiple values are allowed instead of making the number the only one. However, if the plurality of values allowed as the number of 1 are too close together, it is difficult to identify them, and reading errors are likely to occur. As a result of studying this point, the inventors found that if the multiple values allowed as the number of l are separated by 3 or more from each other, it is possible to accurately identify the number of 1's included in the input channel code. I found out. So the numbers of 1 are mutually here, M, NX i, j
satisfies C, + NCJ ≧ 2'''. Comparing with Table 1, it can be seen that N for each M can be reduced by 1. In the above manner, the code is efficiently converted into channel signal de, and This allows the input channel signal to be read accurately.

Embodiment Below, a code conversion device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a code conversion device in an embodiment of the present invention. In FIG. 1, 100 is a discriminator, and the input 8-bit information word a6a (aza
8 depending on the number of l included in saaasahat
It is determined which group the bit information word belongs to, and the subsequent processing method is selected. 1.2.3 are a first channel code generation means, a second channel code generation means, and a third channel code generation means, respectively, and the first channel code generation means l generates the first group of channel codes. , the second channel code generation means 2 generates the second group of channel codes, and the third channel code generation means 3 generates the third and fourth groups of channel codes from 8-bit information words. .

Groups will be discussed later.

The components of the first channel code generation means 1 will be explained. Reference numeral 11 denotes an additional code generator, which generates a 2-bit additional code according to the contents of the 8-bit information word.

Reference numeral 12 denotes an additional code generator, which generates a 4-bit additional code according to the contents of the upper 6 bits of the 8-bit information word.

Next, the components of the second channel code generation means 2 will be explained. A discriminator 21 generates a flag F depending on the number of 1's included in the 8-bit information word. 22 is a logic inversion means which holds the logic of the 8-bit information word when the flag F is 0, and inverts the logic when the flag F is 1.

23 is ROM (read only memory)
: read-only memory), reads out the 6-bit code corresponding to the 8-bit information word that has been appropriately processed by the logic inversion means 22,
Output. Reference numeral 24 denotes an additional code generator, which generates two types of additional codes depending on the value of the flag F.

Next, the components of the third channel code generation means 3 will be explained. 31 is a conversion table which converts an 8-bit information word into a 10-bit channel code. 32
is a sequential logic inversion means, which sequentially holds and stores the logic of the 10-bit channel code generated by the conversion table 31.
Invert. The above are the constituent elements of the third channel code generation means 3.

Reference numeral 4 denotes an output selection means, which selects the outputs of the first, second, and third channel code generation means 1, 2.3 according to the value of the discrimination flag G of the discrimination i 100, and generates the channel code b. Let b+bzbsbabsbibtbsbw. 41 and 42 are large capacity buffers for temporarily holding the output of the first channel code generation means 1, and 43 and 44 are inputs for temporarily holding the outputs of the second and third channel code generation means 2 and 3, respectively. It is a buffer.

The operation of the code conversion device configured as described above will be described below with reference to FIG. 1, Tables 3 and 4.

Table 3 Table 4 First, the operation of the discriminator 100 will be explained.

(2) When the number of 1's included in the input information word a6aHaza3a4aSaha'r is 3.4 or 5, the information word is transferred to the additional code generator 11 of the first channel code generation means 1.

■ Input information word aoalaza3a4a3a6a7 to 1
When there are two 1s and further a6a7=oO, or there are six 1s in the input information word aoalaza3a4a5a6a7 and further a.

When at=11, the information word is transferred to the additional code generator 12 of the first channel code generating means 1.

■ Input information word a. When a+aza3aaa5athal or a@alala3aaasaba is any of the information words shown in Table 3, the above information word is transferred to the second channel code generation means 2.

(2) When the input information word aoarazasaaaSaha7 is any of the information words shown in Table 4, the information word is transferred to the third channel code generation means 3.

Next, the functions of each channel code generation means will be described. First, the first channel code generation means will be explained. The additional code generator 12 generates a 10-bit channel code by adding a 2-bit code to the 8-bit information word sent from the discriminator 100. Its content is determined by the number of 1's in the 8-bit information word. In other words, the 10-bit channel code is (a) When there are 5 1s...aOa1a2a,
When there are 4 a4a, a6a, 00(c)1...
・・aoa+azasa<asabaq 01(C)
When there are three 1's..."aoa+azazaaasa
ba? It becomes 11. For example, a, a, a, a, a, asaha-r = 11001
When it is 001, add 01, bob+tlzb3')4bsbabJ*bw = 1
100100101. According to this, a 10-bit channel code always contains 5 1's,
The 5-out-of-10 code described above can be easily implemented. The number of 10-bit channel codes that can be generated in this way is sca + ace + sc * = 182.

When there are two or six 1's in an 8-bit information word, the additional code generator 11 generates a channel code as follows.

(d) When there are two 1's and a, a1=00...
・・a(1alazala4asllOO(e)1 is 6
, and a, a, = 11, then one--a, a, a
, asaaas00L.

In this case as well, a 5-out-of-10 code is generated. The channel code that can be generated by this is zcb
+4C&=30 ways. In this way, what is created by adding an appropriate bit code to an 8-bit information word or a part thereof (L bits) will be referred to as the first group of channel codes.

The second channel code generation means and the third channel code generation means convert 8-bit information words other than those mentioned above into 10-bit channel codes. The second channel code generation means generates a 6-bit code C6C corresponding to the 8-bit information word or its inverse logic code when it is shown in Table 3.
ICzC3CnCs is obtained from the conversion table 23, and an additional code generator 24 adds a 4-bit code. That is, ge) a6ala2a3anasab
When at is in Table 3, "'"・C0CtCzC+Cn
CnC50110 (a6a, aza3a, aSa6a7
When is in Table 3"'...'CoC+CzCzCaC
By setting slO10, a bit channel code is generated. C@CIC1C3C4C5 is 3-out-
of-6 code, resulting in a channel code of 5-out-.

It becomes f-10. The discriminator 21 determines the logicality of the 8-bit information word, that is, whether it is the case (f) or the case (g).
If g), the logic of the 8-bit information word is inverted. Whether or not the logic is to be inverted is transmitted to the logic inverting means 22 and the additional code generator 24 using a flag F. Additional code generator 24
The additional code is 0110 or 101 depending on the value of flag F.
Let it be O. In this way, by adding an appropriate 4-bit code to the 8-bit information word converted to 6-bit (H=), the resulting 5-out-of-10 is called the second group of channel codes. Make it.

The number of channel codes is 20 for both positive logic codes and negative logic codes.

Here, the role of the additional code will be explained in more detail. The main purpose of the additional code is to make the number of 1's equal to 5 by adding it to an information word or a part thereof, but this operation converts two or more different 8-bit codes into the same 10-bit channel code. It must not be In other words, the additional code must be able to identify by itself the group to which the channel code belongs. In this example, the additional code is , and if you look at the lower 2 bits, it is the first 2-bit addition.
You can identify the group, and if you look at 4 bits further, you can see 4
A first group and a second group of bit additions can be distinguished.

Therefore, the total number of channel codes generated by the above rules is 182 + 30 + 20 + 20 = 252, which is 5, the total number of out-of-10 codes SCI
. −252 and therefore according to the above method all 5
-out-of-10 codes can be made to correspond to 8-bit information words.

However, the information word that can be described with 8 bits is 2'' −
There are 256 types. Therefore, the above 5-out-of-10
The code cannot describe all of the 8-bit information words.

The third channel code generation means 3 uses these remaining four (
=256-252). That is, α'4 a+1alaza:+ana5al, when a7 is in Table 4, 9°°"' 6) eI14e3134
Outputs ese6e7eseg. According to this, of the information words of 8 pits (・, those in Table 4 are 2-out-of
-10 is converted to a 10-bit channel code.

The conversion table 31 is described in Table 4. It electrically implements the conversion rules.

Since the number of corresponding information words is four, which is a small number, the conversion table 2 can be constructed only from channel codes in which two 1's are always adjacent. In this way, when decrypting 1
It becomes easier to identify that the number of is two. The reason is as follows. It is assumed that an input channel signal is sampled for each channel bit, and the sampled values are ranked in descending order of likelihood of 1. At this time, in a state without noise, generally, the two sample values corresponding to 1 are followed by the sample values corresponding to 0, which is closest to 1, and then the sample values are ranked in order.

This is because 0, which is close to 1, is easily influenced by 1.

Since the number of 0s adjacent to 1 is at most 2, the sample value with the fifth rank is at least 2 bits away from 1, so the likelihood of 1 is quite low, and two 1s are adjacent to each other. Therefore, the likelihood of sample values corresponding to these 1s is quite high. Therefore, there is a large difference in the likelihood of 1 between the first and fifth sample values in this order, making it extremely easy to distinguish them from channel codes containing five l's.

The sequential logic inversion means 32 inverts the logic of the output code of the conversion table 31 every other time. This is due to the following reason. In the first and second channel code generation means 1.2, a 5-out-of-10 code was generated, but here it is a 2-out-of-IQ code, resulting in D
C fluctuation occurs. So next, conversion table 31 to 1
When a 0-bit code is output, its logic is inverted,
If an 8-out-of-10 code is used, DC fluctuations will be canceled on average.

Next, when a 10-bit code is output from the conversion table 31, it is passed through without inverting the logic, and this process is repeated from now on. eoe+El! 1338aEls
e & El? elle9 is the third group, 136eIf3zEl
Let xeaeseheteseq be the fourth group.

The output selection means 4 is for selecting the outputs of the channel code generation means from the first group to the fourth group. Of course,
Since it must correspond to the selection result of the channel code generation means by the discriminator 100, the flag G output from the discriminator 100 determines whether the IO from the corresponding output
Let the bit code be the channel code. Input buffers 41, 42, 43, and 44 temporarily store channel codes. By connecting any one of these input buffers to the output according to the flag G, the processed output of the channel code generation means can be correctly output as a channel code.

Note that the conversion table shown in this embodiment is not limited to a ROM table or the like made of semiconductor. It may be constructed of logic circuits as long as it performs an equivalent function.

Furthermore, in this embodiment, an additional code is added to the lower order of the 8-bit information word; This method is not necessarily limited to this method. For example, the information word may be divided appropriately and an additional code may be provided between them.

Next, a decoding device that decodes the channel code converted by the code conversion device in this embodiment will be described.

FIG. 3 is a schematic configuration diagram of a decoding device in an embodiment of the present invention. In FIG. 3, reference numeral 14 denotes a binarization means, which reads the input channel signal and generates a channel code expressed in binary. 50 is 5-out-o
51 is a 2-out-of inverse conversion means for decoding the 10-bit channel code of f-10 into an 8-bit information word;
This is inverse conversion means for decoding a 10-bit channel code of -10 or 8-out-of-10 into an 8-bit information word.

The operation of the decoder configured as above will be explained below. It is assumed that the channel code code-converted by the code conversion device in the above embodiment is transmitted and input as a channel signal. This channel signal may be transmitted through a transmission path or may be reproduced from a recording medium. The signals that have passed through the transmission path in this way are not necessarily binary;
Contains various distortions and noises. Therefore, the binarization means 14
operates in the following steps.

■ Sample the input channel signal in synchronization with the channel clock for each channel bit, and divide it into channel code units.

■ Rank the sample values in descending order of size.

■ The first and fifth sample values are compared, and if the difference is greater than a predetermined value, it is determined that the channel code is 2-out-of-10, that is, the third group of channel codes, and the inverse conversion means 51 is followed. is converted back into information words.

■ Compare the 6th and 10th sample values, and if the difference is greater than a predetermined value, it is determined that the channel code is 8-out-of-10, that is, the channel code of the 4th group, and the inverse conversion means 51
Convert back to information word according to .

■ 5-o if neither group 2 nor group 3
ut-of40, that is, the channel code of the first group or the second group, and is inversely converted into an information word according to the inverse conversion means 50.

The inverse transformation means 50 operates as follows.

(a) Lower 2 bits of channel code, b, b,
is 00.01.11, then bobxbzb*
b<bqbbbt is an 8-bit information word a. a+azaza
4asaaat.

(b) Lower 4 bits of channel code, bab7
When bsbq is 0011, bob+bzbi
b4bsoO as 8-bit information word aoala, a3a4a
Let's say saha.

(C) Lower 4 bits of channel code, b, b,
b, b.

is 001O, then b@b+btbJabsl
l is an 8-bit information word a6ala2a3a*asaba7
This is the case where 0 or more are the first group of channel codes.

(d) Lower 4 bits of channel code, bbbJ
When sbq is 0110, the inverse conversion table having the conversion rules in Table 3 is used. b+bgbst) 8-bit information word a, alaza3a4a3a, a corresponding to sbs
, find.

(e) Lower 4 bits of channel code, babt
When bsbw is 1010, the 8-bit information word aoa+azasa4asaia corresponding to bobrbzbsbabs is obtained from the inverse conversion table having the conversion rules in Table 3.
Find t and its inverse logic a6atazasanasaia
Let t be an information word.

The above is the second group. Furthermore, the inverse transformation means 51 operates as follows.

(f) Channel code is 2-out-of-10
In the case of 8-out-of-10, the corresponding 8-bit code from the inverse conversion table having the conversion rule of Table 4 is used as the information word, and in the case of 8-out-of-10, the 8-bit code corresponding to the logically inverted channel code is used as the information word.

The former is in the third group and the latter is in the fourth group, which is 0 or more, so that the channel signal can be accurately inversely converted into an information word.

In the above-described embodiment, two types of channel codes are associated with a specific information word, and a DC-free code is created in which the DC component does not fluctuate. However, since the decoding device according to the present invention is not affected by fluctuations in the DC component, It is not necessary to make it DC free in this way, for example, 2-out-of-1
8-out-of-10 for a channel code of 0
There is no problem even if the configuration does not use the channel code.

Furthermore, the configuration of the conversion table can be modified in various ways, and is not limited to this configuration in any way.

Effects of the Invention As described above, the present invention converts an M-bit information word into an N-bit channel code where N>M, and the N-bit channel code is divided into the first group, the second group, and the third group. , the channel codes classified into the fourth group, the first group and the second group all have an equal number of 1's, and any two channel codes included in the third group have at least the same number of 1's. The first group of channel codes is generated by adding an appropriate code to an M-bit information word or a part thereof, and the second group of channel codes is generated by adding an M-bit information word to an H-bit I.・It is generated by adding an N−N bit code to the code converted to the code, and then the first group and the second group are
By making the groups distinguishable, it is possible to determine whether each channel bit is 1 or 0 without being affected by low-frequency noise such as DC drift, and furthermore, the channel code of the first group is simply information. Since it can be generated by simply adding a code to a word, the circuit scale required for conversion is smaller than when all information words are converted into all channel bits.

In addition, the number of 1's included in the channel code is determined from the relative relationship of the sampled values obtained by sampling the input channel signal at the position of each channel bit, and the number of 1's included in the channel code is determined in descending order of likelihood from among these sampled values. a binarization means that generates a channel code by determining that the number of bits in the number is 1; and an inverse conversion means that inversely transforms the channel code generated by the binarization means to obtain an information word. With this, it is possible to obtain a decoding device that effectively inversely converts a channel signal transmitted with a channel code converted by the code conversion device into an information word.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a code conversion device according to an embodiment of the present invention, FIG. 2 is a schematic block diagram of the decoding device, and FIGS. 3 and 4 are conceptual diagrams explaining the operation of a conventional example. . 1.2 and 3...Channel code generation means, 11, 12...Additional code generator, 14...
... Binarization means, 23, 31 ... Conversion table, 32 ... Sequential logic inversion means, 50.51
...Inverse conversion means. Name of agent: Patent attorney Shigetaka Awano 1 person 100-1 row J') JL

Claims (7)

[Claims] (1) A code conversion device for converting an information word consisting of M bits of information bits into a channel code consisting of N bits of channel bits larger than M, wherein the channel code is converted from a channel code having i number of 1s. the first group and the second group configured, and j≦i−3 or j
The above information word,
or a first channel code generating means for generating an N-bit channel code belonging to the first group by adding an appropriate code to a part of the information word; and a second channel code generating means for generating an N-bit channel code belonging to the second group by adding an N-H bit code to the code; A code conversion device characterized in that a first group and a second group are distinguishable. (2) The channel code consists of a first group and a second group consisting of channel codes having i number of 1s, and j≦i
-3 consisting of channel codes with j 1's, and a fourth group consisting of channel codes with k 1's where k = 2i-j. Information words are converted into channel codes belonging to the first group or second group, and other information words are converted to channel codes belonging to the third group or fourth group. 2. The code converting device according to claim 1, wherein the code converting device selects and converts in such a manner that fluctuations in the DC component of the column are reduced. (3) The first channel code generating means is a first channel code generator that adds a code of N−M bits to M bits constituting the information word.
additional code generator, and N− bits of M bits.
2. The code conversion device according to claim 1, further comprising a second additional code generator that adds an L-bit code. (4) The code conversion device according to claim (2), wherein M is 8, N is 10, i is 5, j is 2, and k is 8. (5) The code conversion device according to claim (3), wherein M is 8, N is 10, L is 6, and H is 6. (6) A decoding device for decoding the channel code generated by the code conversion device according to claim (1), wherein the input channel signal is sampled at the channel bit position to obtain N sample values. , determine the number of 1's that should be included in the channel code from the relationship between these sample values, and consider the sample values as 1's in the order of the sample values determined above, starting from the one with the highest likelihood. binarizing means for generating a channel code; and a channel code belonging to a first group or a channel code belonging to a second group based on the code added at a predetermined position of the channel code read by the binarizing means. What is claimed is: 1. A decoding device characterized by comprising an identification means for identifying a decoding device. (7) If the N-bit channel code belongs to the first group, remove the bit at a predetermined position from the channel code, or add an appropriate code to the removed bit to make M bits. If it belongs to the second group, the code obtained by removing bits at a predetermined position is converted into M bits according to a certain rule, or the logic is further inverted. 7. The decoding device according to claim 6, further comprising decoding means for decoding.