JPH0225118A - Code converter and decoder - Google Patents

Abstract

PURPOSE:To evade low frequency noise by converting an M-bit information word into part of bit group in an N-bit channel code (N>M) and providing 1s of equal number to the N-bit channel code. CONSTITUTION:In the case of converting M-bit information word into an N-bit channel code (N>M), when the conversion rule is decided so that number (i) of 1s included in each channel code is always a prescribed number, the channel code is read accurately from the inputted channel signal, because the channel signal is sampled for each channel bit and a prescribed number of bits of the sampling values is discriminated to be logical 1 in the order of higher likelihood. Thus, since the sampled value for each bit is compared relatively in the unit of channel code, the effect of noise component at a low frequency is hardly made susceptible.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a code conversion device that converts any information word written in binary values of 1 and O into a channel code suitable for recording and transmission, and the channel code thereof. This invention relates to a decoding device that reversely converts the original information word.

BACKGROUND OF THE INVENTION In recent years, code conversion devices have become indispensable for digital recording and communication.

An example of the above-mentioned conventional code conversion device will be described below with reference to the drawings.

8 and 9 represent the conversion rules in the conventional code conversion device, that is, the conversion rules shown in FIG. 8 (10110100011000011)
It is possible to convert a binary information word such as [0101000010QO] into a channel code such as [0101000010QO]. This conversion method is called (2°7) conversion, and is a conversion method frequently used in magnetic recording and the like (for example, US Pat. No. 3,689,899).

Problems to be Solved by the Invention However, in the above method, the number of 1's and the number of O's in the channel code are generally not equal, so especially when recording directly on an optical disc, it is difficult to play back after recording on the medium. There is a problem in that DC drift occurs in the reproduced signal, making it easy to make an error when identifying whether it is 11pO from the reproduced signal. In other words, the playback signal of an optical disc originally contains low-frequency noise components such as DC drift caused by differences in the reflectance of the medium surface and differences in recording angle of 18 degrees during recording, and these must be removed before demodulation. There is. However, in this (2,7) conversion method, since the reproduced signal itself also has low frequency components, it is difficult to separate the two. For this reason, it is susceptible to the influence of low frequency noise components and reading errors are likely to occur.

In view of the above problems, the present invention provides a code conversion device and a decoding device that are less susceptible to low frequency noise.

Means for Solving the Problems In order to solve the above problems, the code conversion device of the present invention converts an M-bit information word into a partial bit group of an N-bit channel code where N>M. , and the above N
The focus channel codes have an equal number of 1's.

Effect of the Invention With the above-described configuration, the number of 1's included in the reproduced channel code is determined to be a predetermined number, so the channel bits of the input channel code are sorted into a predetermined number in order of likelihood. By determining only the bit as 1, it is possible to determine whether each channel bit is 1 or O without being affected by low-frequency noise such as DC drift, making it possible to read the channel code accurately. Since the information word is converted into a partial bit group of the N-bit channel code, the circuit scale required for the conversion is smaller than when converting the information word into all channel bits.

EXAMPLES The basic concept of the present invention will be explained in more detail below.

When converting an M-bit information word into an N-bit channel code where N>M, the number i of l included in each channel code is always a predetermined number (iouLofN
) By determining the conversion rules, it is possible to accurately read the channel code from the input channel signal.

This is because a channel signal can be sampled for each channel bit, and a predetermined number of bits can be determined to be 1 from the sampled values in descending order of likelihood. In this way, sample values for each bit are relatively compared in channel code units, making it less susceptible to low frequency noise components.

Once the number M of bits of the information word is determined, the minimum number N of bits of the channel code that allows such conversion is uniquely determined. Table 1 shows the correspondence between M, N, and i.

Table 1 where M, N, i are NC, ≧2P'... (1
) among the combinations satisfying N
is determined as the minimum value.

On the other hand, the smaller the N7M ratio, the better the efficiency of channel code transfer. l included in channel code
The value of N can be made even smaller than that shown in Table 1 if multiple values are allowed instead of making the number the only one. However, if the multiple values allowed as the number 1 are too close together, it becomes difficult to distinguish between them, and reading errors are likely to occur. It has been found that if a plurality of allowable values are separated from each other by 3 or more, it is possible to accurately identify how many l's are included in the input channel code. Therefore, we set the number of 1s in two ways that are 3 or more apart from each other,
Table 2 shows an example when each is expressed by i and j.

Table 2 where M, N, t, j are N C10N CJ 22M...
(2) is satisfied, and when compared with Table 1, it can be seen that N for each M is reduced by 1. Efficiently converting the code into a channel code as above 0, and accurately converting the input channel signal. This means that it can be read.

A code conversion device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a code converting device according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing the block diagram. In FIG. 2, 100 is a converter, l is a conversion means, 2 and 3 are conversion tables, and the converter lOO is inputted (M-)8 in accordance with the rules of the conversion means l or conversion tables 2 and 3. Bit information word a1alasaaasa
6a? a @ (N-) 10-bit channel code b
lbtb! b, bibAbtbsb9b,.

Convert to A group discriminator 4 determines whether an 8-bit information word is to be converted by the conversion means 1 or conversion tables 2 and 3, depending on its contents. The converting means 1 has a structure as shown in FIG. In other words, 10 is a family discriminator, which converts each 8-bit information word into a 4-bit (0 to 15) family identifier i.
and j]. Furthermore, 11.12 is a conversion table,
5-bit code d Idzdxda for i and j
ds and "d&dtdsdqd+." are output, respectively.

The former corresponds to the upper five bits of the channel code, and the latter corresponds to the lower five bits of the channel code. The output codes of conversion tables 11 and 12 for the same values of i and j are complementary to each other. 13 is an inverse logic operator, and when the first focus 1 of the information word is I,
The logic of the above output code is inverted, and finally the channel code is b+bzbxb4bsbbbJeb*b+. get.

The operation of the binary information loading method configured as above will be described below with reference to FIGS. 1 and 2.

First, the operation of the family discriminator 10 will be explained.

FIG. 3 shows the operating algorithm. In the figure, A is an 8-bit information word ala! a3a4asa&a
It represents ffa@ and is written in decimal notation.

In the first progressive, is the first bit a+ 0?
It is determined whether A≦127)1 (A≧128).

In the former case, set the flag F to 0 and proceed to the next process; in the latter case, set the flag F to 1 and perform an inverse logical operation on A (A
-A) Do.

Next, if A-0, i=o, j=o...
(3), otherwise proceed to the next process In the zero-order process, if l≦A≦25, i=i n t ((A-1)15) +1 −・=(
4) j=mod ((A-1)15]+1 otherwise i=in t ((A-26)/10) +
6 −=45)j = m od ((A −26)
/10) Calculate +6 and output. Here, int means +4 operation to find a quotient, and mod means an operation to find a remainder.

Next, we will read out the output code from the conversion table based on these i and j, but before that, let me explain about the "family".
of 10 code) is separated into upper and lower 5 bits, the number of 1s contained in each must be the upper and lower. Furthermore, if we take into account inverse logic symmetry, which will be described later, there are only the above three patterns, and if we list them all, we get Table 3.

5 out of l, 0 codes can all be written along the combinations of Di and /Dj belonging to the same family. For example, with D2 and /D5 of Group 1-4, a code containing five 1's as shown in Table 3 (see below) can be generated. If they are in the same family, 5outof for all combinations.
It becomes IO code. The number of combinations is 126 in total: 0-5 group lX1=1 1-4 group 5x 5=25 2-3 group 10XIO-100. Furthermore, the reverse logic combination is 1011100 for 0100011110.
Since 001 is possible, there are 126x2-252 codes after all. Now, the total number of 10-bit codes containing 5 l's is. C5=252...
- (6) Therefore, according to the method using this family classification, all possible 10-bit codes can be realized under the constraint that five l's are included.

The explanation will be continued by returning to FIGS. 1 and 3. In Figure 1, the family discriminator is nothing but a device that classifies the 8-bit information word A into the above-mentioned family.When A is expressed in decimal notation, A-0
is for the 0-5 group, ISA≦25 is for the 1-4 group, 26≦A≦
125 is assigned to Group 2-3, and i and j are determined by (3) to (5).

i and j correspond to the subscripts D and /D in Table 3, respectively. Furthermore, obtain the 5-bit code corresponding to each t and J from the conversion table 11.12,
A 10-bit code is generated in which both are upper and lower. Conversion table 11 is Di and d+dxd in Table 3.
The conversion table 12 is for electrically realizing the correspondence between /Dj and d&d, dwd, and d+* in Table 3.

For example, for A-10, from (4) 1=inL [(10-1)15)+1-21-2J=
((10-1)15)+1-5, and from Table 3 it becomes D2-01000 /D5-11110, so the obtained 10-bit code is D2/D5-
0100011110.

According to this conversion rule, A 0 (00000000) ~ 1
25 (011111101) 5 out of 10
It can be converted to code. Furthermore, if we use the inverse logical symmetry shown below, A-130 (10000010)
The conversion code for ~255 (111111111) can be easily obtained. That is, A and 255-A
and A-255-A In other words, they have a relationship of opposite logic to each other. This and the 5 I got earlier
The family discriminator IO determines whether the 8-bit information word has positive logic or reverse logic (whether it is larger or smaller than 127) by making it correspond to the inverse logic code of the out of 10 code. The determination result is transmitted to the inverse logic calculation means 13 by flag F. The inverse logic operation means 13 outputs 5out o accordingly.
By keeping or reversing the logic of the f l O code, we finally get the channel code b+bzbsbJsbhb
JJ, b+. generate. For example a +ntasa, asti, aquae-000010
When 10 (10 in decimal notation), F-O d+dzdsdadsd&dqd*d*d+e =01
00011110b+b*bsbabibhbtbsb
*b+. -0100011110 [Logic retention] a, ata, a, asa, ayas-1111010
When it is 1 (245 in decimal notation), F-1 drdzdsdadsdhdqdmdqd+. -010
0011110b+btbsbabstlatlJsb
,b+. -1011100001 [Logic reversal] In this way, just by preparing a conversion table with a total of 32 conversion patterns, 16 for the upper and lower, 252 types of 8-bit binary → 5 out
One major feature of the present invention is that of 10 conversion can be realized.

Next, special codes will be explained. Now, there are 2"-256 information words that can be described with 8 bits. On the other hand, the number of 5 out of 10 codes obtained earlier is 252. Therefore, the conversion means l
However, it is not possible to deal with all 8-bit information words, and a conversion table outside this constraint is required for the remaining four information words.

Conversion table 2 and conversion table 3 provide conversion rules for these four. Conversion table 2 is 01111110.0111111 of the 8-bit information word.
11,10000001゜10000011 2 out
Convert to channel code of 10. If the previously obtained 5 out of 10 code is referred to as the first group of channel codes, this conversion table 2 generates the second group of channel codes. Furthermore, the conversion table 3 converts the same information word 8 out of 10 into a 10-bit channel code, that is, a third group of channel codes.

Here, for convenience, the information word corresponding to the first group of channel codes will be referred to as a normal information word, and the above four information words corresponding to the second and third group channel codes will be referred to as specific information words.

The functions of the second group and the third group of channel codes will be explained using an example. Now, as shown in FIG. 4, it is assumed that 8-bit information words are input sequentially from the top. Since the first three words are normal information words, the first three words according to conversion means 1
Each channel code belonging to the group is converted. The next input information word is a specific information word. Two channel codes, a channel code belonging to the second group and a channel code belonging to the third group, correspond to a specific information word, and the second group or the third group is selected alternately. Convert to the corresponding channel code. Here, we first convert 0 to the second group of channel codes.
Since the next information word is a normal information word, it is converted into the first group of channel codes. Then, a specific information word is input again, but since the previous specific ffffllll word was converted to the channel code of the second group, it is now converted to the corresponding channel code of the third group. In this way, a particular information word can be assigned to the second group of channel codes and the third group of channel codes.
The converter 100 operates to alternately convert between the groups of channel codes. In this way, the number of l's included in the second group of channel codes is 2. The number of I's included in the third group of channel codes is 8, so the average is 5.
Since this is equal to the number of 1's included in the first group of channel codes, the number of 1's appearing in the channel code is constant on average, resulting in a so-called DC-free channel code.

Note that in this embodiment, the family identifier 1. ft respectively for j
I have prepared rotiple 11.12, but the conversion table 11
In this case, for j, by performing an inverse logical operation on the output of the conversion table 11, a result equivalent to referring to the conversion table 12 can be obtained. This allows 16 combinations of conversion tables.

Further, in this embodiment, the 10-bit channel code is divided into bit groups of upper and lower 5 bits, but this is not necessarily limited to such division. For example, if you write a 10-bit channel code as odd number digits (b+b
zbsbJq), even digits (bzbJib, lb+.)
I don't mind dividing it by.

Next, a decoding device that decodes the channel code converted by the code conversion device in this embodiment will be explained.

FIG. 5 is a schematic configuration diagram of a decoding device in an embodiment of the present invention. FIG. 6 is a diagram showing the configuration of its main parts. In FIG. 5, reference numeral 14 denotes a binarization means, which reads the input channel signal and generates a chunkful code expressed in binary. A group discriminator 15 determines whether the channel code belongs to the first group, the second group, or the third group. 20
is a reverse loader and sets the channel code of lO bits to 8
Convert to bit information word. 21 is the first group (5 out
This is an inverse conversion means for inversely converting the channel code of 10), and its details are shown in FIG. 22.23
are conversion tables for converting the channel codes of the second group (2 out of 10 ) and the channel codes of the third group (8 out of 10 ), respectively.

In FIG. 6, 25 is a logic discriminating means (5out
It is determined whether the channel code of 10) has been subjected to an inverse logic operation during modulation. 24 is an inverted logic wave: 1:3, which inverts the logic of the channel code according to the judgment result of the logic judgment means 25. 26 and 27 are inverse conversion tables that output family identifiers lj corresponding to the upper and lower 5 bits of the channel code, respectively. 2
8 is a decoding calculation means for demodulating the 8-bit information word from i and j. 29 according to the judgment of the logical judgment means 25,
This is an inverse logic arithmetic unit that inverts the logic of an 8-bit information word.

The operation of the decoding device configured as described above will be explained below. It is assumed that the channel code code-converted by the code conversion device in the above embodiment is transmitted and input as a channel signal. This channel signal may be one that has been transmitted through a transmission line, or
It may be reproduced from a recording medium. The signals that have passed through the transmission path in this way are not necessarily binary, and contain various distortions and noises. Therefore, binarization means 1
4 operates in the following steps.

■ Sample the input channel signal in synchronization with the channel clock for each channel bit, and divide it into channel code units.

■ Rank the sample values in descending order of size.

■ Compare the first and fifth sample values, and if the difference is greater than a predetermined value, use the second group channel code (2out
oflO) and is inversely converted into an information word according to the inverse conversion table 22.

■ Compare the 6th and 10th sample values, and if the difference is greater than a predetermined value, use the third group channel code (8ou
t of 10 ), and the information word is inversely converted into an information word according to the inverse conversion table 23.

■ If it is neither group 2 nor group 3, the first
It is determined that the channel code is the group channel code (5outoflO), and is inversely converted into an information word using the inverse conversion means 21 as described below.

The operation of the inverse conversion means 21 will be described in more detail with reference to FIG. First, the logic determining means 25 determines (5 out ofl O) the 10-bit channel code btbtbsb4bsb&bJJ,b+. is a result of an inverse logical operation during modulation.

For example, if it is a positive logic code, the number of 1s included in the upper 5 bits is either 0 or 1.2, and if it is a reverse logic code, the number of 1s is either 3 or 4.5. Therefore, its identification is possible. In the case of reverse logic, the logic of the 10-bit channel code is inverted, and as will be described later, the logic of the 8-bit information word of the inverse conversion word is also inverted. The 10-bit code drdzdxd obtained in this way
adsdhdtdmd*dra is divided into upper and lower 5-bit codes, and the corresponding identifier '+J is determined using conversion tables 26 and 27. Conversion table 26
．． Table 27 is based on the rules of Table 3, and performs the reverse operation of conversion tables 11 and 12 shown in the previous embodiment.

Once i and j are determined in this way, the 8-bit code A ("a+
aiajaaaasahataw) can be obtained.

The decoding calculation means 2 is for performing this calculation. The algorithm is shown in FIG.

When i=0, it is in the O-5 family and the 8-bit decoding code C is C=O, and when l≦i≦5, it is in the l-4 group and C=
(i-1)xs+j, and when 5≦i≦15, it is a group 2-3 and C=(i 1)xlO+j+26.

When the logic determining means 25 determines that the 10-bit channel code is of reverse logic, ^=C(a+a
tasaaasail+am-CtCtCseaesC
aCyCs), otherwise ^5c(a+ata3a4a5aia7as−C+Cx
esCaCsCbCtC*) is calculated. This is the first
The decoding process for the 8-bit information word corresponding to the channel code is all completed. As an example below, the previously converted lO
Let us consider the case of decoding a bit channel code.

b+bzbsbabsbJql)sl), b+. -01
When 00011110 [positive logic] dldzd3dadsdidtdsdqd+. =01
00011110i=2: j=5 N-4 group] c= (2-1) X5+5-10 (00001010
) a, azasaaasaiatas””000010
10b+bztlsbabsbib? b*bqbte
When =101'1lOO001 [reverse logic] d, dtd, d4d, dhd? d, d, dl @ -01
00011110i=2 2 j-5 (1-481 C-(2-1) X5+5-10 (00001010)
a+azazaaasa&ayaaa-11110101
Thus, it can be seen that the 10-bit channel code has been completely decoded.

In the manner described above, it is possible to accurately inversely transform a channel signal into an information word.

In the above-mentioned embodiment, two types of channel codes are associated with a specific information word, and a DC-free code is created in which the DC component does not fluctuate. However, since the decoding device according to the present invention is not affected by fluctuations in the DC component, It does not necessarily have to be DC-free like this, and for example, a configuration that does not use the third group of channel codes may be used.

In addition, the configuration of the conversion table can be modified in various ways, and is not limited to this configuration. It does not necessarily have to be something like a ROM table, and it can be
, or a logic circuit composed of an OR circuit.

Effects of the Invention As described above, the present invention converts an M-bit information word into a partial group of bits in an N-bit channel code where N>M, and the N-bit channel code has an equal number of bits. 1, it is possible to determine whether each channel bit is 1 or 0 without being affected by low-frequency noise such as DC drift, making it possible to read the channel code accurately and to compare It is possible to realize a code conversion device that can be configured with a relatively small-scale circuit. In addition, the number of 1's included in the channel code is determined from the relative relationship of the sampled values obtained by sampling the input channel signal at the position of each channel bit, and the number of 1's included in the channel code is determined in descending order of luminosity from among these sampled values. A binarization means for generating a channel code by determining that the number of bits is l, and an inverse conversion means for inversely converting the channel code generated by the binarization means to obtain an information word. By doing so, it is possible to obtain a decoding device that effectively inversely converts a channel signal transmitted with a channel code converted by the code converting device into an information word.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of a code conversion device according to an embodiment of the present invention, FIG. 2 is a block diagram of a code conversion device according to an embodiment of the present invention, and FIG. 3 is a block diagram of a code conversion device according to an embodiment of the present invention. FIG. 4 is an explanatory diagram of an example of the operation of the code converting device in an embodiment of the present invention, FIG. 5 is a block diagram of the decoding device in an embodiment of the present invention, and FIG. Main part configuration diagram of a decoding device in an embodiment of the invention, No. 7
Fig. 1 ■ Conversion means, 2.3 Conversion table, 4 Group discriminator, 10 Group discriminator, 11.12 ...Conversion table, 13...
...inverse logic operator, 14...binarization means,
20...Inverse converter, 21.Old...Inverse conversion means,
22.23, 26.27 Old... Inverse conversion table, 28
...Decryption calculation means. Name of agent: Patent attorney Shigetaka Awano 1 person Figure: r=-1---==--=----+00000
LL1 0LOOOJOIlh-11 abusel details L-
---------

Claims (9)

[Claims] (1) A code conversion device that converts an information word consisting of M bits of information bits into a channel code consisting of N bits of channel bits larger than M, the number of 1 among the M bits constituting the channel code. 1. A code conversion device comprising conversion means for converting the information bits into a partial group of bits constituting the channel code so that the information bits are constant. (2) The number of bits N of the channel code is an even number,
a first bit group of N/2 bits and a second bit group of N/2 bits, and further converts information bits into the first bit group and the second bit group, respectively. The code conversion device according to claim 1, further comprising means. (3) The code conversion device according to claim (2), wherein the number of 1's included in the first bit group is the same as the number of 0's included in the second bit group. (4) A channel code is characterized in that it is classified into multiple families in which the number of 1s or 0s contained in a bit group is the same, and family discrimination is performed to distribute information words to each family according to their values. The code conversion device according to claim 1, further comprising means. (5) The number of bits N of the channel code is an even number,
Each channel code is characterized by a first bit group of N/2 bits and a second bit group of N/2 bits, and furthermore, the number of 1's included in the first bit group of channel codes belonging to the same family is 5. The code conversion device according to claim 4, wherein the number is the same as the number of 0s included in the second bit group. (6) The code conversion device according to claim (2), wherein M is 8 and N is 10. (7) A code conversion device for converting an information word consisting of M-bit information bits into a channel code consisting of an even number of N-bit channel bits larger than M, wherein the channel code is an N/2-bit first It is characterized by comprising a bit group and a second bit group of N/2 bits, and further comprising conversion means for converting the information bits into the first bit group and the second bit group, respectively. Code converter. (8) A decoding device for decoding a channel code generated by the code converting device according to claim (1), wherein an M-bit information word smaller than N is selected from a part of bit groups constituting an N-bit channel code. What is claimed is: 1. A decoding device characterized by comprising an inverse transformation means for inversely transforming . (9) A decoding device for decoding the channel code generated by the code conversion device according to claim (2), wherein the N-bit channel code is converted into an N/2-bit first
into a bit group and a second bit group, and uniquely generate a first intermediate code and a second intermediate code for each bit group from each bit group. A decoding device further comprising decoding means for decoding an M-bit information word from the first and second intermediate codes.