JPH0253229U - - Google Patents
Info
- Publication number
- JPH0253229U JPH0253229U JP13029588U JP13029588U JPH0253229U JP H0253229 U JPH0253229 U JP H0253229U JP 13029588 U JP13029588 U JP 13029588U JP 13029588 U JP13029588 U JP 13029588U JP H0253229 U JPH0253229 U JP H0253229U
- Authority
- JP
- Japan
- Prior art keywords
- zero
- sequence
- circuit
- signal
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009499 grossing Methods 0.000 claims description 2
- 230000003111 delayed effect Effects 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Emergency Protection Circuit Devices (AREA)
Description
第１図はこの考案の実施例のブロツク図、第２
図、第３図は実施例の動作を説明するための波形
図、第４図は位相検出回路の回路例を示す図、第
５図、第６図は従来の欠点を説明するための図で
ある。
２―遅延回路、３―第１の減算回路、４，５―
平滑回路、６―第２の減算回路。
Figure 1 is a block diagram of an embodiment of this invention;
3 are waveform diagrams for explaining the operation of the embodiment, FIG. 4 is a diagram showing a circuit example of a phase detection circuit, and FIGS. 5 and 6 are diagrams for explaining the drawbacks of the conventional method. be. 2-delay circuit, 3-first subtraction circuit, 4,5-
Smoothing circuit, 6-Second subtraction circuit.
Claims (1)
を一定周期遅延させる第１の遅延回路と、その遅
延出力と前記零相電圧または零相電流との差を検
出し、位相情報を有する信号として出力する第１
の減算回路と、 前記零相電圧または零相電流と前記遅延出力と
を各々平滑する平滑回路と、それらの平滑出力の
差を振幅情報を有する信号として出力する第２の
減算回路とを備えてなる残留電圧、電流除去回路
。[Claims for Utility Model Registration] A first delay circuit that delays a zero-sequence voltage or zero-sequence current detected by a sensor by a certain period, and detects a difference between the delayed output and the zero-sequence voltage or zero-sequence current; The first signal is output as a signal having phase information.
a subtraction circuit, a smoothing circuit that smoothes each of the zero-sequence voltage or zero-sequence current and the delayed output, and a second subtraction circuit that outputs the difference between the smoothed outputs as a signal having amplitude information. Residual voltage and current removal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13029588U JPH0613583Y2 (en) | 1988-10-04 | 1988-10-04 | Residual voltage / current removal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13029588U JPH0613583Y2 (en) | 1988-10-04 | 1988-10-04 | Residual voltage / current removal circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0253229U true JPH0253229U (en) | 1990-04-17 |
| JPH0613583Y2 JPH0613583Y2 (en) | 1994-04-06 |
Family
ID=31385335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13029588U Expired - Lifetime JPH0613583Y2 (en) | 1988-10-04 | 1988-10-04 | Residual voltage / current removal circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0613583Y2 (en) |
-
1988
- 1988-10-04 JP JP13029588U patent/JPH0613583Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0613583Y2 (en) | 1994-04-06 |
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