JPH025298A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JPH025298A
JPH025298A JP88154178A JP15417888A JPH025298A JP H025298 A JPH025298 A JP H025298A JP 88154178 A JP88154178 A JP 88154178A JP 15417888 A JP15417888 A JP 15417888A JP H025298 A JPH025298 A JP H025298A
Authority
JP
Japan
Prior art keywords
output
drom
capacity
memory
influence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP88154178A
Other languages
Japanese (ja)
Inventor
Koichiro Shimizu
清水　晃一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP88154178A priority Critical patent/JPH025298A/en
Publication of JPH025298A publication Critical patent/JPH025298A/en
Pending legal-status Critical Current

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  • Read Only Memory (AREA)

Abstract

PURPOSE:To suppress the influence of the off-leak by adding the capacity to the output of a DROM (dynamic read-only memory). CONSTITUTION:The proper capacity 8 is added to a parasitic capacity 6 in consideration of the working speed, the working temperature range and the working voltage at an output part 3 of a DROM. Thus the stored electric charge increases and therefore the memory contents can be normally latched by a flip-flop 7 of the next stage even though a certain extent of electric charge is omitted due to the off-like of transistors TR 11, TR 1n and TR 2 (l-m+2). As a result, the influence of the off-leak of those TRs can be suppressed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ダイナミック・リード・オンリー・メモリを
有する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having a dynamic read-only memory.

〔発明の概要〕[Summary of the invention]

本発明は、ダイナミック・リード・オンリーメモリ（以
下ＤＲＯＭと称す）において、メモリ部のＮチャネル・
トランジスタ側に供給する電位を次段のフリップ・フロ
ップ（以下Ｆ−Ｆと称す）の入力に容量を付加すること
により、Ｎチャネル・トランジスタのオフ、リークの影
響を押さえる様にしたものである。The present invention provides an N-channel memory section in a dynamic read only memory (hereinafter referred to as DROM).
By adding a capacitor to the input of the next-stage flip-flop (hereinafter referred to as FF) to supply the potential to the transistor side, the influence of off-state leakage of the N-channel transistor is suppressed.

〔忙来の技術〕[Traditional technology]

従来、ＤＲＯＭとして、一般に第２図に示す様に、読み
出し時以外の時プリチャージ人力２によって導通する、
Ｐチャネル型ＭＩＳＦＥＴＩＩ、１２、＝−１ｎと、該
ＭＩＳＦＥＴＩＩ、１２、・・・１ｎと出力３を通して
つながり、読み出し時に導通か非導通かを制御する信号
がアドレス人力１に入る選択的に配置されたＮチャネル
型Ｍ　Ｉ　Ｓ　ＦＥＴ２１．２２、・・・２ｊ″′Ｃ′
構成され、読み出し時に縦積みとなっている該Ｎチャネ
ル型ＭＩＳＦＥＴの１列の中のいづれかが非導通で、そ
れがすべての列にわたっていれば出力３はダイナミック
状態となり寄生容量６により保持していたＶ。０を出力
とし、該Ｎチャネル型ＭＩ　５ＦＥＴ２１．２２、・・
・２ｊの１列のすべてのトランジスタが導通状態であれ
ば寄生容量により保持していたＶＤＤがＶ。Conventionally, as a DROM, as shown in FIG.
The P-channel type MISFET II, 12, = -1n is connected to the MISFET II, 12, . N-channel type MI S FET21.22,...2j'''C'
If any one of the rows of N-channel MISFETs stacked vertically during readout is non-conducting, and it extends across all rows, the output 3 becomes a dynamic state and is maintained by the parasitic capacitance 6. V. 0 as the output, and the N-channel type MI 5FET21.22,...
・If all transistors in one column of 2j are conductive, VDD held by parasitic capacitance becomes V.

側にぬけて、出力３がＶＢＢとなる。Output 3 becomes VBB.

これにより貫通電流を押さえ低消費電流を実現すること
が知られていた。It has been known that this reduces through current and achieves low current consumption.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来のＤＲＯＭの構成では、低電圧・低速動作
・高温動作では出力３の電位が非導通状態の該Ｎチャネ
ル型ＭＩＳＦＥＴのオフリークで寄生容量により保持し
ていたＶＤＤが次段のＦ−Ｆにラッチする以前にぬけて
しまう欠点があった。However, in the conventional DROM configuration, in low voltage, low speed operation, and high temperature operation, the potential of output 3 is off-leak from the non-conducting N-channel MISFET, and the VDD held by the parasitic capacitance is The problem was that it would come off before it latched.

そこで本発明は、従来のこの様な欠点を解決するため、
読み出し時の出力がダイナミック状態になっている時に
、ある程度のリークがあっても、正常に次段のＦ−Ｆに
出力３の状態をラッチすることを目的としている。Therefore, in order to solve these conventional drawbacks, the present invention has the following features:
The purpose is to normally latch the state of output 3 to the next stage FF even if there is a certain amount of leakage when the output is in a dynamic state during reading.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決するため出力３部に適当な容量を１子方
口した。In order to solve the above problem, one suitable capacity was added to each of the three output parts.

〔作用〕[Effect]

上記の様に出力３部に動作スピード、動作温度範囲、動
作電圧を考慮して適当な容量を寄生容量に付加する事に
より、たくわえられる電荷が増加し、トランジスタのオ
フリークによりある程度の電荷が抜けても正常にメモリ
の内容を次段のＦ・Ｆにラッチすることができる。As mentioned above, by adding an appropriate capacitance to the parasitic capacitance in the output 3 section considering the operating speed, operating temperature range, and operating voltage, the amount of charge that can be stored increases, and a certain amount of charge is released due to off-leakage of the transistor. The contents of the memory can also be normally latched into the next F/F.

〔実゛施例〕[Practical example]

以下に、本発明の実施例を図面に基づいて、説明する。 Embodiments of the present invention will be described below based on the drawings.

第１図において、容量８を寄生容量６に付加することに
より出力３の容量が増加し、オフリークがあり電荷があ
る程度ぬけても次段のＦ−Ｆ７には、トランジスタのオ
フリークの影響を排除することができる。In Figure 1, by adding capacitor 8 to parasitic capacitance 6, the capacitance of output 3 increases, and even if there is off-leakage and some charge is lost, the effect of off-leakage of the transistor is eliminated in the next stage F-F7. be able to.

なお２はプリチャージ入力であり、４は出力をラッチす
るためのラッチクロックである。Note that 2 is a precharge input, and 4 is a latch clock for latching the output.

また５はメモリ部であり、１１．１ｎ、２（」−ｍ＋２
）はＭＩＳＦＥＴである。5 is a memory section, 11.1n, 2(''-m+2
) is a MISFET.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、ＤＲＯＭの出力に容量
を付加することにより、トランジスタのオフリークの影
響を押さえるという効果がある。As explained above, the present invention has the effect of suppressing the influence of off-leakage of transistors by adding a capacitor to the output of the DROM.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明にかかるＤＲＯＭの回路図、第２図は
、従来のＤＲＯＭの回路図である。 アドレス入力 プリチャージ入力 出力 入力 メモリ部 寄生容量 プリップフロップ 容量 以上 出願人　セイコー電子工業株式会社FIG. 1 is a circuit diagram of a DROM according to the present invention, and FIG. 2 is a circuit diagram of a conventional DROM. Address Input Precharge Input Output Input Memory Section Parasitic Capacitance Flip Flop Capacity Applicant: Seiko Electronics Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] ダイナミック・リード・オンリー・メモリにおいてセン
スアンプ部のデータ・リード・オンリー・メモリ・トラ
ジスタとプリチャージトランジスタの接合部に容量を付
加する事を特徴とする半導体装置。A semiconductor device characterized in that a capacitor is added to a junction between a data read only memory transistor and a precharge transistor in a sense amplifier section in a dynamic read only memory.
JP88154178A 1988-06-22 1988-06-22 Semiconductor integrated circuit Pending JPH025298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP88154178A JPH025298A (en) 1988-06-22 1988-06-22 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP88154178A JPH025298A (en) 1988-06-22 1988-06-22 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH025298A true JPH025298A (en) 1990-01-10

Family

ID=15578539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP88154178A Pending JPH025298A (en) 1988-06-22 1988-06-22 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH025298A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9502080B2 (en) 2014-03-13 2016-11-22 Kabushiki Kaisha Toshiba Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9502080B2 (en) 2014-03-13 2016-11-22 Kabushiki Kaisha Toshiba Semiconductor memory device

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