JPS63146292A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize the low power consumption of a semiconductor memory by adding a BICMOS differential amplifier to a bit line sense amplifier part and providing a C<2>MOS inverter between a pair of bit wires and the differential amplifier. CONSTITUTION:A bit line sense amplifier consists of a CMOS flip-flop 1 and a BICMOS differential amplifier 2. The flip-flop 1 contains p channel MOS transistor TRQP1-QP3 and n channel MOS TRQN1-QN3 and the nodes of these TR are connected directly to a pair of bit lines BL and the inverse of BL. The amplifier 2 includes bipolar TRT11-T14, p channel MOS TRQP4 and QP5, and (n) channel MOS TRQN8. A clocked CMOS (C<2>MOS) inverter is provided between the pair of bit lines and the amplifier 2 to cut DC. Thus the power consumption of a semiconductor memory can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a dynamic semiconductor memory device that achieves high integration and high speed.

(Prior Art) In MO8 type semiconductor memory devices, elements are becoming increasingly finer and highly integrated. Currently, 4-bit or 16-bit static RAM (sRAM) is often used in fields where particularly high speed is required, such as cache memory in large computers.

However, when the gate length of a MOS transistor is miniaturized to about 0.5 μm, the external power supply must be lowered to ensure the reliability of the device, and it is no longer possible to increase speed through miniaturization as in the past. Become. Therefore, in sRAM,
MOS) - Attempts are being made to increase speed by introducing bipolar transistors, which have a larger current drive capability than transistors. For example, in a bit line sense amplifier,
A differential amplifier circuit using a bipolar transistor as a driver in combination with a CMOS element is used. CMO like this
The circuit combining S element and bipolar transistor is 8
It is called the 10M08 circuit.

Dynamic R is easier to achieve high integration than SRAM.
The same idea applies to AM (dRAM) as well.
It has been proposed to increase the speed by using a 0M08 circuit. Unlike sRAM, dRAM requires rewriting. Therefore, it is necessary to provide, for example, a CMOS type flip-flop for rewriting, in addition to a differential amplifier using a bipolar transistor as a sense amplifier. Furthermore, since the dRAM cell is essentially a destructive read type, the bit line cannot be directly connected to a differential amplifier using bipolar transistors. It has already been proposed to provide a current mirror circuit using MOS transistors as a means for cutting direct current between a bit line and a differential amplifier using bipolar transistors.

However, in such a bit line sense amplifier configuration, there is a DC current especially when the current mirror circuit operates, and the x4. When using a configuration such as x8, current consumption increases.

(Problems to be Solved by the Invention) As described above, the introduction of the BICMO8 circuit into dRAM has the problem of increased current consumption.

An object of the present invention is to provide a dRAM that solves these problems.

[Structure of the Invention] (Means for Solving Problems) A dRAM according to the present invention has a CMOS flip-flop as a bit line sense amplifier, and a BICMO8 differential amplifier using a bipolar transistor and a MOS transistor. The flip-flop is connected directly to the bit line pair and B I CMO8! ! The dynamic amplifier is characterized in that a bit line pair is connected to the dynamic amplifier via a clocked CMO8 (02MOS) inverter.

(Function) With such a configuration, B I with large current drive ability
By introducing the CMO8 differential amplifier, a highly integrated dRAM capable of high-speed operation can be realized. Furthermore, in the present invention, since a 02 MOS inverter is provided between the bit line pair and the B I CMO3 differential amplifier to cut off DC, power consumption can be reduced.

(Example) The present invention will be explained in detail below.

FIG. 1 is an equivalent circuit showing the main structure of a dRAM according to an embodiment. In the figure, one memory cell M is composed of - MOS transistors and one capacitor, respectively.
C, one dummy cell DC1, and a bit line sense amplifier section for reading the information thereof. The bit line sense amplifier is composed of a CMOS flip-flop 1 and a BICMO8 differential amplifier 2. CMOS flip-flop 1 includes p-channel MOS transistors Qpt to QP3.
and n-channel MO8 transistors QNI-QN3, whose nodes are directly connected to the bit line pair BL, BL.

B I CMO8 differential amplifier 2 includes bipolar transistors Trt to T14, D channel MOS transistor Q
p 41 Qp 5 and an n-channel MOS transistor QN8. Bit line pair BL, 02 MOS between BL and B I CMO8 differential amplifier 2
Inverters 3t and 32 are provided. One 02
MOS inverter 31 includes p-channel MOS transistor QP6.0P7 and n-channel MOS transistor Q.
The other O2MOS inverter 32 is composed of p-channel MOS transistors Qpa and Qp.
! I and n-channel MOS transistors QN s , Q
It is composed of N7.

FIG. 2 is an operational waveform timing diagram of the main nodes of this dRAM. First, in the active cycle, the word line WL and the dummy word line DWL are selected by the row address signal, and the intermediate potential (1/2) of the drain power supply voltage VDO is selected.
The bit line pair BL, BL that was precharged to Vcc
The data stored in memory cell MC and dummy cell DC is then transferred. Next, when the column selection lines C3LA, C3LA, and C3LB are selected by the column address signal, the C2CMOS inverters 3t and 32 operate, and the B I
CMO8 differential amplifier 2 is activated.

As a result, the information transferred to the bit line pair BL, BL is
I Amplified by CMO8 differential amplifier 2 and connected to input/output line I1
0. Transferred to I10.

Rewriting of information is performed by sequentially inputting clocks φP and φ and activating the CMOS flip-flop 1. If the read content of the memory cell MC is logic “1”, the bit line BL is connected to the drain power supply voltage V
In DD, BL becomes the source power supply voltage Vss, and 1 is loaded into the capacitor of the memory cell. This memory cell rewriting is performed so that all CMOS flip-flops are activated for the selected word line after a certain predetermined time has elapsed after the word line is selected regardless of the column selection signal.

According to this embodiment, it is possible to obtain a dRAM that can operate at a high speed comparable to that of an sRAM while taking advantage of the high integration performance of the dRAM.

FIG. 3 shows a comparison of access times in a 16 Mbit dRAM for various configurations. CMOS
Access time t*Ac-96nSeC in the configuration of
BICMO is installed in the parts other than the bit line sense amplifier.
If 8 configuration is introduced, this will be 57 n sea, but this is only 70% of the case with only CMOS. On the other hand, the bit line sense amplifier along with other parts
By converting to CMO8, the acquisition time can be changed to CMOS.
The time can be reduced to about 1/2 compared to the case where only

Furthermore, in a conventional general dRAM sense amplifier, its sensitivity is determined by the ratio of the bit line capacitance CB to the cell capacitance ff1cs, and it is not possible to reduce Co to 40 fF or less due to the relationship with the operating margin. In the present invention, since the bit line sense amplifier is of a current amplification type, it can operate satisfactorily even if the cell capacitance is 20 fF or less. Currently, high integration of 4M or more (JRAM
In order to secure a capacitance of 40 fF or more, the memory cell manufacturing process becomes complicated, which leads to a decrease in yield and an increase in cost. In this respect, in the present invention, since the cell capacity can be small, there is no need to complicate the memory cell manufacturing process, and the cost per bit can be reduced.

In this embodiment, a row address signal is input to select a word line, and then a column address signal is input to select a B I
The case where the CMO8 differential amplifier is activated has been described.

Conversely, the column address signal may be input before the row address signal and the BICMO8 differential amplifier may be activated before the word line is selected. If you do this,
As soon as a word line and a dummy word line are selected, the information read onto the bit line is transferred as is to the input/output line, allowing higher-speed reading.

In addition, FIG. 4 shows the input/output line as the readout input/output line 110R.
, l10R and write input/output line I/○W.

This is the dRAM configuration when separated into 1/Ow,
The present invention is also effective in this case.

[Effects of the Invention] As described above, according to the present invention, a dRAM with increased speed can be realized by introducing a B I CMO8 differential amplifier into the bit line sense amplifier section. In particular, in the present invention, when introducing the BICMO8 differential amplifier, 02M between the bit line pair and the BICMO8 differential amplifier is introduced.
By interposing the OS inverter, lower power consumption can be achieved.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing the main structure of a dRAM according to an embodiment of the present invention, FIG. 2 is an operation timing diagram thereof, and FIG. 3 is a comparison of the access time of the dRAM of this embodiment with that of a conventional example. FIG. 4 is an equivalent circuit diagram showing the main part configuration of a dRAM according to another embodiment. 1...CMOS flip-flop, 2...B I
CMO8 differential amplifier, 31.32...C'' MOS inverter, MC...memory cell, DC...dummy cell, BL, BL...bit line pair, WL...word line, DWL... Dummy word line. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Time Figure 2

Claims (4)

[Claims] (1) In a semiconductor memory device in which dRAM cells are integrated on a semiconductor substrate, a CMOS flip-flop and a differential amplifier combining bipolar transistors and MOS transistors are used as bit line sense amplifiers that read information from dRAM cells. A semiconductor memory device comprising: a bit line pair directly connected to the CMOS type flip-flop, and a bit line pair connected to the differential amplifier via a clocked CMOS inverter. (2) The semiconductor memory device according to claim 1, wherein said differential amplifier is controlled by a column selection signal and only one corresponding to a selected column is activated. (3) The semiconductor memory device according to claim 1, wherein the differential amplifier is activated by a column selection signal before a word line is selected by a row selection signal during active operation. (4) The dRAM cell is constituted by one MOS transistor and one capacitor.
The semiconductor storage device described in 1.