JPH025282A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the signal transmitting speed and to reduce the wiring area by using a bit line in a memory area also as a signal transmission line. CONSTITUTION:A word line inactivating means (d) is prepared to inactivate a word line in a memory area (a) as necessary for transmission of the signal received from a signal output circuit (b) to a logic circuit (c). In this invalidating period, a bit line of the area (a) serves as a transmission line to send the signal received from the circuit (b) to the circuit (c). Thus it is possible to omit the transmission line detouring the area (a). As a result, the signal transmitting speed is increased together with reduction of the wiring area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device in which a memory area is built in, and in which signals are transmitted between the memory areas. The present invention relates to a semiconductor integrated circuit device in which bif +-bi in a memory area can be used as a transmission path when performing the above.

In recent years, with the improvement of semiconductor technology, semiconductor integrated circuit devices have come to be equipped with multiple functions. As a result, devices that meet a variety of user requirements at a high level have been realized.

[Conventional technology]

The above-mentioned tendency is noticeable in microcomputers and their peripheral devices, and specifically, for example, in devices that incorporate cache memory, or so-called devices equipped with judgment memory for checking the cache hit for this cache memory. Examples include address conversion chips.

Mixed memory on the same chip has a fast memory access speed and meets the recent demands for higher speeds, and of course requires fewer chips, making it easier for PCs.
The implementation rate on B is improved.

Generally, the memory on the chip is often located relatively near the center.

[Problem to be solved by the invention]

However, in such conventional semiconductor integrated circuit devices, various logic circuits are often arranged around the memory at the center of the chip. When transmitting a signal to the second logic circuit located on the other side of the memory, the signal transmission path had to be routed around the memory. Therefore, there is a problem in that the transmission path becomes long, resulting in a reduction in signal transmission speed. Furthermore, when there are multiple transmission lines, there is a problem in that the wiring area on the chip increases.

Therefore, the present invention aims to shorten the transmission speed and reduce the wiring area by making it possible to use the bit line in the memory area as a mere signal transmission path, eliminating the need for a transmission path that bypasses the memory. It is said that

[Means to solve the problem]

FIG. 1 shows a principle block diagram of a semiconductor integrated circuit device according to the present invention.

In FIG. 1, a signal output circuit for outputting a predetermined signal is disposed on one side of the memory area a in the extending direction of the bit line in the memory area a, and at least the signal output circuit is placed on the other side. Logic circuit C that requires appropriate signals from
A semiconductor integrated circuit device in which a word line deactivation means d for deactivating the word line of the memory area a as necessary, and a word line deactivating means d for deactivating the word line of the memory area a, and a bit line of the memory area a are arranged. The first connecting means e connects to one end of the bit line, and the second connecting means f connects the logic circuit C to the other end of the bit line of the memory area a.

[Effect]

In the present invention, when transmitting the signal from the signal output circuit to the logic circuit, the word line in the memory area is inactivated, and during this inactivation period, the bit line in the memory area is used to transmit the signal from the signal output circuit to the logic circuit. Functions as a transmission path for transmitting information to the circuit.

Therefore, there is no need for a transmission line that detours around the memory circuit, and the wiring area can be reduced.
Because it is the shortest distance between the signal output circuit and the logic circuit,
Signal transmission speed can be increased.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 2.3 is a diagram showing an embodiment of the semiconductor integrated circuit device according to the present invention, and is an example applied to an address conversion chip used as a peripheral device of a microcomputer.

First, the configuration will be explained. In FIG. 2, 1 is an address conversion chip, and the address conversion chip 1 is a first
It is configured to include a memory section M1, a second memory section M2, and a comparison section CMP arranged between them.

The first memory section M1 has an input/output port 2 (signal output means) to which a logical address LA from a microcomputer (not shown) is input during system startup, etc., and a physical address LA from a microcomputer (not shown) during processing. Input/output port 3 (signal output means) into which PA is input and control signal SCN□
input/output port 4 to which control address CA1 is input;
a control circuit 6 that generates control signals including ill and word line deactivation signals Wl, l, l; a decoder 7 that decodes CAI and outputs a word line selection signal W S E L I; It outputs a signal WoN that activates one word line, and when WI- is input, W. 8, a memory area MEMa in which a large number of word lines and bit lines are arranged in an intersecting manner, and memory cells are connected to each intersection; SEL+ is connected to one end of the bit line in LA or PA.
A read/write circuit (first connection means) 9 that transmits data on the bit line to the input/output port 2 or the human output boat 3, and the other end of the bit line in MEMa. The comparison unit C
A lead circuit (second connection means) 10 added to the MP,
It is equipped with

The second memory unit M2 has an input/output port 1 to which a physical address PAc assigned to a cache memory (not shown) is input.
1 and an input port 12 into which the control signal 5cNvz is input.
And control dress CA! an input boat 13 into which is input;
Select signal 35 according to S CNT□! LO, read/write signal stt/wg and register drive signal 30G
A control circuit 14 generates a control signal including a word line selection signal W S ! by decoding CAz. L! a gate circuit 16 that activates one word line according to WsEL2, a memory cell area MEMb in which a large number of word lines and bit lines are arranged in a crosswise manner, and a memory cell is connected to each intersection; A read/write circuit 17 that is connected to one end of the bit line in MEMb and writes PAC to the memory cell by putting it on the bit line;
A read circuit 18 is connected to the other end of the bit line in the memory cell and reads out data in the memory cell via the bit line.

The comparison unit CMP includes a comparison circuit (logic circuit) 20 that compares data from the read circuit 10 of MEM a and the read circuit 18 of MEMb and outputs a match signal SCMF.
and S□, a register 21 that takes in and holds this S CNP, and an output port 22 that outputs seI4p in the register 21 to the outside (for example, a microcomputer).

FIG. 3 is a diagram specifically showing the read/write circuit 9 of the first memory section M1 and a part of the memory area MEMa.

In FIG. 3, the read/write circuit 9 includes a plurality of circuits 9. 97, and the configuration of each circuit is the same. The circuit 91 will be explained as a representative. 25 is a read gate whose output side is opened on either side by a read control signal Sll; 26 is a write control signal S; 27 is a selector that selects either P or LA by S5ELI.

In addition, in the same figure, there are many bit lines B in MEMa.
Ll ""' B Ln and a number of word lines WL,
-WL7 are arranged and these B L l-B Lls
A memory cell M is connected to the intersection of and WLI-WL,l.

Next, the effect will be explained.

In the instruction prefetch control system, a so-called cache check is performed to determine whether or not necessary data exists in a prefetch cache memory.

For example, in a system including the address conversion chip 1 of this embodiment, first, the physical address PAc assigned to the cache memory is stored in MEMb, and then the physical address PA associated with the logical address is stored in MEMa. , these MEMa and MEMb data are CM
Compare with P to find a match. That is, when the one-defeat signal SCMP is output from CMP, it becomes a cash hit.

On the other hand, even when checking a similar cache hint, for example, when data is not stored in the main memory, such as when the system is started up, the logical address LA generated by the microcomputer and the contents of MEMb can be directly checked. It becomes necessary to compare.

In such a case, the conventional method described above requires a dedicated transmission line for transmitting L, and this transmission line bypasses MEMa and is routed to the comparator circuit 2o, resulting in a reduction in LA transmission time and This also led to an increase in the wiring area.

On the other hand, in this embodiment, W from the gate circuit 8 is used. H
Since the word line of MEMa can be inactivated by inhibiting the output of
It is possible to use CMP to match the data within.

Therefore, there is no need to provide a dedicated transmission line for transmitting the LA (the wiring area can be reduced, and since the LA is transmitted to the comparator circuit 20 over the shortest distance, it is possible to increase the speed). can.

In the above embodiment, the number of signals that can be selected by the read/write circuit 9 is two, LA and PA, but the number is not limited to this and may be two or more.

FIG. 4 is a diagram showing another example of application of the present invention.

In FIG. 4, 31 is a first internal data bus, 32 is a second internal data bus, 33 is a third internal data bus,
34 is a read/write circuit (first connection means), 35 is an internal memory (memory area), 36 is a word decoder (also serves as word line deactivation means), 37 is a read circuit (second connection means), 38 39 is a read/write control circuit, and 40 is a read control circuit.

According to such a configuration, the read/write circuit 34 appropriately selects data from a plurality of signal output circuits (not shown) inputted via the first internal data bus 31 or the second internal data bus 32. The stored data can be stored in the internal memory 35, and the comparison circuit 38 can compare the stored data with the data input via the third internal data bus 33.

Furthermore, by stopping the decoding function of the word decoder 36 and inactivating the word line of the internal memory 35, the bit line within the internal memory 35 can be made to function simply as a transmission path. The data input via the internal data bus 31 or the second internal data bus 32 and the data input via the third internal data bus 33 can be compared.

〔Effect of the invention〕

According to the present invention, the bit line in the memory area can be used as a simple signal transmission path, eliminating the need for a transmission path that detours around the memory, thereby shortening the transmission speed and reducing the wiring area. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2.3 is a diagram showing an embodiment of the present invention, FIG. 2 is an overall configuration diagram thereof, FIG. 3 is a configuration diagram of its main parts, FIG. 4 is a configuration diagram showing another example of application of the present invention. 8...Gate circuit (word line deactivation means),
9...read/write circuit (first connection means),
10...--Lead circuit (second connection means), 20
...Comparison circuit (logic circuit), BL, -B...
...Bit line, MEMa...Memory area. The bookkeeping pro of the present invention...7 Figure 1 Figure 2 Person output boat 3) X (+/4 area one branch precedent complete stop "Configuration ° mouth 2nd t!!

Claims (1)

[Claims] A signal output circuit (b) for outputting a predetermined signal is arranged on one side in the extending direction of the bit line in the memory area (a), with the memory area (a) in between, and on the other side. A semiconductor integrated circuit device in which a logic circuit (c) that appropriately requires at least a signal from the signal output circuit (b) is arranged, the word line of the memory area (a) being Activating word line deactivation means (d)
and a first connecting means (e) for connecting the signal output circuit (b) to one end of the bit line in the memory area (a); and a first connecting means (e) for connecting the logic circuit (c) to one end of the bit line in the memory area (a). A semiconductor integrated circuit device comprising: second connection means (f) connected to the other end.