JPH0251263A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0251263A JPH0251263A JP20104288A JP20104288A JPH0251263A JP H0251263 A JPH0251263 A JP H0251263A JP 20104288 A JP20104288 A JP 20104288A JP 20104288 A JP20104288 A JP 20104288A JP H0251263 A JPH0251263 A JP H0251263A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- conductivity type
- resistor
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 239000012535 impurity Substances 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 2
- 229960001866 silicon dioxide Drugs 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要］
一導電型の半導体層の一部領域に形成された反対導電型
領域をもって構成されるいわゆる拡散抵抗の絶縁耐力を
向上する改良に関し、
通電時の電圧降下が大きい場合にも、絶縁破壊が起こら
ないように改良された拡散抵抗を提供することを目的と
し、
一導電型の半導体層の表層に反対導電型の領域が形成さ
れ、この反対導電型の領域の一部領域に、前記の一導電
型の半導体層と絶縁されて一導電型の領域が形成されて
なり、前記の反対導電型の領域をもって抵抗が構成され
てなる半導体装置において、前記の一導電型の領域は、
前記の抵抗の長手方向と交叉する方向に分割されるよう
に構成される。[Detailed Description of the Invention] [Summary] Regarding an improvement to improve the dielectric strength of a so-called diffused resistor that is composed of a region of an opposite conductivity type formed in a partial region of a semiconductor layer of one conductivity type, the voltage drop when energized is reduced. In order to provide improved diffusion resistance so that dielectric breakdown does not occur even when the diffusion resistance is large, a region of an opposite conductivity type is formed on the surface layer of a semiconductor layer of one conductivity type, and a region of the opposite conductivity type is formed in the surface layer of a semiconductor layer of one conductivity type. In a semiconductor device in which a region of one conductivity type is formed in a partial region insulated from the semiconductor layer of one conductivity type, and a resistor is constituted by the region of the opposite conductivity type, the one conductivity type The area of the type is
The resistor is configured to be divided in a direction intersecting the longitudinal direction of the resistor.
本発明は、一導電型の半導体層の一部領域に形成された
反対導電型領域をもって構成されるいわゆる拡散抵抗の
絶縁耐力を向上する改良に関する。The present invention relates to an improvement in improving the dielectric strength of a so-called diffused resistor that is constituted by a region of an opposite conductivity type formed in a partial region of a semiconductor layer of one conductivity type.
従来技術に係る拡散抵抗について図を参照して説明する
。A diffused resistor according to the prior art will be explained with reference to the drawings.
第５図参照
１は一導電型例えばｎ型の半導体層であり、２は反対導
電型のｐ型不純物を拡散して形成されたｐ０型の領域で
あり、４は絶縁膜であり、５はｐ゛°型のコンタクト領
域であり、６は電極・配線である。ｐ゛型ｅＭＭＵ２を
もって抵抗が構成されている。抵抗値は、Ｐ９型領域２
に導入される不純物濃度と不純物拡散領域とによって調
整されるが、抵抗値の制御性をよくするため、特に、抵
抗値の高い領域の抵抗値の制御性をよくするため、次の
方法が使用されている。Referring to FIG. 5, 1 is a semiconductor layer of one conductivity type, for example, an n-type, 2 is a p0 type region formed by diffusing p-type impurities of the opposite conductivity type, 4 is an insulating film, and 5 is a semiconductor layer of one conductivity type, for example, an n-type. It is a p゛° type contact region, and 6 is an electrode/wiring. A resistor is constituted by the p' type eMMU2. The resistance value is P9 type region 2
It is adjusted by the impurity concentration introduced in the region and the impurity diffusion region, but the following method is used to improve the controllability of the resistance value, especially in the region with high resistance value. has been done.
第６図参照
その方法は、ｐ“型の抵抗ＳＮ［２の一部領域にｎ型不
純物を拡散してｎ型の半導体層！と絶縁されたｎ゛型の
領域３を形成し、このｎ゛型の領域３の不純物拡散領域
を調整することによって、抵抗を構成するｐ゛型の領域
２の通電面積を調整して抵抗値を制御する方法である。Refer to FIG. 6. The method involves diffusing n-type impurities into a partial region of the p"-type resistor SN[2 to form an n-type region 3 insulated from the n-type semiconductor layer! This is a method of controlling the resistance value by adjusting the current-carrying area of the p'-type region 2 constituting the resistor by adjusting the impurity diffusion region of the p-type region 3.
〔発明が解決しようとする課題ゴ
第６図再参照
ところで、図に示すように拡散抵抗の電極・配線６の一
方を正の電源に接続し、他方を負の電源に接続して電流
を流すと、抵抗を構成するｐ０型の領域２内で電圧降下
が生ずる。一方、ｎ゛型のＭ域３には、Ｐ−Ｎ接合を介
して正の電源側の電位が加わる。この結果、図にＡをも
って示す領域のｐ゛型の領域２とｎ゛型の領域３との間
に、ｐ゛型の領域２内に発生した電圧降下に相当する電
位差が発生し、この電位差がＰ−Ｎ接合部のブレークダ
ウン電圧よりも高いと、絶縁破壊が発生する。[Problems to be Solved by the Invention]Refer to Figure 6 By the way, as shown in the figure, one of the electrodes/wirings 6 of the diffused resistor is connected to a positive power source, and the other is connected to a negative power source to flow a current. Then, a voltage drop occurs within the p0 type region 2 that constitutes the resistor. On the other hand, a positive power supply potential is applied to the n-type M region 3 via the PN junction. As a result, a potential difference corresponding to the voltage drop occurring in the p-type region 2 is generated between the p-type region 2 and the n-type region 3 in the region indicated by A in the figure, and this potential difference is higher than the breakdown voltage of the PN junction, dielectric breakdown occurs.
本発明の目的は、この欠点を解消することにあり、通電
時の電圧降下が大きい場合にも、絶縁破壊が起こらない
ように改良された拡散抵抗を提供することにある。An object of the present invention is to eliminate this drawback, and to provide an improved diffused resistance that prevents dielectric breakdown even when the voltage drop during energization is large.
上記の目的は、一導電型の半導体層（１）の表層に反対
導電型の８１１Ｍ１（２）が形成され、この反対導電型
の領域（２）の一部領域に、前記の一導電型の半導体層
（１）と絶縁されて一導電型の領域（３）が形成されて
おり、前記の反対導電型の領域（２）をもって抵抗が構
成されている半導体装置において、前記の一導電型の領
域（３）が、前記の抵抗の長手方向と交叉する方向に分
割されることによって達成される。The above purpose is to form 811M1 (2) of the opposite conductivity type on the surface layer of the semiconductor layer (1) of one conductivity type, and to form the 811M1 (2) of the opposite conductivity type in a part of the region (2) of the opposite conductivity type. In a semiconductor device in which a region (3) of one conductivity type is formed insulated from the semiconductor layer (1), and a resistor is constituted by the region (2) of the opposite conductivity type, the region (3) of one conductivity type is This is achieved by dividing the region (3) in a direction transverse to the longitudinal direction of the resistor.
本発明に係る半導体装置においては、一導電型の領域３
が抵抗の長手方向と交叉する方向に分割されており、分
割された一導電型の領域３の幅をそれぞれａとし、抵抗
を構成する反対導電型の領域２の長手方向の単位長さ当
りの抵抗値をＲｕとすると、抵抗に電流■が流れたとき
に、分割された一導電型の領域３の幅ａに対応する領域
の反対導電型の領域２に発生する電圧降下はａ−Ｒｕ・
■となる０分割された一導電型の領域３と反対導電型の
領域２との間には、この電圧降下ａ−Ｒｕ・Ｉに相当す
る電圧が加わるが、もし、電圧降下ａ−１？ ｕ−Ｉが
一導電型領域３と反対導電型の領域２との間のＰ−Ｎ接
合のブレークダウン電圧ＶＩＩ＋より小さければブレー
クダウンは起こらない。In the semiconductor device according to the present invention, the region 3 of one conductivity type
is divided in the direction crossing the longitudinal direction of the resistor, the width of each divided region 3 of one conductivity type is a, and the width per unit length in the longitudinal direction of the region 2 of the opposite conductivity type constituting the resistor is Assuming that the resistance value is Ru, when a current ■ flows through the resistor, the voltage drop that occurs in the region 2 of the opposite conductivity type to the region corresponding to the width a of the divided region 3 of one conductivity type is a−Ru・
A voltage corresponding to this voltage drop a-Ru·I is applied between the zero-divided region 3 of one conductivity type and the region 2 of the opposite conductivity type, which is 2, but if the voltage drop a-1? If u-I is smaller than the breakdown voltage VII+ of the P-N junction between the region 3 of one conductivity type and the region 2 of the opposite conductivity type, no breakdown will occur.
すなわち
Ｖａｎ＞ａ −Ｒｕ −１
を満足するように、分割される一導電型の領域３の幅ａ
を選定すれば、ブレークダウンは起こらない。In other words, the width a of the region 3 of one conductivity type to be divided is such that Van>a −Ru −1 is satisfied.
If you select , breakdown will not occur.
以下、図面を参照しつ一１本発明の一実施例に係る半導
体装置の製造工程について説明し、本発明の構成をさら
に明らかにする。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the manufacturing process of a semiconductor device according to an embodiment of the present invention will be explained with reference to the drawings to further clarify the structure of the present invention.
第２図参照
例えばｎ型のシリコン基板１の拡散抵抗形成領域、例え
ば長さ約１０Ｏｎ、幅約２０ｎをもって囲まれた領域に
開口を有するレジスト層７を形成し、ボロン等のｐ型不
純物を表面不純物濃度が１×１０′６〜Ｉ ＸＩＯ”ｃ
ｍ−’程度となるようにイオン注入した後アニールをな
し、深さ２〜５ｎ程度のｐ型の領域２を形成する。Refer to FIG. 2. For example, a resist layer 7 having an opening is formed in a diffused resistance forming region of an n-type silicon substrate 1, for example, a region surrounded by a length of about 10 On and a width of about 20 On, and a p-type impurity such as boron is added to the surface. Impurity concentration is 1×10′6~IXIO”c
After ion implantation to a depth of about m-', annealing is performed to form a p-type region 2 with a depth of about 2 to 5 nm.
第３図、第４図参照 第４図は第３図の平面図である。See Figures 3 and 4. FIG. 4 is a plan view of FIG. 3.
レジスト層８を形成し、これをバターニングして、例え
ば抵抗の長手方向に対応する幅ａが約１０ｕであり、こ
れと直交する方向の幅すが約１５ｎである開口９を、開
口相互間の間隙Ｃが約１０βｌとなるように複数個例え
ば３個形成する。この場合、開口９はｎ型のシリコン基
板ｌと接触しないように形成する。ヒ素等のｎ型の不純
物を表面不純物濃度がＩ ＸＩＯ”〜Ｉ ＸＩＯ”ｃ＋
ｓ−’程度となるようにイオン注入した後アニールをな
し、厚さ１〜１．５μ程度のｎ°型の領域３を形成する
。なお、ｎ。A resist layer 8 is formed and patterned to form an opening 9 between the openings, for example, the width a corresponding to the longitudinal direction of the resistor is about 10u, and the width in the direction perpendicular to this is about 15n. A plurality of, for example, three, are formed so that the gap C is about 10βl. In this case, the opening 9 is formed so as not to contact the n-type silicon substrate l. The surface impurity concentration of n-type impurities such as arsenic is IXIO”~IXIO”c+
After ion implantation so as to have a thickness of about s-', annealing is performed to form an n° type region 3 having a thickness of about 1 to 1.5 μm. In addition, n.
型の領域３の不純物濃度をｐ°型の領域２の不純物濃度
より低くすれば、空乏層がｎ゛型の領域３側に形成され
るので、抵抗を構成するｐＩ型の領域２の通電面積をよ
り正確に制御できる。If the impurity concentration of the p-type region 3 is lower than the impurity concentration of the p-type region 2, a depletion layer is formed on the n-type region 3 side, so that the current-carrying area of the pI-type region 2 constituting the resistor is reduced. can be controlled more precisely.
第１ａ図、第１ｂ図参照 第１ｂ図は第１ａ図の平面図である。See Figures 1a and 1b. FIG. 1b is a plan view of FIG. 1a.
ＣＶＤ法等を使用して表面に二酸化シリコン層４を形成
し、バターニングしてコンタクト領域５形成領域に開口
を形成し、ｐ型の不純物ボロン等を不純物濃度が５Ｘｌ
Ｏ”〜１×１０°ｃｍ−”程度となるように拡散して２
０′″型コンタクト領域５を形成し、全面にアルミニウ
ム膜を形成して、これをバターニングし、電極・配線６
を形成し、１００Ω〜１０にΩ程度の拡散抵抗を形成す
る。A silicon dioxide layer 4 is formed on the surface using a CVD method or the like, and an opening is formed in the contact region 5 formation region by buttering, and a p-type impurity such as boron is added to the impurity concentration of 5Xl.
Diffuse it so that it is about 0"~1 x 10°cm-"2
A 0'' type contact region 5 is formed, an aluminum film is formed on the entire surface, and this is patterned to form an electrode/wiring 6.
, and form a diffused resistance of about 100Ω to 10Ω.
以上説明せるとおり、本発明に係る半導体装置において
は、一導電型の半導体層の表面に反対導電型の領域が形
成され、この反対導電型の領域の一部領域に前記の一導
電型の半導体層と絶縁されて一導電型の領域が形成され
、前記の反対導電型の領域をもって抵抗が構成されてい
る半導体装置において、前記の一導電型の領域が抵抗の
長手方向と交叉する方向に分割されているため、抵抗を
構成する反対導電型の領域に発生する電圧降下が大きい
場合にも、反対導電型の領域と分割された一導電型の領
域との間に加わる電圧は、分割された一導電型の領域の
幅にほり比例して低（なるので、反対導電型の領域と分
割された一導電型の領域との間のＰ−Ｎ接合部のブレー
クダウン電圧よりも低くなり、絶縁破壊は起こらない。As explained above, in the semiconductor device according to the present invention, a region of the opposite conductivity type is formed on the surface of the semiconductor layer of one conductivity type, and a part of the region of the opposite conductivity type is covered with the semiconductor layer of the one conductivity type. In a semiconductor device in which a region of one conductivity type is formed insulated from a layer, and a resistor is constituted by the region of the opposite conductivity type, the region of one conductivity type is divided in a direction intersecting the longitudinal direction of the resistor. Therefore, even if the voltage drop occurring in the regions of the opposite conductivity type that constitutes the resistor is large, the voltage applied between the region of the opposite conductivity type and the divided region of one conductivity type is The voltage decreases in proportion to the width of the region of one conductivity type, so it becomes lower than the breakdown voltage of the P-N junction between the region of the opposite conductivity type and the divided region of one conductivity type. No destruction will occur.
第１ａ図は、本発明の一実施例に係る半導体装置の断面
図である。
第１ｂ図は、本発明の一実施例に係る半導体装置の平面
図である。
第２図〜第４図は、本発明の一実施例に係る半導体装置
の工程図である。
第５図、第６図は、従来技術に係る半導体装置の断面図
である。
５・・・コンタクト領域、
６・・・電極・配線、
７．８・・・レジスト層、
９・・・開口。FIG. 1a is a sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 1b is a plan view of a semiconductor device according to an embodiment of the present invention. 2 to 4 are process diagrams of a semiconductor device according to an embodiment of the present invention. 5 and 6 are cross-sectional views of a semiconductor device according to the prior art. 5... Contact region, 6... Electrode/wiring, 7.8... Resist layer, 9... Opening.
Claims (1)
２）が形成され、 該反対導電型の領域（２）の一部領域に、前記一導電型
の半導体層（１）と絶縁されて一導電型の領域（３）が
形成されてなり、 前記反対導電型の領域（２）をもって抵抗が構成されて
なる半導体装置において、 前記一導電型の領域（３）は、前記抵抗の長手方向と交
叉する方向に分割されてなる ことを特徴とする半導体装置。[Claims] A region of the opposite conductivity type (
2) is formed, and a region (3) of one conductivity type is formed in a part of the region (2) of the opposite conductivity type, insulated from the semiconductor layer (1) of one conductivity type, and A semiconductor device in which a resistor is configured with a region (2) of an opposite conductivity type, characterized in that the region (3) of one conductivity type is divided in a direction intersecting the longitudinal direction of the resistor. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20104288A JPH0251263A (en) | 1988-08-13 | 1988-08-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20104288A JPH0251263A (en) | 1988-08-13 | 1988-08-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0251263A true JPH0251263A (en) | 1990-02-21 |
Family
ID=16434458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20104288A Pending JPH0251263A (en) | 1988-08-13 | 1988-08-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0251263A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5990538A (en) * | 1996-02-01 | 1999-11-23 | Micron Technology, Inc. | High resistivity integrated circuit resistor |
| KR20020071099A (en) * | 2001-03-03 | 2002-09-12 | (주)에너펙텍 | A hydrogen and oxygen generator |
| US6500723B1 (en) * | 2001-10-05 | 2002-12-31 | Motorola, Inc. | Method for forming a well under isolation and structure thereof |
| JP2006518006A (en) * | 2003-02-17 | 2006-08-03 | オーエム エナジー リミテッド | Plant for decomposing water by electrolysis |
-
1988
- 1988-08-13 JP JP20104288A patent/JPH0251263A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5990538A (en) * | 1996-02-01 | 1999-11-23 | Micron Technology, Inc. | High resistivity integrated circuit resistor |
| KR20020071099A (en) * | 2001-03-03 | 2002-09-12 | (주)에너펙텍 | A hydrogen and oxygen generator |
| US6500723B1 (en) * | 2001-10-05 | 2002-12-31 | Motorola, Inc. | Method for forming a well under isolation and structure thereof |
| JP2006518006A (en) * | 2003-02-17 | 2006-08-03 | オーエム エナジー リミテッド | Plant for decomposing water by electrolysis |
| JP4729311B2 (en) * | 2003-02-17 | 2011-07-20 | オーエム エナジー リミテッド | Plant for decomposing water by electrolysis |
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