JPH025085A - Power circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption by generating a potential difference between mutually different levels by a potential difference generating means and supplying a driving signal to a potential difference selecting means. CONSTITUTION:The power circuit 4 consists of transistors(TR) Tp1 and Tp2 as the potential difference generating means which generates the constant potential difference by being applied with a DC voltage and TRs Tp3 and Tn1 as the potential difference selecting means which extracts a desired-level potential difference selectively from the potential difference by turning on and off said TRs Tp1 and Tp2. Those TRs are paired and connected in parallel to constitute voltage dividing circuits 4a and 4b as a voltage dividing means which divides an applied DC voltage Vdd into different level voltages and leads them out individually. Thus, the driving signal is supplied to the potential difference selecting means and the difference level voltages are extracted selectively from potential differences generated by the potential difference generating means and led out. Consequently, a source voltage of necessary level can be supplied with low power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a power supply circuit suitably implemented in a liquid crystal display device or the like.

<Prior Art> In recent years, with the progress of miniaturization and lower power consumption of electronic devices, liquid crystal display devices using liquid crystal elements have been widely used as display means suitable for these devices. An operating voltage is supplied from the power supply circuit to the liquid crystal drive circuit for this purpose.

FIG. 3 is a block diagram showing the electrical configuration of the liquid crystal display device I. In order to display characters such as letters and figures on a liquid crystal display device (hereinafter referred to as display device) 2 consisting of a plurality of liquid crystal elements, a liquid crystal drive circuit (hereinafter referred to as “display device”) is used.
A display signal S such as characters to be displayed is sent to the drive circuit (referred to as a drive circuit) 3 via a line g4 and a line e5.
and drive signal F are respectively input. The drive circuit 3 outputs the logic level if ]l+ as the drive voltage.
A segment drive voltage v1 having not only the binary value of %I Q +1 but also an intermediate level therebetween and a back grade voltage 2 are applied to the display device 2 via lines 2I and 12, respectively. The power supply voltages a, vb, and VC necessary to create the above segment drive voltage v1 and back plate voltage v2 are connected to the line 16.1 from the power supply circuit 4.
7 and /8 to the drive circuit 3.

FIG. 4 ft) is the waveform of the drive signal F, whose frequency is, for example, 0 Hz, and every 1/2 cycle period,
The level changes alternately between the ground potential GND (OV) and the power supply voltage Vdd, that is, the logic level "+Q +1."
Repeat “I”.

FIG. 4(2) shows the waveform of the segment drive voltage V1 also output from the drive circuit 3, which is 1/1/2 of the drive signal F.
Vdd with 4 duty and level divided by 3 of logic level
, Via, and Vlb, using a 1/3 bias method.

FIG. 4(3) shows the waveform of the back plate voltage V2, which has a 1/4 duty like the segment drive voltage Vl and whose levels are three parts of the logic level, Vdd, V2a,
It is created using a 1/3 bias method that changes with V2b.

FIG. 5 is a circuit diagram of a power supply circuit 4 according to the prior art. The power supply circuit 4 is formed by a series circuit of resistors R1-R4,
Power supply voltage Vdd is applied, current 1 flows, and each resistor R1
A potential difference occurs at the connection points S, c, and d of ~R4 due to a voltage drop.

Transistors Tp and Tn, which are switching elements, are connected in parallel to the resistors R1 and R4, and when the drive signal F inputted through the line 15 is 0', the transistor Tp
conducts, the transistor Tn is cut off, the voltage Va delivered to the line la becomes equal to the power supply voltage Vdd, and the levels of the voltages vb, vc delivered to the lines lb, lc rise.

Next, when the drive signal F is 11 ] +1, on the contrary, the transistor Tp is cut off and the transistor Tn is turned on, so that the voltage VC on the line lc becomes OV, and the line 1! a,
The levels of voltages va and vb of eb decrease.

In this way, the voltage v a - v c whose level changes depending on the drive signal F is supplied as a power supply voltage to the drive circuit 3 shown in FIG. 3, and the drive circuit 3 responds to the level change as shown in FIG. A segment drive voltage Vl and a back plate voltage v2 are created.

<Problems to be Solved by the Invention> However, in the conventional technique shown in FIG. However, it consumes a lot of power, which has been an obstacle to reducing the power consumption of devices.

Therefore, a power supply circuit with low power consumption has been desired.

The present invention has been made in view of the above-mentioned technical problems, and its purpose is to provide a power supply circuit that consumes low power and can supply a required level of power supply voltage. be.

Means for Solving the Problems> The present invention provides such a power supply circuit including voltage dividing means for dividing an applied DC voltage into voltages at different levels and individually deriving the voltages, The voltage dividing means is
It includes a plurality of potential difference generation means of a semiconductor structure to which a voltage is applied to generate a constant potential difference, and a potential difference selection means of a semiconductor structure that selectively extracts a desired level from the plurality of potential differences formed by the potential difference generation means. This is a power supply circuit characterized by being configured.

<Operation> The power supply circuit according to the present invention includes a plurality of potential difference generating means to which a DC voltage is applied to generate a constant potential difference, and a semiconductor structure that selectively extracts a desired level from the plurality of potential differences formed by the potential difference generating means. forming a voltage dividing means with the potential difference selecting means, and supplying a drive signal to the potential difference selecting means to selectively extract a desired potential difference from the plurality of potential differences formed by the potential difference generating means, thereby causing a current to flow. Instead, they derive different levels of voltage from each other.

<Embodiment> FIG. 1 is a configuration diagram showing the electrical configuration of a power supply circuit 4 according to an embodiment of the present invention. The power supply circuit 4 includes transistors Tpl and Tp2, which are potential difference generating means that generate a constant potential difference by applying a DC voltage, and transistors Tpl and Tp2.
A transistor Tp3.p2 serves as potential difference selection means for selectively extracting a desired level of potential difference from the potential difference by short-circuiting/opening Tp2. Constructed by Tnl. Transistors Tpl, Tp3, and transistor Tp2.

Tnl is formed by voltage dividing circuits 4a and 4b which are connected in parallel in pairs and are voltage dividing means for dividing the applied DC voltage Vdd into voltages of different levels and deriving them individually. has been done.

Transistors Tpl to Tp3 are P-channel MIS
(insulated gate) type field effect transistor, and transistor Tnl is an N-channel MIS type field effect transistor with opposite polarity. Transistor Tp8. The gates of Tn+ are commonly connected to line J5, and conduction/cutoff is controlled by drive signal F. Furthermore, the gates of the transistors Tpl and Tp2, which are potential difference generating means, are connected to their respective sources.

Transistor Tpl forming the first voltage dividing circuit 4a.

The line 13 to which the drains of Tp8 are commonly connected is
Power supply voltage V, dd (for example, 3V in this embodiment)
A line 16 to which the sources of the transistors Tpl and Tp3 are connected in common is connected to the output terminal P1 of the first voltage dividing circuit 4a. Further, a line e7 to which the drains of transistors Tp2 and Tnl forming the second voltage dividing circuit 4b are commonly connected is connected to the output terminal P of the second voltage dividing circuit 4b.
2 and transistors Tp2. A line 19 to which the sources of Tnl are commonly connected is connected to a ground line GND having an OV potential.

A drive circuit 3 is connected between the output terminal P1 of the first voltage dividing circuit 4a and the output terminal 22 of the second voltage dividing circuit 4b. Therefore, a series circuit of the first voltage dividing circuit 4a, the driving circuit 3, and the second voltage dividing circuit 4b is connected between the line 13 and the ground line GND, so that the transistors Tp3. When both Tnl are in the cut-off state, a voltage V1 which is lowered from the power supply voltage Vdd by the threshold voltage Vthl of the transistor Tpl is derived from the line e6, that is, the output terminal P1, and a voltage V1 which is lowered by the threshold voltage Vth1 of the transistor Tp2 from Ov is derived from the line 17. The voltage V2 is derived, and the difference voltage vl-v2 acts as the power supply voltage of the drive circuit 3.

Both transistors Tpl and Tp2 are MIS type field effect transistors, and their gates are connected to the same potential as their sources, so their internal impedance is extremely high, and the drive circuit 3 also has a high impedance with respect to the voltage vl-v2. Therefore, when deriving the voltages vl and v2, almost no current flows from the line 13,
Therefore, power consumption is small.

'! In a normal bipolar transistor, the threshold voltage is approximately constant at about 0.6 to 0.7 V, whereas in an MIS type field effect transistor, the threshold voltage vth can be set to an arbitrary value during the transistor manufacturing process.

Therefore, by appropriately selecting the threshold voltage vth of the transistors Tpl and Tp2 forming the voltage dividing circuits 4a and 4b, it is possible to divide the power supply voltage Vdd and derive the voltages vl and v2 corresponding to the drive circuit 3. The operation of this embodiment will be described below with reference to FIG.

In FIG. 1, the power supply voltage V applied to line 773
It is assumed that dd is, for example, 3■, and that the threshold voltage Vth1 of the transistor Tp+, which is a potential difference generating element, and the threshold voltage Vt112 of the transistor Tp2 are both equal, for example, 1V. Transistor Tp8. Since Tnl is alternately cut off or turned on depending on the polarity of the drive signal F, for example, if the drive signal F is ++
At the timing of 11 levels, the transistor Tnl on the ground line GND side becomes conductive, and the transistor Tp3 on the 10 potential Vdd side is cut off. Therefore, the voltage v of line 17
2 is OV, and the voltage v1 of the line 16 is a voltage 2V that is lower than the power supply voltage Vdd (3V) applied to the line 13 by the threshold voltage Vth (IV).

Next, at the timing when the drive signal F is at the 0" level, the transistor Tp8 becomes conductive and the transistor Tn+ is cut off. Therefore, the voltage v1 on the line 26 is
The line l! rose to 3V equal to the voltage Vdd of the line l! 7
The voltage V2 becomes the voltage IV increased by the threshold voltage IV of the transistor Tp2.

FIGS. 2(1) to 2(3) are waveform diagrams showing signal and voltage waveforms of each part of the power supply circuit 4 of this embodiment.

The time axes of FIGS. 2(1) to 2(3) are all the same, and will be explained with reference to FIG. 1 as well.

FIG. 2(1) shows the transistor Tp via line e5.
3. The waveform of the drive signal F applied to each gate of Tnl is shown. The drive signal F is an alternating waveform with a frequency of, for example, 100 Hz and an amplitude of OV - power supply voltage Vdd (SV in this embodiment). The level of the power supply voltage Vdd is "11 levels," and the level of OV is "01 levels." When the level is ``1'' and when the level is +1011, the voltage dividing circuits 4a and 4b
transistor Tp8.

As described above, the conduction timing of Tnl is opposite.

FIG. 2(2) shows the level change of the voltage v1 derived to the line I6. The voltage ■1 is derived at the level of the line p1 which is lower than the power supply voltage Vdd by the threshold voltage vth during the period t] when the drive signal F is at the "1" level, and when the drive signal F is at the (I 01 level) level t2, the voltage It is derived at a level equal to voltage Vdd.

FIG. 2(3) shows the level change of the voltage v2 derived on the line 17. The voltage V2 is equal to the drive signal F of 11]
In a period of 1 level [1, the drive signal F is derived at OV, and in a period t2 of i+01 levels, the drive signal F is derived at the level of line p2 which has increased from Ov by the threshold voltage vth.

In this way, the drive circuit 3 receives a voltage vl whose level changes in accordance with the timing of the drive signal F.

V2 is supplied as the power supply voltage, and thereby the drive circuit 3 creates intermediate level voltages Vl and V2 necessary for display in addition to the logic level 11311, R]+1, and applies them to the liquid crystal display device 2 to display the desired voltage. display.

In the above embodiment, the voltage obtained from the power supply circuit 4 is set to three levels, but the levels are not limited to three, and the application is of course not limited to liquid crystal display devices. It is.

<Effects of the Invention> As described above, in the power supply circuit according to the present invention, potential differences of different levels are formed by the plurality of potential difference generation means that generate a constant potential difference by applying a DC voltage, and the potential difference selection means drives the power supply circuit. By applying a signal, a desired voltage level was obtained. Since the potential difference generating means and the potential difference selecting means have a semiconductor structure, there is no need to conduct a current as in the conventional technology to obtain a desired voltage level, and a power supply circuit with significantly reduced power consumption is realized.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of a power supply circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the voltage and signal waveforms of each part, and FIG.
The figure is a block diagram showing the electrical configuration of a general liquid crystal display device 1, FIG. 4 is a waveform diagram showing voltage and signal waveforms necessary for liquid crystal display, and FIG. 5 is an electric circuit of a power supply circuit according to the conventional technology. It is a diagram. 3...Liquid crystal drive circuit, 4...Power supply circuit, 4a, 4b
...Voltage divider circuit, F/drive signal, Tpl, Tp2゜Tp
3...P channel MIS) transistor, Tnl/N channel MIS) transistor.

Claims (1)

[Claims] 1. Such a power supply circuit including voltage dividing means for dividing an applied DC voltage into voltages of different levels and individually deriving the voltages, the voltage dividing means comprising: A plurality of potential difference generation means of a semiconductor structure to which a voltage is applied to generate a constant potential difference; and a potential difference selection means of a semiconductor structure for selectively extracting a desired level from the plurality of potential differences formed by the potential difference generation means. A power supply circuit comprising: