JPH0250718A - Data input circuit - Google Patents

Abstract

PURPOSE:To accurately input data consisting of many bits from a simple pulse generating circuit by masking a data register writing signal during a period in which the contents of a measuring counter coincide with that of a data register and a certain fixed period before and after the coincidence period. CONSTITUTION:The title data input circuit includes pulse width variable elements 13, 14 for varying the width of a pulse signal and generates a data input signal consisting of the set of periodical signals. A mask timing generating circuit 8 is started by an output 115 from a coincidence deciding circuit 6 to turn a data register writing mask signal 117 to low before a ceratain time (a) from the period in which the contents of the data register 4 coincide with that of the counter 2 and turn the signal 117 to a high state after a certain time (b) from the rediscrepancy between the contents of the register 4 and the counter 2. Thus, the data register writing signal is masked during the coincidence period between the contents of the register 4 and the counter 2 and the period arranged before and after the coincidence period. Consequently, data consisting of many reliable bits can be inputted.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a variable data input circuit for electronic equipment.

[Conventional technology]

The conventional method of inputting variable data by changing the width of periodic pulses by operating a variable pulse width element and measuring the pulse width reads the data multiple times and processes it using software. The stability of the data was obtained through these methods. However, it was unsuitable for applications that required higher reliability, such as setting computer parameters.

[Problem to be solved by the invention]

Pulse signal generating circuits usually have slight jitter and also have temperature characteristics. In a pulse width measurement circuit that does not have a data register write control circuit, the value of the data register will become K or +1 near the boundary value between a certain value K (K is a positive integer) and the next value +1. It does not reach a stable value. Since the pulse width takes an arbitrary value depending on the pulse width variable element, there is a sufficient probability that the measured value of the pulse width will be near the above boundary. In particular, when the number of bits (accuracy) of data is large, it is strongly influenced by the jitter and temperature characteristics described above. Therefore, when the number of bits of data is large, the value of the data register varies with probability, and it is difficult to obtain an accurate value. An object of the present invention is to make it possible to accurately input data of a large number of bits from a simple pulse generation circuit by adding a data register write control circuit to a pulse measurement circuit.

[Means for Solving the Problems] A data input circuit according to the present invention includes a variable pulse width element that varies the pulse signal width, and generates a data input signal consisting of a set of periodic at least one type of data input pulse signals. a measurement counter operated by a measurement basic clock to measure the data pulse signal width; and at least one or more data items each storing measurement results of the data pulse signal width. a pulse width measuring circuit comprising a register, and a data register write signal control circuit for masking a write signal of each of the data registers during a period in which the contents of each of the data registers and the measurement counter match, and a period before and after the period; It is characterized by consisting of.

The present invention also provides a data input signal generation circuit that generates a data input signal consisting of a header signal indicating the head of the data pulse signal group and the data pulse signal group, and a data input signal generation circuit that detects the header signal from the data input signal. It is characterized by comprising a pulse width measurement circuit equipped with a header detection circuit.

[Effect]

In the data input circuit of the present invention, when a certain data pulse is input, the pulse width is measured, and at the same time, the measurement counter and the data register are compared, and the period when the contents of the measurement counter and the data register match, and the period before and after that, is measured. The data register write signal is masked for a certain period of time.

〔Example〕

The following is the data of the present invention. FIG. 1, which is an embodiment of a data input circuit, will be described.

In this embodiment, the measured periodic pulse widths are of two types: a positive data pulse and a negative data pulse (in other words, the HIGH width and the LOW width of the data input signal 105). Therefore, the pulse width variable element (here represented by a variable resistor) included in the pulse generation circuit is 13.1
There are 2 of 4.

The data register 4.5 and the match judgment circuit 6.7 are each 2
However, the other parts can be shared for two types of pulse widths. Here, the data register write signal control circuit is comprised of an adder 3, a match determination circuit 6.7, a mask timing generation circuit 8, and the like.

The operation of measuring the width of the negative data pulse signal output by the pulse generating circuit and inputting it to the data register 4 is as follows. First, when the data input signal 105 falls to LOW, the measurement counter 2 is reset. While the data input signal 105 is LOW, the counter is operated by the measurement clock 118, and the data input signal 105 is LOW.
Measure the time since the At the same time, the output 114 of the adder 3 which adds a constant 1 is compared with the data register 4, and when they match, the output 115 of the match determination circuit 6 is output and the mask timing generation circuit 8 starts operating. In other words, since the signal 114 is the output of the measurement counter added by 1, the mask timing generation circuit 8
is started. This is because the data register write signal is masked before and after the period when the values of the data register 4 and the counter 2 match. The mask timing generation circuit 8 is activated by the output 115 of the coincidence determination circuit 6, and turns the data register write mask signal 117 to LOW (masks) a certain period a from the period in which the values of the data register 4 and the counter 2 match. ) and the data register write mask signal 117 is set to HIGH after a certain period of time after the values of the data register 4 and the counter 2 become inconsistent again. In this way, the data register write signal is masked for a period including the period in which the values of the data register 4 and the counter 2 match and the periods (a, b) before and after that period. On the other hand, the data register write signal 109 is generated by the timing circuit 9 by detecting the rising edge of the data input signal 105 by the rising edge detector 11 . The signal 111 input to the write control terminal of the data register is 109
is masked by the data register write mask signal. A timing chart of the above operation is shown in FIG. The operation of measuring the width of the positive data pulse and entering it into the data register 5 is similar to the above operation.

In Figures 1 and 2, 101 is the basic clock;
02 is the output of the measurement counter, 103 is the reset signal of the measurement counter, 104 is the output of the previous stage counter, 105 is the data input signal, 106 is the falling detection pulse signal, and 107 is the rising detection pulse signal. , 108 is a data register write signal (HIGH
109 is the data register write signal (LOW pulse width), 110 is the masked data register write signal (HIGH pulse width), 11
1 is the masked data register write signal (LO
W pulse width), 112 is the output of data register 4, 113 is the output of data register 5, 114 is the output of measurement counter 2 plus 1, and 115 is the A input of coincidence judgment circuit 6. 116 is a signal indicating that the A and B inputs of the match determination circuit 7 are equal; 117 is a mask signal for the data register write signal; and 118 is a measurement clock.

Next, a description will be given of FIG. 3, which is an embodiment of the data input circuit for data inputting data according to claim 2 of the present invention.

In this embodiment, the number of data pulses to be measured is N (N is an integer of 2 or more), and the number of variable pulse width elements and data registers is also N.

In the embodiment shown in FIG. 1, a header detection circuit 511 and a data counter 512 are mainly added, and a data register, a match judgment circuit, and a pulse width variable element are N.
There are only dots.

The operation of measuring the pulse widths of N types of data pulses output from the pulse generating circuit and inputting them to N data registers is as follows. A header detection circuit finds a header signal indicating the beginning of a data pulse in data input signal 610 and resets data counter 512 .

The data counter counts up each time a rising detection pulse and a rising detection pulse are input, and indicates the order of the data pulses. That is, the count is incremented every time a data pulse is input, and the output of the data counter 512 is 0 at the first data pulse and N-1 at the last data pulse. The timing circuit 508 selects a data register, a coincidence judgment circuit, etc. corresponding to the order of data pulses according to the output 613 of the data counter 512, and controls each data register write signal. There are many possible shapes for the header signal, but the simplest ones are a method that uses a pulse width that is sufficiently shorter than the minimum pulse width of the data pulse, and a method that uses a pulse width that is sufficiently longer than the maximum pulse width of the data pulse. be. Figures 4 and 5 show data input signals when a signal with a pulse width sufficiently shorter than the data pulse is used as the header and when a signal with a pulse width sufficiently longer than the data pulse is used as the header. 610a is a data input signal when a signal with a pulse width sufficiently shorter than the data pulse of the second embodiment of the present invention is used as a header, and 610b is a data input signal when a signal with a pulse width sufficiently longer than the data pulse is used as a header. be. 701.8
01 is the header signal, 702.802 is the first data pulse signal, and 704.804 is the last data pulse.

In FIG. 3, 601 is the basic clock, 602 is the measurement clock, 603 is the output of the measurement counter,
604 is a reset signal for the measurement counter, 605 is the output of measurement counter 2 added by 1, and 60
6 is the output of data register 4, 607 is the output of data register 5, 608 is a signal indicating that the A input and B input of match judgment circuit 6 are equal, and 60゛9 is the A input of match judgment circuit 7. A signal indicating that the B inputs are equal, and 6
10 is a data input signal, 611 is a pulse indicating that a header has been detected, 612 is an OR signal of the rising detection pulse signal and the falling detection pulse, 613 is the output of the data counter 12, and 614 is the data register 4 615 is a write signal for the data register 5.

〔Effect of the invention〕

In the above data input circuit of the present invention, the pulse width when the data register is rewritten to a certain value M for the first time is within the period during which the counter is a certain value M (M is a positive integer); In order to rewrite M to another value, the width of the data pulse signal must be a value that is outside the period (a, b) before and after that and the period in which the counter is at a certain value M. Therefore, the value of the data register does not change due to a minute change in pulse width. Therefore, it is possible to input data of a large number of bits with high reliability using a variable pulse width pulse generation circuit such as an ordinary oscillation circuit. In the second embodiment, it is possible to input a large number of variable data by knowing the beginning of a data pulse group from the header signal of the data input signal. Furthermore, the pulse width measuring circuit is entirely composed of logic circuits and can be easily integrated into an IC. In other words, it can be integrated into an IC and is very effective for inputting IC parameters where many parameters need to be freely set.

[Brief explanation of the drawing]

FIG. 1 is a plotter diagram of an embodiment of a data input circuit according to claim 1 of the present invention. FIG. 2 is a time chart diagram of each signal of FIG. 1 according to the present invention. FIG. 3 is a block diagram of an embodiment of the data input circuit according to claim 2 of the present invention. FIG. 4 is a time chart diagram of an embodiment of the 610 signal of FIG. 3 according to the present invention. FIG. 5 is a time chart diagram of an embodiment of the 610 signal of FIG. 3 according to the present invention. 1... Pre-stage counter 2... Pulse width measurement counter 3... Adder for adding constant 1 4.5... Data register 6.7... Coincidence judgment circuit 8... Mask timing generation circuit 9... Timing circuit 10...Fall detection circuit 11...Rise detection circuit 12...Pulse signal generation circuit 13.14...Pulse width variable element 501...Pre-stage counter 502...Pulse width measurement counter 503...1 Adder 504,505...Data register 506,507...Coincidence judgment circuit 508...Timing circuit 509...Falling detection circuit 10, 11, 12, 13, 14, Rising detection circuit Header detection circuit Data counter pulse Signal generation circuit 15...Pulse width variable element and above Applicant: Seiko Epson Co., Ltd. Patent attorney Kizobe Suzuki and others (reference flock) Figure N4 Figure 5

Claims (2)

[Claims] (1) A pulse signal that includes a pulse width variable element that makes the pulse signal width variable and generates a data input signal consisting of a set of periodic at least one type of data input pulse signals (hereinafter referred to as data pulse signals) a generation circuit, a measurement counter operated by a measurement basic clock to measure the data pulse signal width, at least one or more data registers each storing measurement results of the data pulse signal width, and the data pulse signal width. a pulse width measurement circuit equipped with a data register write signal control circuit for masking the write signal of each of the registers during a period in which the contents of each of the data registers and the measurement counter match, and a period before and after that period; A data input circuit characterized in that desired data is input to each of the data registers by operating each of the variable width elements. (2) a data input signal generation circuit that generates a data input signal consisting of a header signal indicating the head of the data pulse signal group and the data pulse signal group; and a header detection circuit that detects the header signal from the data input signal. 2. The data input circuit according to claim 1, further comprising a pulse width measuring circuit.