JPH0250222A - Operand supplying system - Google Patents

Abstract

PURPOSE:To reduce firmware quantity by making a supplying pass being the instruction executing part of an immediate operand the same as a memory operand. CONSTITUTION:An immediate operand detecting means 115 provided in an instruction fetching part 111 detects whether the immediate operand is included in an instruction word taken out from a memory control part 101 or not. When it is detected that the immediate operand is included, the immediate operand in the instruction word is sent to the memory control part 101 by an immediate operand sending means 117 and transferred to an instruction executing part 131 by the memory control part 101 with use of a supplying pass P the same as the memory operand. Accordingly, in the instruction executing part 131, the taking out of the immediate operand can be executed samely as the memory operand. Thus, the firmware to be prepared in each instruction for immediate operand is eliminated and whole firmware capacity can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The invention relates to a method for supplying an immediate operand to an instruction execution unit in a central processing unit.

[Conventional technology]

An operand is data specified by an instruction word, that is, data that is the target of an operation, and is generally an immediate operand or a register operand.

There are different types of memory operands. An immediate operand is an operand included in an instruction word, a register operand is an operand stored in a software-visible register specified by an instruction word, and a memory operand is an operand contained in an instruction word. Refers to the operand that exists in the memory (main memory) specified by the address in the instruction word. All operands are ultimately taken into the operand register in the instruction execution unit that executes the operation specified by the instruction word, and are processed by the memory control unit that controls data transfer to and from memory. , a central processing unit that includes an instruction fetching section that controls fetching of an instruction word, and an instruction execution section that executes an operation specified by the instruction word fetched by the instruction fetching section, and that controls execution of operands by firmware. handles each type of operand as follows:

First, the instruction execution unit in the central processing unit is provided with separate hardware mechanisms for receiving and receiving immediate operands, register operands, and memory operands, and firmware for the number of types of the above three operands is installed for each instruction. A firmware storage memory having an entry is provided, and the instruction fetch section decodes the instruction code part of the instruction word fetched from the memory control section to determine the type of instruction code and the type of specified operand. , launches the firmware in the firmware entry corresponding to that operand type of that instruction. As a result, for example, in the case of an immediate operand, the firmware corresponding to the type of operand of that instruction is activated, and the immediate operand in the instruction word that was fetched by the instruction fetching section becomes the immediate operand. The instruction is fetched from the instruction fetching section to the instruction execution section by the hardware mechanism, and is set in the operand register and processed. In the case of a memory operand, the memory operand read from the memory by the memory control unit is controlled by the firmware that corresponds to the type of operan 1 of the instruction in question. The instruction processing unit imports the instruction from the memory control unit to the instruction execution unit, writes it to the operand register, and processes it. Further, in the case of a register operand, firmware corresponding to the type of operand of the instruction is activated, and the register operand stored in an internal software-visible register is stored in the operand register and processed.

[Problem to be solved by the invention]

In the conventional central processing unit described above, the immediate operand is supplied from the instruction fetching section to the instruction execution section, the memory operand is supplied from the memory control section to the instruction execution section, and the register operand exists within the instruction execution section. It is retrieved from a software-visible register. Therefore, as mentioned above, it was necessary to provide a hardware mechanism for each type of operand to receive and receive each operand, and to prepare firmware correspondingly for each type of operand for each instruction. .

Therefore, the overall amount of firmware (number of firmware steps) has become considerably large.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an operand supply method that makes it possible to reduce the amount of firmware by using the same bus for supplying immediate operands to an instruction execution unit as for memory operands.

(Means for Solving the Problems) In order to achieve the above object, the operand supply method of the present invention includes a memory control unit that controls data transfer to and from memory, and an instruction fetch unit that controls fetching of instruction words. and an instruction execution section that executes an operation specified by the instruction word fetched by the instruction fetch section, the instruction word fetched from the memory control section includes an immediate operand. an immediate operand detection means for detecting whether the instruction word is an immediate operand; the instruction fetching section is provided with immediate operand sending means for sending out an immediate operand to the instruction fetching section, and when the memory control section receives the immediate operand from the instruction fetching section, the received immediate operand is sent to the instruction fetching section. The information is configured to be transferred to the instruction execution unit via a supply bus.

[Effect]

In the operand supply method of the present invention, the immediate operand detection means provided in the instruction fetching section
It is detected whether or not an immediate operand is included in the instruction word fetched from the memory control section, and if it is detected that the instruction word is included, the immediate operand sending means also provided in the instruction fetch section sends the immediate operand. The immediate operand in the instruction word is sent to the memory control unit, and the memory control unit transfers this immediate operand to the instruction execution unit through the same supply path as the memory operand.

[Example] Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of the main parts of a central processing unit to which the operand supply method of the present invention is applied, and 101 is a memory control unit (MB) that controls data transfer to and from a memory (not shown).
U), 111 is a command fetching unit (PFU) that controls fetching of instruction words, 121 is a firmware control unit, 13
Reference numeral 1 denotes an instruction execution unit (EXU) that executes the operation specified by the instruction word extracted by the instruction extraction unit 111 by executing the corresponding firmware stored in the firmware control unit 121.

Memory control unit 101. The instruction retrieval unit 111, the firmware control unit 121, and the instruction execution unit 13I include the main components related to the operand supply method of the present invention. That is, the memory control unit 101 includes a memory read register 102, a memory read data output buffer 103, an immediate operand input buffer sofa 104, and registers 105 and 106 for adjusting pipeline timing. , memory read data manual buffer 112, selector 113 . Instruction register 114. Immediate operand detection means 115. Instruction buffer register 116. Immediate operand sending means 117 and immediate operand/memory operand OR gate 118
The firmware control section 121 includes a firmware storage memory 122, and the instruction execution section 131 includes an operand register 132.

FIG. 2 shows that in FIG. 1, an instruction word including an immediate operand is transferred from the memory control unit 101 to the instruction fetching unit 111, and the immediate operand in the instruction word is transferred to the memory control unit 101 again. , is a time chart when the instruction is supplied to the instruction execution unit via the memory control unit 101. Also, Figure 3 shows an image of the instruction word including the immediate operand in memory,
This instruction word 300 is composed of an instruction code section 301 and an immediate operand 302. Furthermore, referring to FIG. 4, the instruction code section 301 includes an instruction code 401
and an address syllable (describing the procedure for addressing the operand) 402.

Next, with reference to FIGS. 1 to 4, the operation of the operand supply system of this embodiment for supplying the immediate operand 302 shown in FIG. 3 to the instruction execution section 131 will be described.

Referring to FIG. 1, in response to an instruction fetch request issued from the instruction fetching unit 111 to the memory control unit 101, the memory control unit 101 sends the memory read register 102
An instruction word (in this case, an instruction word 300 including the immediate operand 302 shown in FIG. 3) is set at timing t1 in FIG. 2. This memory read register 10
The instruction word 300 set to 2 is the memory read data output buffer 103. The instruction code section 301 in the instruction word 300 is supplied to the instruction fetch section 111 via the path P1 between the memory control section 101 and the instruction fetch section 111, and at timing t2 in FIG. 112 and selector 113, and the immediate operand 302 is set in the instruction buffer register 116 via the memory read data input buffer 112.

Instruction code section 301 set in instruction register 114
That is, the instruction code 401 and address syllable 402 in FIG. 4 are decoded by the immediate operand detection means 115. As a result, when it is detected that the instruction word 300 is an instruction word containing an immediate operand,
The immediate operand sending means 117 is enabled by the output of the immediate operand detecting means 115, and the immediate memory operand firmware entry 1 corresponding to the instruction code 401 is
23 is sent from the immediate operand detection means 115 to the firmware control unit 121 via the immediate operand/memory operand OR gate 118 and the path P2 between the instruction fetching unit 111 and the firmware control unit 121. Firmware entry 123 for immediate memory operand
will be highlighted.

When the immediate operand sending means 117 is enabled as described above, the immediate operand 302 in the instruction buffer register 116 is transferred to the activated immediate operand sending means 117. It is sent to the memory control unit 101 via the path P1, and the memory control unit 101
In this case, this immediate operand 302 is set in the pipeline timing adjustment register 105 via the immediate operand input buffer 104 at timing t3 in FIG. The timing t in FIG. 2 is stored in the register 106.
4, the memory controller 1 is set at timing t4.
01 and the instruction execution unit 131 via the path P3. Then, the instruction execution unit 131
, the operation specified by the firmware in the pointed immediate memory operand firmware entry 123 is started at timing 4 in FIG.
Immediate operand 30 transferred from 01
2 is set in the operand register 132 at timing L5, and then the operation specified by the instruction code 401 is executed on the immediate operand 302.

On the other hand, if the instruction code set in the instruction register 114 is the same as the instruction code shown in FIG. 4, but the address syllable does not specify an immediate operand but specifies a memory operand, the instruction buffer register 1
The data in 16 is address information indicating a memory operand, not an immediate operand. In this case, the instruction buffer register 11
6 is transferred to the instruction register 114, and in accordance with the data, the memory control unit 101 is operated in the same manner as in the prior art to read out the false memory operand from the memory. The memory operand read by the memory control unit 101 is supplied from the memory control unit lot to the instruction execution unit 131 via a path P3.

That is, both the memory operand and the immediate operand are supplied from the memory control unit 101 to the instruction execution unit 131 via the same path P3.

Therefore, firmware corresponding to the same instruction code can be used for both the memory operand and the immediate operand.

Therefore, the immediate operand detection means 115
When the instruction code specifying the memory operand is decoded, it points to the same entry point as for the immediate operand, ie, firmware entry 123 for the immediate memory operand in FIG.

In this way, according to this embodiment, the immediate operand supply path to the instruction execution unit 131 can be shared with the memory operand supply path, thereby making it possible to share firmware corresponding to the same instruction code. It becomes possible to do so. Furthermore, since the supply path is shared, the instruction retrieval unit 111. For example, conventionally, the number of input/output bins of each LSI can be reduced when the instruction execution unit 131 and the like are implemented using individual LSIs.
If the immediate operand is supplied to the instruction execution unit 131 by a supply path with a width of 11 to 32 bits, 32 input/output pins can be reduced from each of the instruction fetch unit 111 and the instruction execution unit 131. .

〔Effect of the invention〕

As explained above, in the operand supply method of the present invention, the immediate operand is supplied from the memory control unit to the instruction execution unit via the same supply path as the memory operand, so the immediate operand is supplied to the instruction execution unit in the instruction execution unit. The eight operands can be taken in in the same way as the memory operands, so the firmware that was conventionally prepared for each instruction for the immediate eight operands is no longer necessary, and the overall firmware capacity can be reduced. Additionally, since the path for supplying immediate operands from the instruction fetching section to the instruction execution section is no longer required, when the instruction fetching section and the instruction execution section are integrated into an LSI, the number of input/output pins of each LSI can be reduced. It's also effective. Furthermore, since the firmware capacity can be kept small, it is also possible to reduce the number of gates in the LSI that constitutes the firmware storage memory.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of a central processing unit to which the operand supply method of the present invention is applied, Figure 2 is a time chart until the immediate operand is stored in the operand register of the instruction execution unit, and Figure 3 is A diagram showing an image of an instruction word including an immediate operand on the memory, and FIG. 4 are diagrams showing an example of the configuration of the instruction code section 301. In the figure, 101...Memory control unit (MBU) 102...Memory read register 103...Memory read data output buffer 104
... Immediate operand input cover sofa 105, 106... Register for pipeline timing adjustment 111... Instruction fetch unit (PFU) 112... Memory read data manual buffer 113... Selector 114... - Instruction register 115...immediate operand detection means 116
...Instruction buffer register 117...Immediate operand sending means 118
...immediate operand/memory operand O
R gate 121...firmware control unit 122...firmware storage memory 123...
Immediate memory operand firmware entry 131...Instruction execution unit (EXU) 132...Operand registers P1 to P3...Path

Claims (1)

[Claims] A memory control unit that controls data transfer to and from the memory;
In a central processing unit that includes an instruction fetching section that controls fetching of an instruction word, and an instruction execution section that executes an operation specified by the instruction word fetched by the instruction fetching section, the instruction word fetched from the memory control section. an immediate operand detection means for detecting whether or not the instruction word includes an immediate operand; The instruction retrieval section includes immediate operand sending means for sending an immediate operand to the memory control section, and when the memory control section receives the immediate operand from the instruction retrieval section, the received immediate operand is sent to the memory control section. An operand supply method characterized in that eight operands are transferred to the instruction execution unit through the same supply path as a memory operand.