JPH0249024B2 - - Google Patents
Info
- Publication number
- JPH0249024B2 JPH0249024B2 JP58137948A JP13794883A JPH0249024B2 JP H0249024 B2 JPH0249024 B2 JP H0249024B2 JP 58137948 A JP58137948 A JP 58137948A JP 13794883 A JP13794883 A JP 13794883A JP H0249024 B2 JPH0249024 B2 JP H0249024B2
- Authority
- JP
- Japan
- Prior art keywords
- latch
- current
- transistor
- bistable device
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000013461 design Methods 0.000 claims description 6
- 238000012360 testing method Methods 0.000 description 12
- 230000000295 complement effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
- H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/445,601 US4535467A (en) | 1982-11-30 | 1982-11-30 | Switch logic for shift register latch pair |
US445601 | 1982-11-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59106130A JPS59106130A (ja) | 1984-06-19 |
JPH0249024B2 true JPH0249024B2 (US07922777-20110412-C00004.png) | 1990-10-26 |
Family
ID=23769539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58137948A Granted JPS59106130A (ja) | 1982-11-30 | 1983-07-29 | レベル・センステイブ・スキヤン・デザインのためのシフト・レジスタ・ラツチ対 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4535467A (US07922777-20110412-C00004.png) |
EP (1) | EP0111056B1 (US07922777-20110412-C00004.png) |
JP (1) | JPS59106130A (US07922777-20110412-C00004.png) |
DE (1) | DE3368771D1 (US07922777-20110412-C00004.png) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0442024U (US07922777-20110412-C00004.png) * | 1990-08-08 | 1992-04-09 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4580137A (en) * | 1983-08-29 | 1986-04-01 | International Business Machines Corporation | LSSD-testable D-type edge-trigger-operable latch with overriding set/reset asynchronous control |
US4628217A (en) * | 1984-03-22 | 1986-12-09 | Sperry Corporation | Fast scan/set testable latch using two levels of series gating with one current source |
JPH0648779B2 (ja) * | 1985-07-18 | 1994-06-22 | 富士通株式会社 | フリップフロップ回路 |
US5299136A (en) * | 1991-06-05 | 1994-03-29 | International Business Machines Corp. | Fully testable DCVS circuits with single-track global wiring |
US5272397A (en) * | 1992-03-27 | 1993-12-21 | International Business Machines Corp. | Basic DCVS circuits with dual function load circuits |
US5475815A (en) * | 1994-04-11 | 1995-12-12 | Unisys Corporation | Built-in-self-test scheme for testing multiple memory elements |
US5612965A (en) * | 1994-04-26 | 1997-03-18 | Unisys Corporation | Multiple memory bit/chip failure detection |
US5666371A (en) * | 1995-02-24 | 1997-09-09 | Unisys Corporation | Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements |
US5701313A (en) * | 1995-02-24 | 1997-12-23 | Unisys Corporation | Method and apparatus for removing soft errors from a memory |
US5784382A (en) * | 1995-03-01 | 1998-07-21 | Unisys Corporation | Method and apparatus for dynamically testing a memory within a computer system |
US5511164A (en) * | 1995-03-01 | 1996-04-23 | Unisys Corporation | Method and apparatus for determining the source and nature of an error within a computer system |
US7000162B2 (en) | 2001-08-08 | 2006-02-14 | International Business Machines Corporation | Integrated circuit phase partitioned power distribution for stress power reduction |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3294919A (en) * | 1963-01-17 | 1966-12-27 | Bell Telephone Labor Inc | Convertible binary counter and shift register with interstage gating means individual to each operating mode |
GB1098979A (en) * | 1965-07-03 | 1968-01-10 | Marconi Co Ltd | Improvements in or relating to high frequency transistor amplifiers |
US3618033A (en) * | 1968-12-26 | 1971-11-02 | Bell Telephone Labor Inc | Transistor shift register using bidirectional gates connected between register stages |
US3953746A (en) * | 1974-07-29 | 1976-04-27 | Honeywell Information Systems, Inc. | Selector latch gate |
DE2740353C2 (de) * | 1977-09-07 | 1982-05-13 | Siemens AG, 1000 Berlin und 8000 München | ECL-kompatibler Registerbaustein mit bipolaren Speicherzellen |
-
1982
- 1982-11-30 US US06/445,601 patent/US4535467A/en not_active Expired - Fee Related
-
1983
- 1983-07-29 JP JP58137948A patent/JPS59106130A/ja active Granted
- 1983-08-31 EP EP83108574A patent/EP0111056B1/en not_active Expired
- 1983-08-31 DE DE8383108574T patent/DE3368771D1/de not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0442024U (US07922777-20110412-C00004.png) * | 1990-08-08 | 1992-04-09 |
Also Published As
Publication number | Publication date |
---|---|
EP0111056A1 (en) | 1984-06-20 |
DE3368771D1 (en) | 1987-02-05 |
JPS59106130A (ja) | 1984-06-19 |
EP0111056B1 (en) | 1986-12-30 |
US4535467A (en) | 1985-08-13 |
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