JPH0247834A - Method of connecting by filling contact window - Google Patents
Method of connecting by filling contact windowInfo
- Publication number
- JPH0247834A JPH0247834A JP1107964A JP10796489A JPH0247834A JP H0247834 A JPH0247834 A JP H0247834A JP 1107964 A JP1107964 A JP 1107964A JP 10796489 A JP10796489 A JP 10796489A JP H0247834 A JPH0247834 A JP H0247834A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal
- connection window
- photoresist
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 30
- 239000002184 metal Substances 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000009413 insulation Methods 0.000 abstract 4
- 238000005520 cutting process Methods 0.000 description 4
- 238000005429 filling process Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体製造工程中のりソグラフイエ程に関し
、特に多層フォトレジスト及びリフトオフ工程を用いる
自己整合接続窓充填に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to photolithographic processes during semiconductor manufacturing processes, and more particularly to self-aligned connection window filling using multilayer photoresists and lift-off processes.
［従来の技術及び発明が解決しようとする課題］半導体
の工程が進行して種々の層とパターンとが形成されるに
つれ、シリコン基板上に自然に階段状部分が生ずる。複
雑な回路を有するＶＬＳＩは非常に多くの工程ステップ
を必要とし、この結果、多層が形成され、表面の屈曲も
甚だしくなる。[Background Art and Problems to be Solved by the Invention] As semiconductor processing progresses and various layers and patterns are formed, stepped portions naturally occur on a silicon substrate. VLSIs with complex circuits require a large number of process steps, resulting in multiple layers and severe surface curvature.
このような場合、フォトマスキングに次のような問題が
生ずる。即ち、露光する光がマスクパターンの周囲に広
がってマスクパターンの大きさが変化させられるという
問題が生ずる。深いところにあるパターンがより影響を
受けることになる。In such a case, the following problems occur in photomasking. That is, a problem arises in that the exposing light spreads around the mask pattern, causing the size of the mask pattern to change. Deeper patterns will be more affected.
また、このような階段状部分は、金属蒸着工程において
も問題を発生させる。金属蒸着工程の主要な目的は、均
一な金属層をウェーハ上に形成することであるが、階段
状部分を有する基板の場合にはそれが困難である。金属
層の均一な蒸着は、電気的伝達と高抵抗とをもたらすの
に必須である。Further, such stepped portions also cause problems in a metal deposition process. The main goal of the metal deposition process is to form a uniform metal layer on the wafer, which is difficult in the case of substrates with stepped portions. Uniform deposition of metal layers is essential to provide electrical conduction and high resistance.
さらに、階段状部分が形成されている層をフォトレジス
トや金属層で覆う場合、切断現象が発生する場合もある
。Furthermore, when covering the layer in which the stepped portion is formed with a photoresist or metal layer, a cutting phenomenon may occur.
これを従来の接続窓形成及び充填工程を図示した第１図
に従って説明すると、次の通りである。This will be explained with reference to FIG. 1, which illustrates the conventional connection window forming and filling process.
第１図（Ａ）に図示したように、導電層１．２゜３及び
絶縁層４．５上に絶縁層６を形成する際、階段状部分が
形成される。即ち、導電層１ならびに導電層２及び導電
層３上の絶縁層６の厚さが異なっているので、その上に
付着させられるフォトレジスタ層７の厚さに差異が生ず
るようになる。As shown in FIG. 1A, when forming the insulating layer 6 on the conductive layer 1.2.3 and the insulating layer 4.5, a stepped portion is formed. That is, since the thicknesses of the conductive layer 1 and the insulating layer 6 on the conductive layer 2 and the conductive layer 3 are different, there will be a difference in the thickness of the photoresist layer 7 deposited thereon.
ここで、露光すると、階段状部分によるフォトレジスト
層７の厚さの差異によって接続窓パターンｗ、、ｗ２
、ｗ３の大きさに差異が発生する。即ち、接続窓パター
ンＷ３が形成しようとする所望の大きさとすると、接続
窓パターンｗ、ｗ２は、接続窓パターンＷ３よりそれぞ
れ大及び小となり、均一な接続窓パターンが形成されな
い。フォトレジスタ層７をマスクとして使用したエツチ
ング工程後にフォトレジスト層７を除去すると、前記絶
縁層６の厚さｔｌ、ｔ２．ｔ３の差に起因する、接続窓
ｗ３ 、ｗ５ 、Ｗｅの大きさの間の差異も発生する（
第１図（Ｂ）参照）。Here, when exposed to light, connection window patterns w, , w2 are formed due to differences in the thickness of the photoresist layer 7 due to the stepped portions.
, w3. That is, if the connection window pattern W3 has the desired size, the connection window patterns w and w2 will be larger and smaller than the connection window pattern W3, respectively, and a uniform connection window pattern will not be formed. When the photoresist layer 7 is removed after an etching process using the photoresist layer 7 as a mask, the thicknesses tl, t2 . Differences between the sizes of the connection windows w3, w5, We due to the difference in t3 also occur (
(See Figure 1 (B)).
次の工程において、もし金属８が付着させられると、形
成された接続窓の縦横比が異なるので、第１図（Ｃ）に
図示のように、部分９では切断現象が発生すると共に部
分１０では厚過ぎる層が形成され、もって均一な金属層
が形成されない。In the next step, if the metal 8 is deposited, the aspect ratio of the formed connection window is different, so that a cutting phenomenon occurs in the part 9 and in the part 10, as shown in FIG. 1(C). A layer that is too thick is formed and therefore a uniform metal layer is not formed.
本発明は、このような点に鑑みてなされたもので、本発
明の目的は、リソグラフィ工程で多層フォトレジスト工
程を使用する、接続窓を形成する方法であって、リソグ
ラフィ工程後の大きさの変化が最小化されるものを提供
することにある。The present invention has been made in view of these points, and an object of the present invention is to provide a method for forming a connection window using a multilayer photoresist process in a lithography process, which reduces the size of the connection window after the lithography process. The goal is to provide something that minimizes change.
本発明の他の目的は、自己整合接続窓充填工程を使用し
たリフトオフ工程を使用することによってリソグラフィ
工程におる誤整合問題を解決することにある。Another object of the present invention is to solve the misalignment problem in the lithography process by using a lift-off process using a self-aligned connection window filling process.
本発明のさらに他の目的は、接続窓に予め金属を形成す
ることにより、接続窓の縦横比の変化に起因する金属の
切断現象を根本的に解決することにある。Still another object of the present invention is to fundamentally solve the phenomenon of metal cutting caused by changes in the aspect ratio of the connection window by forming metal on the connection window in advance.
［課題を解決するための手段］
上記目的を達成するため、本発明によれば、接続窓を充
填して接続する方法であって、階段状部分が形成されて
いる絶縁層の上に平坦化層及び中間層を形成する工程と
、前記中間層の上にフォトレジストを用いて接続窓のパ
ターンを形成する工程と、前記接続窓のパターンに従っ
て前記中間層と前記平坦化層とをエツチングする工程と
、前記平坦化層と前記中間層と前記フォトレジスト層と
をマスクとして使用して前記絶縁層中に接続窓の部分を
エツチングする工程と、前記フォトレジスト層を一定の
厚さだけ除去する工程と、一部が除去された前記フォト
レジスタ層をマスクとして使用して前記平坦化層をアン
ダカットした後、前記一部が除去されたフォトレジスト
層を除去する工程と、前記接続窓及び前記中間層の上に
金属を多重に付着させる工程と、前記平坦化層と前記中
間層と前記中間層上の前記金属とをリフトオフ方法で除
去する工程と、前記絶縁層の上と金属が充填されている
前記接続窓の上とに金属を付着させて前記接続窓と付着
させられた前記金属とを接続する工程と、を具備する方
法が提供される。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for connecting by filling a connection window, in which flattening is performed on an insulating layer in which a stepped portion is formed. forming a connection window pattern using photoresist on the intermediate layer; and etching the intermediate layer and the planarization layer according to the connection window pattern. etching a portion of the connection window in the insulating layer using the planarization layer, the intermediate layer, and the photoresist layer as a mask; and removing the photoresist layer by a certain thickness. using the partially removed photoresist layer as a mask to undercut the planarization layer, and then removing the partially removed photoresist layer; a step of depositing metal in multiple layers on the layer; a step of removing the planarization layer, the intermediate layer, and the metal on the intermediate layer by a lift-off method; and filling the top of the insulating layer with metal. depositing metal on top of the connection window to connect the connection window and the deposited metal.
［実 施 例］
以下、添付図面を参照して本発明の一実施例について説
明する。[Example] Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.
第２図（Ａ）に図示したように、階段状部分が形成され
ている絶縁層６上に、フォトレジストを用いて平坦化層
１１を形成する。さらに平坦化層１１のマスクとして利
用され、且つ後述するように、優れた選択性を得るため
に利用される。このように平坦化層１１と中間層１２と
を形成するこにより、中間層１２上に均一なマスクパタ
ーンが形成され、もって均一な接続窓パターン及び接続
窓を作ることができる。As shown in FIG. 2A, a planarization layer 11 is formed using photoresist on the insulating layer 6 in which the stepped portion is formed. Furthermore, it is used as a mask for the planarization layer 11 and, as will be described later, is used to obtain excellent selectivity. By forming the planarization layer 11 and the intermediate layer 12 in this manner, a uniform mask pattern is formed on the intermediate layer 12, thereby making it possible to create uniform connection window patterns and connection windows.
次に、フォトレジスト層１３を形成した後、第２図（Ｂ
）に図示したような接続窓パターンを形成し、そのパー
タンに従って中間層１２と平坦化層１１とをエツチング
すると、第２図（Ｃ）に図示したようになる。平坦化層
１１と中間層１２とフォトレジスト層１３とをマスクと
して使用し、第２図（Ｄ）に図示するように、絶縁層６
中の接続窓部分をエツチングし、そしてフォトレジスト
層１３を適切な厚さにエツチングする。Next, after forming the photoresist layer 13, as shown in FIG.
) is formed, and the intermediate layer 12 and planarization layer 11 are etched according to the pattern, resulting in a pattern as shown in FIG. 2(C). Using the planarization layer 11, intermediate layer 12, and photoresist layer 13 as a mask, the insulating layer 6 is formed as shown in FIG. 2(D).
The inner connection window portion is etched, and the photoresist layer 13 is etched to the appropriate thickness.
ここで、フォトレジスト層１３を残す理由は、平坦化層
１１と中間層１２とをエツチングした後にもフォトレジ
スト層１３が残っていることによって平坦化層１２上に
再びフォトレジスト層を形成する必要がなくなり、そし
て中間層１２をオーバハングとして利用することによっ
て優れた選択性を得ることができるからである。即ち、
第２図（Ｄ）以後にも平坦化層１１は、同一の厚さを継
続して維持し、もって均一な接続窓パターンと接続窓と
を形成し、そしてきれいな接続窓充填を行うことができ
る。Here, the reason why the photoresist layer 13 is left is that the photoresist layer 13 remains even after the planarization layer 11 and the intermediate layer 12 are etched, so that it is necessary to form a photoresist layer again on the planarization layer 12. This is because excellent selectivity can be obtained by using the intermediate layer 12 as an overhang. That is,
Even after FIG. 2(D), the planarization layer 11 continues to maintain the same thickness, thereby forming a uniform connection window pattern and connection windows, and making it possible to cleanly fill the connection windows. .
従って、その工程の間、フォトレジスト＠１３を残すこ
とによって新しいフォトレジスト層を形成する必要がな
く、それによって自己整合接続窓充填工程が得られ、誤
整ぎ問題が解決される。また、フォトレジスト層１３を
適切な厚さだけエツチングする理由は、第２図（Ｅ）に
図示したように、反応性イオンエツチング工程を使用し
て平坦化層１１の所望のアンダカットを形成するためで
ある。Therefore, there is no need to form a new photoresist layer by leaving the photoresist@13 during the process, thereby providing a self-aligned connection window filling process and solving the misalignment problem. Also, the reason for etching the photoresist layer 13 to an appropriate thickness is to form the desired undercuts in the planarization layer 11 using a reactive ion etching process, as illustrated in FIG. 2(E). It's for a reason.
絶縁層６中の接続窓部分をエツチングした後、反応性イ
オンエツチング工程を使用して平坦化層１１のアンダカ
ットを実行し、フォトレジスト層１３を除去すると第２
図（Ｅ）のようになる。ここで、中間層１２はアンダカ
ットされた平坦化層１１に対するオーバハングとして作
用する。従って、第２図（Ｆ＞に図示したように、金属
１４を付着させた後にリフトオフ工程によって平坦化層
１１と中間層１２と中間層上の金属１４とを除去する際
、第２図（Ｇ）における絶縁層６上の接続窓に隣接した
部分から金属が完全には除去されないで残るという現象
を除去することができるので優れた選択性を得ることが
できる。After etching the connection window portion in the insulating layer 6, undercutting of the planarization layer 11 is performed using a reactive ion etching process and the photoresist layer 13 is removed.
The result will be as shown in Figure (E). Here, the intermediate layer 12 acts as an overhang to the undercut planarization layer 11. Therefore, as shown in FIG. 2(F), when removing the planarization layer 11, the intermediate layer 12, and the metal 14 on the intermediate layer by a lift-off process after depositing the metal 14, as shown in FIG. ), it is possible to eliminate the phenomenon in which metal is not completely removed and remains from the portion adjacent to the connection window on the insulating layer 6, and thus excellent selectivity can be obtained.
第２図（Ｆ）に図示した次の工程において、接続窓及び
中間層１２上に金属１４を多重に付着させた後、平坦化
層１１と中間層１２と中間層上の金属１４とをリフトオ
フ工程で除去すると、第２図（Ｇ）のようになる。この
パターン上に金属１５を付着させると、第２図（Ｈ）に
図示したように優れた接続が形成される。In the next step illustrated in FIG. 2(F), after depositing the metal 14 in multiple layers on the connection window and the intermediate layer 12, the planarization layer 11, the intermediate layer 12, and the metal 14 on the intermediate layer are lifted off. When removed in the process, the result is as shown in FIG. 2 (G). Depositing metal 15 over this pattern forms an excellent connection as illustrated in FIG. 2(H).
ここで、従来では接続窓と絶縁層６における金属付着を
同時に行うが（第１図（Ｃ）参照）、本発明では接続窓
中に予め金属を付着させた後、（第２図（Ｇ）参照）、
再び金属を付着させることにより（第２図（Ｈ）参照）
、切断現象の防止及び均一な接続がなされ得る。Here, conventionally, the metal is deposited on the connection window and the insulating layer 6 at the same time (see FIG. 1(C)), but in the present invention, after the metal is deposited in the connection window in advance (see FIG. 2(G)). reference),
By attaching metal again (see Figure 2 (H))
, disconnection phenomenon can be prevented and uniform connection can be achieved.
［発明の効果］
以上のように、本発明によれば、従来技術における問題
点であった接続窓の縦横比の差による金属接続の切断現
象が多層フォトレジスト及び自己整合接続窓充填を用い
たリフトオフ工程を使用することにより、根本的に解決
される。即ち、均一な接続窓パターン及び接続窓を形成
することによって確実な金属間の接続が達成される。従
って、半導体装置の収率及び性能が向上し、且つ製造コ
ストの面でも有利になる。[Effects of the Invention] As described above, according to the present invention, the phenomenon of disconnection of metal connections due to the difference in the aspect ratio of the connection windows, which was a problem in the prior art, can be solved by using a multilayer photoresist and self-aligned connection window filling. This is fundamentally solved by using a lift-off process. That is, reliable metal-to-metal connections are achieved by forming uniform connection window patterns and connection windows. Therefore, the yield and performance of the semiconductor device are improved, and it is also advantageous in terms of manufacturing cost.
本発明に従って接続窓だけに予め金属を充填し、その後
、再び金属を付着させることによって金属の切断現象を
根本的に解決し、且つ金属と金属との間の均一な接続を
維持する方法は、上記実施例だけに限定さるものではな
い。According to the present invention, a method for fundamentally solving the metal cutting phenomenon and maintaining a uniform connection between metals by pre-filling only the connection window with metal and then re-attaching the metal is as follows: The invention is not limited to the above embodiments.
例えば、本発明では、階段状部分を有する絶縁層に接続
窓を形成する前に平坦化層及び中間層を付着させて均一
な接続窓を形成し、もって金属を接続する。しかしなが
ら、階段状部分を有する絶縁層を平坦化させずに形成さ
れた接続窓と絶縁層の上に同時に金属を付着させる従来
の方法に本発明による金属の付着方法を適用することが
できるということが、当業者には理解されよう。For example, in the present invention, prior to forming connection windows in an insulating layer having stepped portions, a planarization layer and an intermediate layer are deposited to form uniform connection windows to connect metals. However, the metal deposition method according to the present invention can be applied to the conventional method of simultaneously depositing metal on a connection window and an insulating layer formed without flattening an insulating layer having a stepped portion. However, it will be understood by those skilled in the art.
第１図は接続窓を形成して接続する従来の工程を説明す
るための断面図、および
第２図は接続窓を形成して充填する本発明の詳細な説明
するための断面図である。
１．２．３・・・導電層
４．５．６・・・絶縁層
７．１３・・・フォトレジスト層
１１・・・平坦化層
１２・・・中間層
８．１４．１５・・・金属
ＦＩＧ 、１
Ｗ１Ｗ２ Ｗ３
μｍ−ドーー −−Ｈ
ＦＩＧ、２
←９←FIG. 1 is a sectional view illustrating a conventional process of forming and connecting connection windows, and FIG. 2 is a sectional view illustrating details of the present invention for forming and filling connection windows. 1.2.3... Conductive layer 4.5.6... Insulating layer 7.13... Photoresist layer 11... Flattening layer 12... Intermediate layer 8.14.15... Metal FIG, 1 W1W2 W3 μm-do--H FIG, 2 ←9←
Claims (3)
部分が形成されている絶縁層の上に平坦化層及び中間層
を形成する工程と、 前記中間層の上にフォトレジストを用いて接続窓のパタ
ーンを形成する工程と、 前記接続窓のパターンに従って前記中間層と前記平坦化
層とをエッチングする工程と、 前記平坦化層と前記中間層と前記フォトレジスト層とを
マスクとして使用して前記絶縁層中に接続窓の部分をエ
ッチングする工程と、 前記フォトレジスト層を一定の厚さだけ除去する工程と
、 一部が除去された前記フォトレジスタ層をマスクとして
使用して前記平坦化層をアンダカットした後、前記一部
が除去されたフォトレジスト層を除去する工程と、 前記接続窓及び前記中間層の上に金属を多重に付着させ
る工程と、 前記平坦化層と前記中間層と前記中間層上の前記金属と
をソフトオフ方法で除去する工程と、前記絶縁層の上と
金属が充填されている前記接続窓の上とに金属を付着さ
せて前記接続窓と付着させられた前記金属とを接続する
工程と、 を具備する方法。(1) A method for connecting by filling a connection window, which includes the steps of forming a flattening layer and an intermediate layer on an insulating layer in which a stepped portion is formed, and applying a photoresist on the intermediate layer. etching the intermediate layer and the planarization layer according to the pattern of the connection window; using the planarization layer, the intermediate layer, and the photoresist layer as a mask; etching a portion of the connection window in the insulating layer using the photoresist layer; removing the photoresist layer by a certain thickness; and using the partially removed photoresist layer as a mask to perform the etching process. removing the partially removed photoresist layer after undercutting the planarization layer; depositing metal in multiple layers on the connection window and the intermediate layer; removing the intermediate layer and the metal on the intermediate layer by a soft-off method, and depositing metal on the insulating layer and on the connection window filled with metal to adhere to the connection window. A method comprising the steps of: connecting the metal that has been oxidized.
絶縁層を除去する前に平坦化層及び中間層を形成するこ
とによって前記中間層の上に均一なマスクパターンを形
成し、もって均一な接続窓のパターン及び接続窓を形成
する請求項１記載の方法。(2) forming a uniform mask pattern on the intermediate layer by forming a flattening layer and an intermediate layer on the insulating layer in which the stepped portion is formed before removing the insulating layer; 2. The method of claim 1, further comprising forming a uniform connection window pattern and connection windows.
化層と前記絶縁層とを除去する工程の間、継続して維持
させることによって自己整合接続窓充填工程を用いる請
求項１記載の方法。3. The method of claim 1 using a self-aligned connection window filling step by maintaining the photoresist layer continuously during the steps of removing the intermediate layer, the planarization layer, and the insulating layer. .
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR88-9156 | 1988-07-21 | ||
| KR1019880009156A KR910006744B1 (en) | 1988-07-21 | 1988-07-21 | Semiconductor contact window filling - up method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0247834A true JPH0247834A (en) | 1990-02-16 |
Family
ID=19276284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1107964A Pending JPH0247834A (en) | 1988-07-21 | 1989-04-28 | Method of connecting by filling contact window |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0247834A (en) |
| KR (1) | KR910006744B1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS633437A (en) * | 1986-06-23 | 1988-01-08 | Sony Corp | Manufacture of semiconductor device |
| JPS6390838A (en) * | 1986-09-30 | 1988-04-21 | ナームローゼ フェンノートチャップ フィリップス グロエイラムペンファブリーケン | Manufacture of electrical mutual connection |
-
1988
- 1988-07-21 KR KR1019880009156A patent/KR910006744B1/en not_active IP Right Cessation
-
1989
- 1989-04-28 JP JP1107964A patent/JPH0247834A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS633437A (en) * | 1986-06-23 | 1988-01-08 | Sony Corp | Manufacture of semiconductor device |
| JPS6390838A (en) * | 1986-09-30 | 1988-04-21 | ナームローゼ フェンノートチャップ フィリップス グロエイラムペンファブリーケン | Manufacture of electrical mutual connection |
Also Published As
| Publication number | Publication date |
|---|---|
| KR900002418A (en) | 1990-02-28 |
| KR910006744B1 (en) | 1991-09-02 |
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