JPH0246076A - Video signal processor - Google Patents

Abstract

PURPOSE:To make the part except a slave screen into a prescribed color by responding to a switching command signal when a master screen signal detection signal shows the absence of a master screen signal and outputting a composite video signal containing a picture corresponding a reduced screen data group. CONSTITUTION:In case a master screen signal (a) does not exists, when a master screen signal detection signal DET outputted from a master screen signal detector 25 becomes high-level, horizontal and vertical synchronizing signals H(b) and V(b) separated from a slave screen signal (b) are outputted from a synchronization switching/generating circuit 15 as reading synchronizing signals H(R) and V(R) by a control signal CONT outputted from a memory controller 8. Only the video signal of a digital system, namely, a reduced screen signal corresponding to the reduced screen data converted from a screen data group stored in a memory 9 is selectively outputted. Thus, the part except the reduced screen signal part of the composite video signal outputted from a change-over switch 4 becomes a black level signal.

Description

TECHNICAL FIELD The present invention relates to a video signal processing device, and more particularly to a video signal processing device having a screen composition function.

Background Art Video signal processing that handles multiple video signals, provides a two-dimensionally reduced screen within one screen, and has a screen compositing function that simultaneously displays two images from two composite video signals on a single screen. An example of the device is shown in FIG.

In FIG. 5, two video input terminals IN, IN2
The input composite video signals v1 and v2 supplied to the switch 1 are supplied to the changeover switch 1. The changeover switch 1 selects two input composite video signals v1 and v in response to a changeover command signal VSEL.
2 is output as the main screen signal a, and the other of the two input composite video signals Vl and V2 is output as the child screen signal. The child screen signal a is supplied to the Y/C separation circuit 2 and the synchronization separation circuit 3, and the main screen signal a is supplied to one input terminal of the changeover switch 4 and the synchronization separation circuit 5.

In the Y/C separation circuit 2, a luminance signal Y and a color signal C are separated from the small screen signal. The luminance signal Y is supplied to an analog-to-digital (hereinafter referred to as A/D) converter 6 and a chroma decoder 7. Further, the color signal C is supplied only to the chroma decoder 7.

The A/D converter 6 is supplied with a write timing pulse W1 of a predetermined frequency from the memory controller 8. In this A/D converter 6, the luminance signal Y is sampled by the write timing pulse Wl, and digital data is generated according to the obtained sample value. The output data of this A/Di converter 6 is stored in a memory 9.
supplied to

Further, in the chroma decoder 7, the color signal C is demodulated to generate a color difference signal R-YSB-Y. These color difference signals R-Y and B-Y are supplied to a multiplexer 10. The multiplexer 10 outputs the color difference signal RY according to the write timing pulse W2 from the memory controller 8.

It is configured to alternately output B-Y at predetermined intervals. The color difference signals R-Y and B-Y alternately output from the multiplexer 10 are supplied to an A/D converter 11. The A/D converter 11 receives a write timing pulse w3 from the memory controller 8 in the same way as the A/D converter 6.
is supplied. In the A/D converter 11, the color difference signals R-Y and B-Y that are alternately outputted by the write timing pulse W3 are sequentially sampled, and digital data is generated according to the obtained sample values. The output data of this A/D converter 11 is supplied to the memory 9.

On the other hand, in the synchronization separation circuit 3, horizontal and vertical synchronization signals H(b) and V(b) are separated from the small screen signal.

Further, in the synchronization separation circuit 5, horizontal and vertical synchronization signals a) and V(a) are separated from the main screen signal a and supplied to the synchronization switching/generation circuit 15.

The synchronization switching/generation circuit 15 outputs the output of the synchronization separation circuit 3 as horizontal and vertical synchronization signals n(W) and V(W) for writing according to the control signal C0NT from the memory controller 8, and The configuration is such that the outputs are outputted as horizontal and vertical synchronizing signals H (1?) and V (1?) for reading. This synchronous switching/generation circuit 1
The write and read synchronization signals (W), V(W), H(R), and V(R) outputted from the memory controller 8 are supplied to the memory controller 8. Memory controller 8
generates write timing pulses w1 to w4 using write synchronization signals H(W) and V(W), and generates read timing pulses "1 to r4" using read synchronization signals H(R) and V(R). It is configured to generate 3 samples in horizontal sampling of the screen performed by the A/D converter 6.11, for example, depending on the generation timing of the write timing pulse WI-W4 and the read timing pulse WI-W4 and the read timing pulse ``1~r4. 2 of them
Samples are thinned out, and in vertical sampling, samples of 2 out of 3 scan lines are thinned out to make the screen 1
A reduction process is performed to reduce the size to /9.

The write timing pulse W4 is supplied to the memory 8,
Luminance data and color data output from each of the A/D converters 6.10 are sequentially written into the memory 9. At the same time, a read timing pulse r1 is supplied to the memory 9, and the data written in the memory 9 is sequentially read out.

The brightness data and color data read from the memory 9 are
It is supplied to digital-to-analog (hereinafter referred to as D/A) converters 16 and 17. These D/A converters 16.1
7, an analog signal having an instantaneous level corresponding to the input data is formed by read timing pulses r2 and r3, and a luminance signal Y is output from the D/A converter 16.
The D/A converter 17 outputs color difference signals RY and BY alternately at predetermined intervals. The output of the D/A converter 16 is supplied to a chroma encoder 18. Further, the output of the D/A converter 17 is supplied to a demultiplexer 19, and the color difference signals RY and BY are separated from each other by a read timing pulse r4 and then supplied to a chroma encoder 18. chroma encoder 1
8 receives a blanking signal 13 from the memory controller 8.
L is supplied. When the blanking signal 13L is absent, the chroma encoder 18 modulates the color subcarrier with the color difference signals R-Y and B-Y to form a color signal, and then combines it with the luminance signal and outputs the blanking signal. B
When L is present, a black level signal is output. The output of this chroma encoder 18 is supplied to an adder 20, to which a synchronization signal output from the synchronization switching/generation circuit 15 is added, and the sub-screen signal is converted from a screen data group stored in the memory 9. This results in a composite video signal including a reduced screen signal corresponding to the reduced screen data.

The synchronization switching/generation circuit 15 receives the main screen signal a by analog horizontal and vertical synchronization signals, that is, the synchronization separation circuit 5.
adder 2 by the horizontal and vertical synchronization signals separated from
is configured to generate a synchronization signal to be supplied to

The output of the adder 20 is supplied to the other input terminal of the changeover switch 4. A control input terminal of the changeover switch 4 is supplied with a changeover control signal ^/D SEL from the memory controller 8 . For example, when the switching control signal A/D SEL is at a high level, the changeover switch 4 selectively outputs a digital video signal, that is, the output of the adder 20, and when the switching control signal A/D SEL is at a low level, it selectively outputs the output. It is configured to selectively output an analog video signal, that is, a main screen signal a directly supplied from the changeover switch 1.

The memory controller 8 receives a switching control signal A/D SEL and a blanking signal BL as shown in FIGS. 6 and 7.
is configured to output. In other words, Fig. 6 (
When the vertical synchronizing signal V(R) for reading as shown in A) is supplied, the switching control signal A/D SEL is set as shown in FIG. The level is high only in

Further, the blanking signal BL becomes high level in synchronization with the horizontal and vertical synchronizing signals for reading, as shown in FIG. 3(C). FIG. 7 is an enlarged diagram of each signal waveform. Horizontal synchronizing signal H(R) for reading as shown in FIG. 7(A)
), the switching control signal A/D SEL becomes high level only during period E within one horizontal scanning period (IH) as shown in FIG. Also, blanking signal B
Then, as shown in FIG. 3(C), it becomes high level in synchronization with the horizontal synchronizing signal +1 (R) for reading.

Therefore, a screen as shown in FIG. 8 is formed by the video signal output from the changeover switch 4, and a digital video signal, i.e., a sub-screen signal, is formed on the main screen Pa by the main screen signal a, which is an analog video signal. A child screen pb based on a reduced screen signal corresponding to reduced screen data converted from the converted screen data group stored in the memory 9
are synthesized.

In the conventional video signal processing device as described above, when the main screen signal a does not exist, there is no vertical synchronization signal in the video signal output from the changeover switch 4.
The image will be distorted.

Moreover, at the same time, the synchronization signal for reading is not output from the synchronization switching/generation circuit 15, and the timing of read timing pulses "1 to "4 output from the memory controller 8 is different from vCO of the PLL circuit in the memory controller 8, for example. There is a problem in that the timing is synchronized with the output pulse of the free-running frequency, the position of the sub-screen is not stable, and the reproduced image becomes extremely unsightly.

Therefore, when the video signal that becomes the main screen is not supplied, it may be possible to provide a circuit that generates a video signal or synchronization signal in place of the video signal that becomes the main screen, but this would increase the circuit scale. Therefore, a problem arises in that the manufacturing cost increases.

Summary of the Invention The present invention has been made in view of the above points, and includes:
It is an object of the present invention to provide a video signal processing device capable of forming a stable child screen even when a composite video signal forming a main screen does not exist.

In order to achieve the above object, the video signal processing device according to the present invention is provided with a detection means for generating a main screen signal detection signal indicating the presence or absence of a main screen signal, and detects the sub screen signal in the sub screen area on the main screen. The screen signal conversion means that converts the reduced screen signal into a reduced screen signal and outputs it together with the switching command signal includes a first conversion means that converts the child screen signal into a screen data group, a storage device that stores the screen data group, and a main screen signal detection signal. When indicates the presence of the main screen signal, the screen data group in the storage means is converted into a reduced screen data group in the sub-screen area on the main screen by the synchronization signal in the main screen signal, and the converted screen data group is output together with the switching command signal. a second converting means for converting the screen data group in the storage means into a reduced screen data group using the synchronization signal in the child screen signal and outputting the reduced screen data group together with the switching command signal when the main screen signal detection signal indicates the absence of the main screen signal; , and a screen signal forming means for forming a reduced screen signal corresponding to the second group of reduced screen data, and the signal selection means selects the screen signal forming means when the main screen detection signal indicates the absence of the main screen signal. The configuration is configured to selectively output only the output of .

Further, the screen signal forming means is configured to output a composite video signal including an image corresponding to the reduced screen data group in response to the switching command signal when the main screen signal detection signal indicates the absence of the main screen signal. By doing so, it is possible to make the parts other than the child screen a predetermined color, which is preferable.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4.

As shown in FIG. 1, a changeover switch 1.4, a Y/C separation circuit 2, a synchronous separation circuit 3.5, an A/D converter 6.11, a chroma decoder 7, a memory controller 8, a memory 9, a multiplexer 10, The synchronous switching/generating circuit 15, D/A converters 16, 17, chroma encoder 18, demultiplexer 19, and adder 20 are connected in the same way as in the device shown in FIG. However, in this example, the vertical synchronization signal V(a) output from the synchronization separation circuit 5 and supplied to the synchronization switching/generation circuit 15 is further supplied to the main screen signal detector 25. The main screen signal detector 25 detects the vertical synchronization signal V
(a) is low level when vertical synchronization signal V(a) is present, and high level when vertical synchronization signal V(a) is not present to generate a master screen signal detection signal DET indicating the presence or absence of master screen signal a. . This detection signal DET is supplied to the memory controller 8 and also serves as the sole power of an OR (logical sum) gate 26 and an AND (logical product) gate 27.

When the detection signal DOT becomes high level, the memory controller 8 outputs the horizontal and vertical synchronization signals a) and V(a) separated from the child screen signal a by the synchronization separation circuit 5 as read synchronization signals. Control signal C0NT
is configured to send the signal to the synchronous switching/generation circuit 15.

A switching control signal A/D SEL output from the memory controller 8 is supplied to the OR gate 26 as an input signal. The output of this OR gate 26 serves as a control input for the changeover switch 4. The AND gate 27 also receives a switching control signal ^/D output from the memory controller 8.
SEL is supplied as external power via an inverter 28. The high level signal output from this AND gate 27 is passed through an OR gate 29 to a blanking signal r3.
Together with L, the blanking signal BL'' is supplied to the chroma encoder 18.

In the above configuration, when the main screen signal a exists,
The output of the main screen signal detector 25 becomes low level. Then, the output of the AND gate 27 is always at a low level because the output of the AND gate 27 is at a low level. Therefore, only the blanking signal BL output from the memory controller 8 is supplied to the chroma encoder 18 via the OR gate 29. In addition, the switching control signal A/
D SEL is connected to the selector switch 4 via the OR gate 26.
Since the images are supplied to the screen, screen composition is performed in the same way as in the apparatus shown in FIG.

Next, when the main screen signal a does not exist, the main screen signal detection signal DET output from the main screen signal detector 25 becomes high level. Then, the horizontal and vertical synchronization signals +1(b) and V(b) separated from the small screen signal from the synchronization switching/generation circuit 15 are converted to the readout synchronization signal H( R) and V (R). Then,
In the memory controller 8, read timing pulses r1 to "4" are generated by the horizontal and vertical synchronizing signals H(b) and V(b). Also, the main screen signal detection signal D
Since the ET is supplied to the changeover switch 4 via the OR gate 26, the changeover switch 4 outputs a digital video signal, that is, a reduced screen corresponding to the reduced screen data converted from the screen data group stored in the memory 9. Only the signal will be selectively output.

In addition, since the main screen signal detection signal DET is further supplied to the AND gate 27, the output of the AND gate 27 is sent from the memory controller 8 to the switching control signal A/D S.
When EL is output, it becomes a high level, and a blanking signal IIL° is supplied to the chroma encoder 18. As a result, the vertical synchronizing signal V(R) for reading is supplied to the memory controller 8 as shown in FIG. 2(A), and the switching command signal A/D SEL and blanking signal BL are The blanking signal BL' supplied to the chroma encoder 18 is output as shown in FIG. 5(C) in the same manner as in the device shown in FIG. 5, but the blanking signal BL' is as shown in FIG. 5(D). In addition, as shown in FIG.
The switching command signal A/D SEL and the blanking signal r3L are output in the same way as the device in FIG. 5, as shown in FIG. 5(B) and FIG. The resulting blanking signal BL' is as shown in FIG.

Then, the part of the composite video signal output from the changeover switch 4 excluding the reduced screen signal part becomes a black level signal, so the sub-screen pb is inserted into the main screen Pa consisting of a black screen as shown in FIG. A screen will be created.

In the above embodiment, the detection means for detecting the main screen signal a is configured to detect based on the presence or absence of a vertical synchronization signal, but the detection means may also be configured to detect based on the presence or absence of a horizontal synchronization signal. good. Further, in the above embodiment, the blanking signal BL" is supplied to the chroma encoder 18, and the portion of the video signal output from the changeover switch 4 other than the reduced screen signal portion is set to black level, and the portion other than the child screen is set to a black screen. However, the parts other than the reduced screen signal part of the composite video signal output from the changeover switch 4 may be fixed at any level other than the black level (or the color of the parts other than the sub-screen). It may become.

Effects of the Invention As detailed above, the video signal processing device according to the present invention is provided with a detection means for generating a main screen signal detection signal indicating the presence or absence of a main screen signal, and detects the sub screen signal within the sub screen area on the main screen. The screen signal converting means converts the reduced screen signal into a reduced screen signal and outputs it together with the switching command signal, the first converting means converting the child screen signal into a screen data group, the storage means storing the screen data group, and the main screen signal detection means. When the signal indicates the presence of the main screen signal, the synchronization signal in the main screen signal converts the screen data group in the storage means into a reduced screen data group in the child screen area on the main screen, and outputs it together with the switching command signal. On the other hand, when the main screen signal detection signal indicates the absence of the main screen signal, the second converting means converts the screen data group in the storage means into a reduced screen data group using the synchronization signal in the child screen signal and outputs the reduced screen data group together with the switching command signal. and a screen signal forming means for forming a reduced screen signal corresponding to the reduced screen data group, and the signal selection means selects the screen signal forming means when the main screen detection signal indicates the absence of the main screen signal. Since the configuration is such that only the output of the main screen signal is selectively output, even when the video signal as the main screen signal is not supplied, there is no need to install a separate circuit to generate a signal to replace the main screen signal. can form a reduced screen signal,
A stable child screen can be obtained with a simple configuration.

Further, the screen signal forming means is configured to output a composite video signal including an image corresponding to the reduced screen data group in response to the switching command signal when the main screen signal detection signal indicates the absence of the main screen signal. By doing so, it is possible to make the parts other than the child screen a predetermined color, which is preferable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams showing the operation of each part of the device shown in FIG. 1, and FIG. FIG. 5 is a block diagram showing a conventional video signal processing device. FIGS. 6 and 7 are waveform diagrams showing the operation of each part of the device in FIG. 5. FIG. 8 is a diagram showing the screen obtained. 5 is a diagram showing a screen obtained by the apparatus of FIG. 5; FIG. Explanation of symbols of main parts 4...Selector switch 8...Memory controller 9...Memory 25...Main screen signal detector Applicant: Pioneer Corporation

Claims (2)

[Claims] (1) at least two video input terminals, a relay means for relaying the composite video signals supplied to each of the two video input terminals as a main screen signal and a child screen signal, respectively, and transmitting the child screen signal onto the main screen. screen signal converting means for converting into a reduced screen signal in a child screen area and outputting it together with a switching command signal; and selecting one of the main screen signal and the output of the screen signal converting means in accordance with the switching command signal. a signal selection means for outputting a signal to perform screen synthesis, the video signal processing device comprising a detection means for generating a main screen signal detection signal indicating the presence or absence of the main screen signal, the screen signal converting means , a first converting means for converting the child screen signal into a screen data group, a storage means for storing the screen data group, and when the main screen signal detection signal indicates the presence of the main screen signal, the main screen signal The screen data group in the storage means is converted into a reduced screen data group in the child screen area on the main screen by the synchronization signal in the main screen, and is output together with the switching command signal, while the main screen signal detection signal is output from the main screen signal. a second converting means for converting the screen data group of the storage means into the reduced screen data group and outputting the reduced screen data group together with the switching command signal using a synchronization signal in the small screen signal; a screen signal forming means for forming a reduced screen signal corresponding to a group, and the signal selection means selects only the output of the screen signal forming means when the main screen detection signal indicates the absence of the main screen signal. A video signal processing device characterized by selectively outputting. (2) The screen signal forming means generates a composite video signal including an image corresponding to the reduced screen data group in response to the switching command signal when the main screen signal detection signal indicates the absence of the main screen signal. The video signal processing device according to claim 1, wherein the video signal processing device outputs the following.