JPH0246062Y2 - - Google Patents

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Publication number
JPH0246062Y2
JPH0246062Y2 JP1985136894U JP13689485U JPH0246062Y2 JP H0246062 Y2 JPH0246062 Y2 JP H0246062Y2 JP 1985136894 U JP1985136894 U JP 1985136894U JP 13689485 U JP13689485 U JP 13689485U JP H0246062 Y2 JPH0246062 Y2 JP H0246062Y2
Authority
JP
Japan
Prior art keywords
base material
printed wiring
conductor
wiring board
porous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1985136894U
Other languages
Japanese (ja)
Other versions
JPS6245863U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985136894U priority Critical patent/JPH0246062Y2/ja
Publication of JPS6245863U publication Critical patent/JPS6245863U/ja
Application granted granted Critical
Publication of JPH0246062Y2 publication Critical patent/JPH0246062Y2/ja
Expired legal-status Critical Current

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  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【考案の詳細な説明】 「考案の目的」 本考案はプリント配線基板の考案に係り、誘電
率が極めて低く、しかも取扱いないし機器設定が
安定したプリント配線基板を提供し、機器の高速
化を図ろうとするものである。
[Detailed description of the invention] "Purpose of the invention" The present invention relates to the invention of a printed wiring board, which provides a printed wiring board that has an extremely low dielectric constant and is stable in handling and equipment settings, thereby increasing the speed of equipment. It is something that we try to do.

産業上の利用分野 電子機器用などのプリント配線基板。Industrial applications Printed wiring boards for electronic devices, etc.

従来の技術 プリント配線基板は複雑な導線の接続、配設に
代わるものとして電子機器などに広く用いられて
いるが、このような従来の基板はエポキシ基材、
ガラスエポキシ基材、セラミツク基材などに対し
電気回路を構成する導電体を直接に形成したもの
が一般的である。
Conventional technology Printed wiring boards are widely used in electronic devices as an alternative to complicated conductor connections and arrangements, but such conventional boards are made of epoxy base materials,
Generally, a conductor constituting an electric circuit is formed directly on a glass epoxy base material, a ceramic base material, or the like.

なおポリイアミド樹脂やポリエステル樹脂など
のフレキシブル性基材面に前記回路形成導電体を
直接に接着したものもある。
Note that there is also one in which the circuit-forming conductor is directly adhered to the surface of a flexible base material such as polyimide resin or polyester resin.

考案が解決しようとする問題点 ところで近時においてはガリウム砒素ICなど
の超高速素子が開発され、上記のようなプリント
配線板においても高速化が課題となつており、伝
播時間遅延は材料の誘導率に影響され、機器を高
速化するためには基材における誘電率が小さいこ
とが要請されるけれども、上述したような従来の
ものにおいてはこの誘電率が4〜7(at1MHz)と
相当に大きく、このような要請に充分即応し難
い。
Problems that the invention aims to solve By the way, in recent years, ultra-high-speed devices such as gallium arsenide ICs have been developed, and increasing the speed of printed wiring boards such as the one mentioned above has become an issue. In order to increase the speed of devices, it is required that the dielectric constant of the base material be small, but in the conventional materials mentioned above, this dielectric constant is quite large at 4 to 7 (at 1 MHz). , it is difficult to respond quickly enough to such requests.

「考案の構成」 問題点を解決するための手段 所要の機械的強度を有する基材面に空隙率70%
以上のポリテトラフロオロエチレン樹脂の多孔質
膜を介して電気回路を形成する導電体をテトラフ
ルオロエチレン−ヘキサフルオロピレン共重合体
の融着層により接着形成したことを特徴とするプ
リント配線基板。
``Constitution of the invention'' Means to solve the problem 70% porosity on the base material surface that has the required mechanical strength
A printed wiring board characterized in that a conductor forming an electric circuit is bonded to a fusion layer of tetrafluoroethylene-hexafluoropyrene copolymer via the porous film of polytetrafluoroethylene resin as described above.

作 用 ポリテトラフルオロエチレン樹脂による多孔質
膜は空隙率70%以上としたものを用いることによ
り、その誘電率が1.1〜1.3(at1MHz)と頗る小で、
このような誘電率の小さい多孔質膜を介して電気
回路を形成する導電体を接着形成することにより
信号伝達速度を充分に高速化しガリウム砒素IC
その他の超高速素子などと相俟つて信号速度の早
い回路が形成される。
Function By using a porous membrane made of polytetrafluoroethylene resin with a porosity of 70% or more, its dielectric constant is extremely low at 1.1 to 1.3 (at 1MHz).
By adhering the conductor that forms the electric circuit through such a porous film with a low dielectric constant, the signal transmission speed can be sufficiently increased to create a gallium arsenide IC.
In combination with other ultra-high-speed elements, a circuit with a high signal speed is formed.

基板においてプリント配線基板としての強度や
安定性を得しめ、その取扱ないし電子機器に対す
る設定を適切化する。
Achieving the strength and stability of a printed wiring board in a board, and optimizing its handling and settings for electronic equipment.

テトラフルオロエチレン−ヘキサフルオロピレ
ン共重合体による接着により好ましい耐薬品性を
もつた接着をなし、しかも連続多孔質ポリテトラ
フルオロエチレン樹脂膜の気孔組織を損なうこと
なしに安定な接着を得しめ、温度変化による回路
特性変化も少ない基板となる。
Adhesion using tetrafluoroethylene-hexafluoropyrene copolymer provides adhesion with favorable chemical resistance, and also achieves stable adhesion without damaging the pore structure of the continuous porous polytetrafluoroethylene resin membrane. The result is a board with little change in circuit characteristics due to changes.

実施例 本考案によるものの具体的な実施態様を添付図
面に示すものについて説明すると、第1、2図に
示すように所要の機械的強度を得るための基材2
面に接着層5によりポリテトラフルオロエチレン
樹脂の多孔質膜1を接着し、該多孔質膜1に電気
回路を形成する導電体3を接着形成したもんであ
つて、前記基材2としてはセラミツク、紙フエノ
ール、ガラスエポキシ、紙エポキシ、ガラス布ポ
リイミド、ポリイミド、ポリエステルなどの所要
の剛性、機械的強度をもつたものを用いることが
でき、回路形成導電体3としては第1図に示すよ
うな銅その他の金属箔層3a或いは第2図に示す
ように蒸着あるいはスパツタリング層3bの何れ
でもよい。又接着層4,5はテトラフルオロエチ
レン−ヘキサフルオロピレン共重合体(FEP)
を用いることによりポリテトラフルオロエチレン
樹脂多孔質化膜の組織を損なうことが少なく、又
温度変化によつて回路特性に影響を来すことの少
ない製品が得られる。前記FEPによる接着は該
FEPが溶剤などで溶解しないことから加熱融着
法で有効になされる。
EXAMPLE To explain the specific embodiment of the present invention shown in the attached drawings, as shown in FIGS. 1 and 2, a base material 2 for obtaining the required mechanical strength
A porous membrane 1 of polytetrafluoroethylene resin is adhered to the surface with an adhesive layer 5, and a conductor 3 for forming an electric circuit is adhesively formed on the porous membrane 1, and the base material 2 is made of ceramic. , paper phenol, glass epoxy, paper epoxy, glass cloth polyimide, polyimide, polyester, etc. having the required rigidity and mechanical strength can be used.As the circuit forming conductor 3, materials such as those shown in FIG. Either a copper or other metal foil layer 3a or a vapor deposited or sputtered layer 3b as shown in FIG. 2 may be used. The adhesive layers 4 and 5 are made of tetrafluoroethylene-hexafluoropyrene copolymer (FEP).
By using this method, it is possible to obtain a product in which the structure of the polytetrafluoroethylene resin porous membrane is less likely to be damaged, and the circuit characteristics are less affected by temperature changes. Adhesion using FEP is applicable.
Since FEP does not dissolve with solvents, it can be effectively bonded by heat fusing.

このような基材2と回路形成導電体3との間に
形成されるポリテトラフルオロエチレンの多孔質
膜1はその若干例が第3図と第4図に示される如
くであつて、ポリテトラフルオロエチレン樹脂フ
イルムを圧延又は延伸の何れか一方又は双方によ
り加工することにより多数の微小結節部11間が
無数の微細繊維12によつてくもの巣状に連結さ
れた組織となり、このような微細繊維12間の孔
隙13は0.02μmにも達する微細なもので樹脂質
自体の撥水性とも相俟つて水のような液体分を透
過せしめない非透水性のものであり、後工程で使
用されるエツチング液に充分耐え得るものであ
る。その空隙率は70%以上、一般的には80%以上
で、92〜93%にも達する程のものであるが上記し
たような微細繊維組織によつて前記基材2上にテ
トラフルオロエチレン−ヘキサフルオロピレン共
重合体(FEP)の融着による接着層5により安
定に接着することができる。又その蒸着あるいは
スパツタリングによる導電体3bを上記したよう
な多孔質膜1の非層に対し薄く充実化した層を形
成し得る。或いは他の樹脂によるラミネート又は
コーテイングによる接着材4を薄く表面に形成
し、フイブリル化多孔質膜1の基本特質を損なう
ことなしに、しかも導電体3の好ましい接着を図
ることができる。このようにして基材2上に形成
されたフイブリル化多孔質膜1における誘電率は
上記したような空隙率やフイブリル化の程度によ
つて若干の差があるとしても概略1.1〜1.3(at1M
Hz)であり、上記した従来の配線基板用基材より
も大幅に小さいものであつて、このように誘電率
の小さい多孔質膜1を用いることにより該プリン
ト配線基板の信号伝達速度を高速化することがで
き、前述したような超高速素子等と組合わせるこ
とにより全体とてい信号速度の早い電気回路を構
成することができる。
Some examples of the polytetrafluoroethylene porous membrane 1 formed between the base material 2 and the circuit-forming conductor 3 are shown in FIGS. 3 and 4. By processing a fluoroethylene resin film by rolling or stretching or both, a structure is formed in which a large number of micro nodules 11 are connected in a spider web shape by countless microfibers 12. The pores 13 between the fibers 12 are as fine as 0.02 μm, and combined with the water repellency of the resin itself, they are water-impermeable and do not allow liquids such as water to pass through, and are used in subsequent processes. It is sufficiently resistant to etching liquid. The porosity is 70% or more, generally 80% or more, and even reaches 92 to 93%, but due to the fine fiber structure as described above, tetrafluoroethylene- Stable adhesion can be achieved by the adhesive layer 5 formed by fusing hexafluoropyrene copolymer (FEP). Further, the conductor 3b formed by vapor deposition or sputtering can be formed into a thin and solid layer with respect to the non-layer of the porous membrane 1 as described above. Alternatively, by forming a thin layer of adhesive 4 on the surface by laminating or coating with another resin, desirable adhesion of the conductor 3 can be achieved without impairing the basic characteristics of the fibrillated porous membrane 1. The dielectric constant of the fibrillated porous film 1 thus formed on the base material 2 is approximately 1.1 to 1.3 (at1M
Hz), which is significantly smaller than the above-mentioned conventional wiring board base material, and by using the porous film 1 with such a low dielectric constant, the signal transmission speed of the printed wiring board can be increased. By combining the above-mentioned ultra-high-speed elements, etc., it is possible to construct an electric circuit with a high overall signal speed.

「考案の効果」 以上説明したような本考案によるときは基材上
に空隙率70%以上であるポリテトラフルオロエチ
レン樹脂の多孔質膜を介して回路形成導電体を形
成することにより信号伝達速度を高速化したプリ
ント配線基板を提供し、又その取扱いないし機器
内設定を容易且つ的確化し、しかもFEPによる
接着でポリテトラフルオロエチレン多孔質樹脂組
織を完全状態に維持せしめたものとなし、又回路
特性を向上し、近時開発された超高速素子などと
相俟つて電気機器の性能を有効に向上し得るもの
であるから工業的にその効果の大きい考案であ
る。
"Effects of the invention" According to the invention as explained above, the signal transmission speed is improved by forming a circuit-forming conductor on a base material through a porous membrane of polytetrafluoroethylene resin with a porosity of 70% or more. The present invention provides a printed wiring board that speeds up the processing of circuits, makes it easy and accurate to handle it and set it inside the device, and maintains the polytetrafluoroethylene porous resin structure in a perfect state by bonding with FEP. This is a highly effective idea industrially, as it can improve the characteristics and effectively improve the performance of electrical equipment when combined with recently developed ultra-high-speed elements.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の実施態様を示すものであつて、
第1図と第2図はそれぞれ本考案によるプリント
配線基板の部分的断面図、第3図と第4図はその
ポリテトラフルオロエチレン樹脂多孔質化膜の繊
維形状を夫々示した顕微鏡写真である。 然してこれらの図面において、1はポリテトラ
フルオロエチレン樹脂多孔質化膜、2は基材、3
は電気回路を形成する導電体、4,5は接着層、
11は微小結節部、12は微細繊維、13は孔隙
を示すものである。
The drawings show embodiments of the invention,
Figures 1 and 2 are partial cross-sectional views of the printed wiring board according to the present invention, and Figures 3 and 4 are microscopic photographs showing the fiber shape of the porous polytetrafluoroethylene resin membrane, respectively. . However, in these drawings, 1 is a porous polytetrafluoroethylene resin membrane, 2 is a base material, and 3 is a porous polytetrafluoroethylene resin membrane.
is a conductor forming an electric circuit, 4 and 5 are adhesive layers,
11 is a micronodule, 12 is a fine fiber, and 13 is a pore.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所要の機械的強度を有する基材面に空隙率70%
以上のポリテトラフロオロエチレン樹脂の多孔質
膜を介して電気回路を形成する導電体をテトラフ
ルオロエチレン−ヘキサフルオロピレン共重合体
の融着層により接着形成したことを特徴とするプ
リント配線基板。
70% porosity on the base material surface with the required mechanical strength
A printed wiring board characterized in that a conductor forming an electric circuit is bonded to a fusion layer of tetrafluoroethylene-hexafluoropyrene copolymer via the porous film of polytetrafluoroethylene resin as described above.
JP1985136894U 1985-09-09 1985-09-09 Expired JPH0246062Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985136894U JPH0246062Y2 (en) 1985-09-09 1985-09-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985136894U JPH0246062Y2 (en) 1985-09-09 1985-09-09

Publications (2)

Publication Number Publication Date
JPS6245863U JPS6245863U (en) 1987-03-19
JPH0246062Y2 true JPH0246062Y2 (en) 1990-12-05

Family

ID=31040435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985136894U Expired JPH0246062Y2 (en) 1985-09-09 1985-09-09

Country Status (1)

Country Link
JP (1) JPH0246062Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60225750A (en) * 1984-04-24 1985-11-11 株式会社 潤工社 Printed substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60225750A (en) * 1984-04-24 1985-11-11 株式会社 潤工社 Printed substrate

Also Published As

Publication number Publication date
JPS6245863U (en) 1987-03-19

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