JPH0245961A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0245961A JPH0245961A JP19688288A JP19688288A JPH0245961A JP H0245961 A JPH0245961 A JP H0245961A JP 19688288 A JP19688288 A JP 19688288A JP 19688288 A JP19688288 A JP 19688288A JP H0245961 A JPH0245961 A JP H0245961A
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead wiring
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000605 extraction Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 12
- 229920005989 resin Polymers 0.000 abstract description 12
- 239000000919 ceramic Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体チップを収容するパッケージに関する
ものであり、特にプリント回路配綜基板等に実装される
までにパッケージが受ける種々のストレスからリード配
線の曲がり折れを防ぐ方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a package for housing a semiconductor chip, and in particular, lead wiring is reduced due to the various stresses that the package receives before being mounted on a printed circuit board, etc. The present invention relates to a method for preventing bending and breaking.
従来この種の半導体集積回路装置としては第５図に示す
ものがある。Ｍ５図はプラスチック型ＤＩ Ｐ （ｄｕ
ａｌ ｉｎ １ｉｎｅ ｐａｃｋａｇｅ）の断面図であ
り、図において、（１）はパッケージを形成するモール
ド樹脂、（２）は半導体チップ、（３）は半導体チップ
（２）をマウントするだめのダイパッド、（４）はリー
ド配線で外部接続用として使用される。（５）は半導体
チップ（２）とリード配線（４）を接続するためのボン
デインダワイヤーである。A conventional semiconductor integrated circuit device of this type is shown in FIG. The M5 diagram shows the plastic type DI P (du
In the figure, (1) is a mold resin forming the package, (2) is a semiconductor chip, (3) is a die pad for mounting the semiconductor chip (2), and (4) is a cross-sectional view of an inline package. ) is used for lead wiring for external connection. (5) is a bonder wire for connecting the semiconductor chip (2) and lead wiring (4).
次に構造の特徴について説明する。図に示すようにパッ
ケージを形成するモールド樹脂（１）のリード配！ （
４）よ）上部の幅ａ１と下部の幅１）ｌが同程度となっ
ていた。Next, the characteristics of the structure will be explained. As shown in the figure, the lead arrangement of the mold resin (1) that forms the package! (
4) The upper width a1 and the lower width 1) l were about the same.
従来の半導体集積回路装置は以上のように構成されてい
るのでこの装置をプリント基板等に実装するまでに種々
のパッケージへのストレスヲ受ける。例えば半導体チッ
プをパッケージに収容後、機能試験の際の搬送時又は出
荷中における搬送ケースとの衝突あるいはプリント基板
実装のための。Since the conventional semiconductor integrated circuit device is constructed as described above, the package is subjected to various stresses before the device is mounted on a printed circuit board or the like. For example, after a semiconductor chip is housed in a package, it may collide with a transport case during functional testing or during shipping, or it may be mounted on a printed circuit board.
搬送時などである。このようなストレスにより、リード
配線が曲がった９、折れたシすることにより自動搬送が
不可能になったシ、牛導体集積回路装置七のものが機能
を果たさなくなったりする等の問題があった０
この発明は上記のような問題点を解消するためになされ
たもので、種々のパッケージへのストレスからリード配
線を保護できる半導体集積回路装置を得ることを目的と
する。For example, during transportation. Such stress caused problems such as lead wires being bent9, broken, making automatic transportation impossible, and conductor integrated circuit devices no longer functioning. 0 This invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device that can protect lead wiring from various stresses on packages.
この発明に係る半導体集積回路装置はリード配線上部の
パッケージ幅をリード配線下部のパッケージ幅よシ広く
したものである。In the semiconductor integrated circuit device according to the present invention, the package width above the lead wires is wider than the package width below the lead wires.
パッケージ形状を上記のようにすることにより、リード
配縁はパッケージによシ保護されるためストレスを直接
受けることがない０
〔実施例〕
以下、この発明の一実施例を図について説明する。第１
図はこの発明によるプラスチック型ＤＩＰの断面図であ
シ、図において、（１）はパッケージを形成するモール
ド樹脂、（２）は半導体チップ、（３）は半導体チップ
（２）をマウントするためのダイノ（ラド、（４）はリ
ード配線で外部接続用として使用される０（５）は半導
体チップ（２）とリード配線（４）を接続するためのポ
ンディングワイヤーである。図に示すようにパッケージ
を形成するモールド樹脂（１）のリード配線（４）よシ
上部の幅ａ２が下部の＠１）２よシ広くなっている。こ
のためリード配線（４）はモールド樹脂（１）の上部に
より保護されるのでストレスを直接受けることがなくな
り、曲がったシ、折れたりすることがなくなる。By making the package shape as described above, the lead wiring is protected by the package and is not directly exposed to stress. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view of a plastic-type DIP according to the present invention. In the figure, (1) is the mold resin forming the package, (2) is the semiconductor chip, and (3) is the mold resin for mounting the semiconductor chip (2). Dyno (4) is a lead wiring used for external connection.0 (5) is a bonding wire for connecting the semiconductor chip (2) and lead wiring (4).As shown in the figure. The width a2 of the upper part of the mold resin (1) forming the package is wider than that of the lead wiring (4) than that of the lower part @1)2. Therefore, the lead wiring (4) is protected by the upper part of the molded resin (1), so that it is not directly subjected to stress and is prevented from being bent or broken.
なお、上記実施例ではプラスチック型ＤＩＰについて説
明したが、他に表面実装凰パッケージへの応用も考えら
れる。表面実装型パッケージのＩＪ −ド配線は一般に
ＤＩＰに比べ弱く、プリント基板への自動マウント等も
なされるためリード配線の曲がりや折れが発生する確率
が高い。表面実装型パッケージとしてはＰＬＯＣ（ｐｌ
ａｓｔｉｃ １ｏａｄｅｄ ｃｈｉｐｃａｒｒｉｅｒ）
、 Ｓ ＯＰ （ｓｍａｌｌ ｏｕｔｌｉｎｅ ｐａ
ｃｋａｇｅ）等がある。第２図はこの発明によるＰＬＯ
Ｏへの実施例を示す断面図（モールド樹脂、（１）の内
部省略）、第４図はこの発明によるｓｏｐへの実施例を
示す断面図（モールド樹脂ｔｌ）の内部省略）、更に他
への実施例として第４図はセラミック型ＤＩＰへの適用
例を示す断面図である。図中ｔｌ） 、 ＋２１ 、
＋４） 、 ＋５）は第５図の従来例に示したものと同
等であるので説明を省略する。（６）はパッケージ上部
を形成するセラミック型フタ、（７）ｌｊパッケージ下
部を形、成するセラミック型パッケージ本体、（８）は
セラミック型フタ（６）とセラミック型本体（７）全接
着するガラスシール材である。In the above embodiment, a plastic type DIP was described, but other applications may be considered, such as a surface-mounted phosphor package. The IJ lead wiring of a surface mount type package is generally weaker than that of a DIP, and since it is automatically mounted on a printed circuit board, there is a high probability that the lead wiring will bend or break. PLOC (pl
astic 1loaded chip carrier)
, S OP (small outline pa
ckage) etc. Figure 2 shows the PLO according to this invention.
FIG. 4 is a sectional view showing an embodiment of the invention to O (mold resin, (1) internally omitted), FIG. As an example, FIG. 4 is a sectional view showing an example of application to a ceramic type DIP. tl in the figure), +21,
+4) and +5) are the same as those shown in the conventional example shown in FIG. 5, so their explanation will be omitted. (6) is a ceramic type lid that forms the upper part of the package, (7) a ceramic type package body that forms the lower part of the lj package, and (8) is a glass that completely adheres the ceramic type lid (6) and the ceramic type body (7). It is a sealing material.
以上のようにこの発明によれば、パッケージ上部をリー
ド配線を＆＆するようにパッケージ下部よシ幅広くした
ので、リード配線の折れ曲がシの少ない半導体集積回路
装置が得られる０As described above, according to the present invention, since the upper part of the package is made wider than the lower part of the package so that the lead wiring is connected, a semiconductor integrated circuit device with fewer bends in the lead wiring can be obtained.
第１図ないし第４図はこの発明に係る半導体集積回路の
実施例で、第１図はプラスチック型ＤＩＰの断面図、第
２図はＰＬＣＣの断面図（モールド樹脂内部省略）、第
３図はｓａｐの断面図（モールド樹脂内部省略）、第４
図はセラミック型ＤＩＰの断面図、第５図は従来のプラ
スチック型ＤＩＰの断面図である。
図において、（１）はモールド樹脂、（２）は半導体チ
ップ、Ｇ３＞ ｌＩｉダイパッド、（４）はリード配線
、（５）はポンディングワイヤー、（６）Ｈセラミック
型フタ、（７）はセラミック型パッケージ本体、（８）
はガラスシール材である。
な−シ、図中、同−符＋’ｉ Ｉま同一、又は相当部分
を示す。
代ｊ人 大岩増雄
第１図
ρ２
第４図
第２図
第５図
ρｌ
第３図1 to 4 show examples of semiconductor integrated circuits according to the present invention, in which FIG. 1 is a cross-sectional view of a plastic type DIP, FIG. 2 is a cross-sectional view of a PLCC (molding resin inside is omitted), and FIG. Cross-sectional view of SAP (mold resin interior omitted), 4th
The figure is a sectional view of a ceramic type DIP, and FIG. 5 is a sectional view of a conventional plastic type DIP. In the figure, (1) is mold resin, (2) is semiconductor chip, G3>IIi die pad, (4) is lead wiring, (5) is bonding wire, (6) H ceramic type lid, (7) is ceramic Type package body, (8)
is a glass sealant. In the figures, the same symbols +'i and I indicate the same or equivalent parts. Masuo Oiwa Figure 1 ρ2 Figure 4 Figure 2 Figure 5 ρl Figure 3
Claims (1)
線に対してパッケージ上部の幅をパッケージ下部の幅よ
りリード配線取り出し方向に広くしたことを特徴とする
半導体集積回路装置。1. A semiconductor integrated circuit device in which a package for accommodating a semiconductor chip is characterized in that the width of the upper part of the package with respect to lead wiring is wider in the lead wiring extraction direction than the width of the lower part of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19688288A JPH0245961A (en) | 1988-08-06 | 1988-08-06 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19688288A JPH0245961A (en) | 1988-08-06 | 1988-08-06 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0245961A true JPH0245961A (en) | 1990-02-15 |
Family
ID=16365223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19688288A Pending JPH0245961A (en) | 1988-08-06 | 1988-08-06 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0245961A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0657922A1 (en) * | 1993-12-10 | 1995-06-14 | Hitachi, Ltd. | A packaged semiconductor device and method of its manufacture |
-
1988
- 1988-08-06 JP JP19688288A patent/JPH0245961A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0657922A1 (en) * | 1993-12-10 | 1995-06-14 | Hitachi, Ltd. | A packaged semiconductor device and method of its manufacture |
| KR950021459A (en) * | 1993-12-10 | 1995-07-26 | 가나이 쓰토무 | Package semiconductor device having a flange on the side and manufacturing method thereof |
| US5885852A (en) * | 1993-12-10 | 1999-03-23 | Hitachi, Ltd. | Packaged semiconductor device having a flange at its side surface and its manufacturing method |
| CN1059053C (en) * | 1993-12-10 | 2000-11-29 | 株式会社日立制作所 | A packaged semiconductor device having a flange at its side surface and its manufacturing method |
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