JPH0245956A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0245956A
JPH0245956A JP63196499A JP19649988A JPH0245956A JP H0245956 A JPH0245956 A JP H0245956A JP 63196499 A JP63196499 A JP 63196499A JP 19649988 A JP19649988 A JP 19649988A JP H0245956 A JPH0245956 A JP H0245956A
Authority
JP
Japan
Prior art keywords
scribe line
insulating film
film
semiconductor device
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63196499A
Other languages
Japanese (ja)
Inventor
Toshio Endo
遠藤 稔雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63196499A priority Critical patent/JPH0245956A/en
Publication of JPH0245956A publication Critical patent/JPH0245956A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent occurrences of conductive foreign substances and hinder the development of cracks when a dicing process is performed by coating a scribe line region with the second and third insulating films and a passivation film. CONSTITUTION:A semiconductor device is formed by making a LOCOS oxide film 2 which is formed on a semiconductor substrate 1 act as the first insulating film. In such a case, scribe line regions 11 are coated with the second and third insulating films 4 and 6 and a passivation film 8. No bases which are formed below various patterns of a gate electrode, the first and second conduction wiring layers 5 and 7 are scooped out by photoetching in an after-treatment process. Such a superior state of the scribe line regions prevents occurrences of conductive foreign substances which give rise to inferior reliability and binder the development of cracks when a dicing process is performed.

Description

【発明の詳細な説明】 【産業上の利用分野〕 本発明は、半導体装置のスクライブライン領域の構造に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a scribe line region of a semiconductor device.

〔従来の技術1 従来のスクライブライン領域の構造は、特開昭60−2
53241の様にスクライブライン領域の中に各種パタ
ーン(半導体装置の特性を測定する半導体素子、アライ
メントマーク、アライメントずれを測定するパターン、
寸法を測定するパターン等)の有無に関係なく一様であ
った。
[Prior art 1 The structure of the conventional scribe line area is disclosed in Japanese Patent Application Laid-Open No. 60-2
Various patterns (semiconductor elements for measuring characteristics of semiconductor devices, alignment marks, patterns for measuring misalignment,
It was uniform regardless of the presence or absence of a pattern (such as a pattern for measuring dimensions).

[発明が解決しようとする課題] しかし、前述の従来技術ではスクライブライン領域に第
1導電配線のアライメントマーク、アライメントずれを
測定するパターン、寸法を測定するパターン等の下地と
なる半導体基板が前記の各種パターンを形成する時の第
1導電配線のエツチング工程や、後工程の第3絶縁膜や
パッシベーション膜のエツチングによって前記第1導電
配線の下地の半導体基板がエツチングされえぐられてそ
の結果として第1導電配線が半導体基板に十分に保持さ
れなくなって剥離し導電性異物となった。この事は、特
に微細化が進んで来て使用するパターンの寸法が2μm
以下になって来た事も要因の一つであるけれど、この剥
離して生じた導電性異物は半導体装置の製造及び品質に
大きな支障をきたすものである。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, the semiconductor substrate that serves as the base for the alignment mark of the first conductive wiring, the pattern for measuring misalignment, the pattern for measuring dimensions, etc. in the scribe line region is During the etching process of the first conductive wiring when forming various patterns, and the etching of the third insulating film and passivation film in the subsequent process, the semiconductor substrate underlying the first conductive wiring is etched and gouged, and as a result, the first conductive wiring is etched. The conductive wiring was no longer held sufficiently by the semiconductor substrate and peeled off, becoming conductive foreign matter. This is especially true as miniaturization progresses and the dimensions of the patterns used are 2 μm.
The conductive foreign matter generated by this peeling poses a major problem in the manufacturing and quality of semiconductor devices, although the following is one of the factors.

まず、アライメントマークが損傷を受けると、後工程の
フォトリソグラフィ工程のアライメント工程においてア
ライメントが不能となり半導体装置の製造に支障をきた
す。次に、剥離した前記導電性異物がウェハーに付着す
るとゲート電極や第1導電配線そして第2導電配線の短
絡の原因となったり、ウェハー上の突起となりフォトリ
ングラフィ工程におけるフォトレジストの膜厚むらの原
因となって正常なフォトリングラフィ工程のパターン形
成を阻害しパターンの短絡や断線等のパターン欠陥をも
たらし、歩留りを低下させるものである。さらには、ウ
ェハー上に付着しても初期の段階では何も悪影響を与え
ずに良品として出荷され、長期にわたる使用において、
付着した導電性異物が水分等によって劣化して半導体装
置の機能を低下させて不良となり信頼性不良を引き起す
事になり重大な品質の問題となる。
First, if the alignment mark is damaged, alignment becomes impossible in the alignment process of the subsequent photolithography process, which hinders the manufacture of semiconductor devices. Next, if the peeled conductive foreign matter adheres to the wafer, it may cause a short circuit between the gate electrode, the first conductive wiring, and the second conductive wiring, or it may become a protrusion on the wafer, causing uneven thickness of the photoresist during the photolithography process. This hinders normal pattern formation in the photolithography process, causing pattern defects such as short circuits and disconnections in the pattern, and lowering yield. Furthermore, even if it adheres to the wafer, it does not have any adverse effects in the initial stage and is shipped as a good product, and after long-term use,
The attached conductive foreign matter deteriorates due to moisture and the like, lowering the functionality of the semiconductor device and causing defects, resulting in poor reliability, resulting in a serious quality problem.

そこで本発明は、前述のような問題点を解決するもので
、その目的は導電性異物が発生しないスクライブライン
領域の構造を提供するところにある。
SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a structure of a scribe line region in which conductive foreign matter is not generated.

[課題を解決するための手段1 本発明の半導体装置はスクライブライン領域を第2絶縁
膜と第3絶縁膜およびパッシベーション膜を被覆し、前
記パッシベーション膜な前記半導体装置の周囲に沿って
線状に除去し溝部を形成しスクライブライン領域の中に
Locos酸化膜のパターンとゲート電極のパターンと
第2絶縁膜のパターンと第1導電配線のパターンと第3
絶縁膜のパターンと第2導電配線のパターンが形成され
た領域の上部のみに形成する。また、前記第2絶縁膜の
一部と前記第3絶縁膜の一部を除去した領域を配した事
を特徴とする。
[Means for Solving the Problems 1] In the semiconductor device of the present invention, a scribe line region is covered with a second insulating film, a third insulating film, and a passivation film, and the passivation film is formed linearly along the periphery of the semiconductor device. A groove is formed by removing a Locos oxide film pattern, a gate electrode pattern, a second insulating film pattern, a first conductive wiring pattern, and a third conductive wiring pattern in the scribe line area.
It is formed only over the region where the insulating film pattern and the second conductive wiring pattern are formed. Further, a region is provided in which a part of the second insulating film and a part of the third insulating film are removed.

[実 施 例] 第1図は本発明の実施例のスクライブライン領域の断面
図。第2図は本発明の実施例の各種パターンがないスク
ライブライン領域の断面図、第3図は本発明の実施例の
第2絶縁膜と第3絶縁膜の一部除去領域の平面図。
[Embodiment] FIG. 1 is a cross-sectional view of a scribe line area according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a scribe line region without various patterns in an embodiment of the present invention, and FIG. 3 is a plan view of a partially removed region of a second insulating film and a third insulating film in an embodiment of the present invention.

半導体基板lに第1絶縁膜としてLOCO3酸化膜2を
形成し、その上にゲート電極3を形成し次に第2絶縁膜
4を形成しフォトリソグラフィ工程によって第3図の1
2で表示した領域をスクライブライン領域の中にエツチ
ングモニタ一部12としてフォトレジストを除去しエツ
チングによって前記第2絶縁114を除去した。次に第
2導電配線5を形成し、その上に第3絶縁膜6を形成し
、フォトリングラフィ工程によって前記第2絶縁膜4の
エツチングモニタ一部12の中に第3絶縁膜6のエツチ
ングモニタ一部13をフォトレジストパターンのぬきパ
ターンで形成しエツチングによって除去し、その上にパ
ッシベーション膜8を形成しフォトエツチングによって
各種パターンが形成されているスクライブライン領域は
半導体装置11より10L1mスクライブライン領域に
入った箇所に5μm幅で前記半導体装置11に平行に前
記パッシベーション膜8を除去し溝部9を形成し第1図
に示した様な断面構造を有すスクライブライン領域を形
成した。また、各種パターンがないスクライブライン領
域は全面において前記パッシベーション膜8を除去し第
2図の様な断面構造を有すスクライブライン領域を形成
し、前記第2絶縁膜4及び前記第3絶縁膜6のエツチン
グモニタ一部12及び13においても前記パッシベーシ
ョン膜8を除去したに のような構造にする事により、前記ゲート電極3と前記
第1導電配線5と前記第2導電配線7のパターンは下地
を後工程のフォトエッチングエ程において^ぐられる事
がなくなり、その結果として半導体装置の製造において
、アライメントマークの損傷がなくなり、アライメント
不能を後工程のフォトリソグラフィ工程で生ずる事がな
くなり支障をきたす事がなくなった。また、剥離する事
がなくな・り導電性異物が生しなくなったために歩留り
の低下及びに信頼性不良という重大な問題を生じなくな
った。さらには、グイシング工程においては、スクライ
ブライン領域IOの中にパッシベーション膜8の溝部9
を形成する事により、グイシング工程において発生する
クラックを前記溝部9によって食い止め半導体装置が損
傷を受けるのを防止するという効果も有するものである
A LOCO3 oxide film 2 is formed as a first insulating film on a semiconductor substrate l, a gate electrode 3 is formed thereon, a second insulating film 4 is formed, and a photolithography process is performed to form a LOCO3 oxide film 2 as shown in FIG.
The photoresist was removed by using the area indicated by 2 as an etching monitor part 12 in the scribe line area, and the second insulating layer 114 was removed by etching. Next, a second conductive wiring 5 is formed, a third insulating film 6 is formed thereon, and the third insulating film 6 is etched into the etching monitor portion 12 of the second insulating film 4 by a photolithography process. A portion of the monitor 13 is formed using a cutout pattern of a photoresist pattern and removed by etching, a passivation film 8 is formed thereon, and various patterns are formed by photoetching.The scribe line area is 10L1m from the semiconductor device 11. The passivation film 8 was removed in parallel to the semiconductor device 11 with a width of 5 .mu.m to form a groove 9 at the location where the groove was inserted, thereby forming a scribe line region having a cross-sectional structure as shown in FIG. Further, in the scribe line region where there is no pattern, the passivation film 8 is removed from the entire surface to form a scribe line region having a cross-sectional structure as shown in FIG. By removing the passivation film 8 from the etching monitor portions 12 and 13 as well, the patterns of the gate electrode 3, the first conductive wiring 5, and the second conductive wiring 7 are formed using the underlying layer. This eliminates damage in the post-process photo-etching process, and as a result, there is no damage to the alignment mark in the manufacturing of semiconductor devices, and alignment failures do not occur in the post-process photolithography process, which prevents problems. lost. Furthermore, since there is no peeling and conductive foreign matter is no longer generated, serious problems such as a decrease in yield and poor reliability do not occur. Furthermore, in the guising process, the groove portion 9 of the passivation film 8 is formed in the scribe line region IO.
By forming this, the groove portion 9 also has the effect of stopping cracks generated in the guising process and preventing damage to the semiconductor device.

しかし、同様の効果を得るためならば前記第2絶縁膜4
や前記第3絶縁膜6においてもパッシベーション膜8の
溝部9の形成と同じようにフォトエツチングによって形
成してもよい訳であるが、第2絶縁tli4や第3絶縁
tli6に溝部があると各次工程の第1導電配線や第2
導電配線のフォトエツチング工程のフォトリソグラフィ
工程において、溝部の段差によって使用するフォトレジ
ストかたまって膜厚が厚くなって所定のパターン形成に
用いる露光量では露光量不足となってフォトレジスト残
りが溝部に発生しこれが第12Jl電配線及び第2導電
配線のエツチングにおいて、エツチング残りになる。こ
のエツチング残りが次工程のフォトレジスト剥離工程や
後工程のフォトエツチングにより、前記エツチング残り
が剥離し導電性異物となる。しかし本発明は、第2絶縁
膜と第3絶縁膜においては、スクライブライン領域に溝
部を形成しないで全面被覆とする事により導電性異物の
発生を防止している。
However, in order to obtain the same effect, the second insulating film 4
Also, the third insulating film 6 may be formed by photo-etching in the same way as the groove 9 of the passivation film 8, but if there is a groove in the second insulating tli4 or the third insulating tli6, each The first conductive wiring and the second
In the photolithography process of the photoetching process of conductive wiring, the photoresist used clumps up due to the step in the groove and becomes thicker, resulting in an insufficient amount of exposure for the prescribed pattern formation, leaving photoresist residue in the groove. However, this becomes the etching residue when etching the 12th Jl electrical wiring and the second electrical wiring. This etching residue is peeled off by the next photoresist stripping process or the post-process photoetching, and becomes a conductive foreign substance. However, in the present invention, the generation of conductive foreign matter is prevented by covering the entire surface of the second and third insulating films without forming grooves in the scribe line regions.

さらには、スクライブライン領域の構造を各種パターン
がある箇所は第1図の様に形成し、各種パターンがない
箇所は第2図の様に形成する事により、グイシング工程
で使用するグイシングツの負荷を低減するという効果を
有する。スクライブライン領域にグイシングツ−に負担
がかからないようにLOGO5酸化膜と第2絶縁膜と第
3絶縁膜とパッシベーション膜を形成しない様にした。
Furthermore, by forming the structure of the scribe line area where there are various patterns as shown in Figure 1, and where there are no patterns as shown in Figure 2, the load on the scribing lines used in the scribing process can be reduced. It has the effect of reducing The LOGO5 oxide film, the second insulating film, the third insulating film, and the passivation film were not formed so as not to place any burden on the scribe line region.

これにより、グイシングツ−の消耗を抑え、グイシング
ツ−の交換や調整の工数増大と使用量の増大を低減する
事が可能となった。
This makes it possible to suppress the wear and tear of the guissing tool, and to reduce the increase in man-hours for replacement and adjustment of the guissing tool, as well as the increase in the amount used.

以上の様なスクライブライン領域に第2絶縁膜と第3絶
縁膜を全面に被覆する事により前述の様な効果を得られ
る訳であるが、半導体装置を製造する上では、やはりフ
ォトエツチング工程においては、エツチングが終了した
か否か外観検査を行なえればなお良い訳であり、さらに
は−、エツチングの速度を測定する箇所が所望される訳
であり、もう1つは、第3絶縁膜を形成後の膜厚確認で
きる箇所が第2絶縁膜が全面に被覆されているために不
可能であった。しかし、本発明は、スクライブライン領
域の中に第3図で示した様に第2絶縁膜のエツチングモ
ニタ一部12をやや大きく形成し、これにより外観検査
とエツチングの速度の測定をできる様にした。また第3
絶縁膜のエツチングモニタ一部13を前記第2絶縁膜の
エツチングモニター12より小さく形成した。これによ
り、第3絶縁膜の膜厚測定は第2絶縁膜のエツチングモ
ニタ一部12で行なう事ができ、第3絶縁膜のフォトエ
ツチング工程後の外観検査及びエツチングの速度の測定
をエツチングモニタ一部13を用いて行なう事ができる
ものである。このエツチングモニタ一部という領域なス
クライブライン領域の中に設ける事により前述の発明の
効果を損う事なく半導体装置の製造工程を管理できるも
のとした。
By covering the entire surface of the scribe line region with the second insulating film and the third insulating film, the above-mentioned effects can be obtained, but in manufacturing semiconductor devices, the photo-etching process is still necessary. In this case, it would be better if the appearance could be inspected to see if etching has been completed.Furthermore, it would be desirable to have a place to measure the rate of etching. It was impossible to check the thickness of the film after it was formed because the entire surface was covered with the second insulating film. However, in the present invention, as shown in FIG. 3, the etching monitor portion 12 of the second insulating film is formed in the scribe line area to be slightly larger, thereby making it possible to inspect the appearance and measure the etching speed. did. Also the third
The etching monitor portion 13 of the insulating film was formed smaller than the etching monitor 12 of the second insulating film. As a result, the film thickness of the third insulating film can be measured using the etching monitor part 12 of the second insulating film, and the appearance inspection and etching speed measurement after the photoetching process of the third insulating film can be performed using the etching monitor part 12. This can be done using part 13. By providing this etching monitor in the scribe line region, which is a part of the etching monitor, it is possible to control the manufacturing process of the semiconductor device without impairing the effects of the invention described above.

[発明の効果] 以上述べたように本発明によればスクライブライン領域
に形成されたゲート電極と第1導電配線と第2導電配線
のパターンを半導体基板から剥離する事な(保持し、半
導体装置を製造する上で支障となるアライメントマーク
の損傷を防止し、歩留りの低下や信頼性不良の原因とな
る導電性異物の発生も防止するという効果を有する。ま
た、スクライブライン領域の中に半導体装置の周囲をか
こむようにパッシベーション膜の溝部を形成した事によ
りグイシング工程のクラックを食い止めるという効果も
有するものである。さらにはスクライブライン領域の中
に各種パターンがない箇所のパッシベーション膜を除去
する事によりグイシングツ程におけるグイシングツ−の
負荷を軽減し寿命を延しグイシングツ−の交換及び調整
の工数増大や使用量の増大を防止するという効果も有す
るものである。
[Effects of the Invention] As described above, according to the present invention, the patterns of the gate electrode, the first conductive wiring, and the second conductive wiring formed in the scribe line region are not peeled off from the semiconductor substrate (they are held and the semiconductor device This has the effect of preventing damage to alignment marks that can be a hindrance in manufacturing semiconductor devices, as well as preventing the generation of conductive foreign matter that can lead to lower yields and poor reliability. It also has the effect of preventing cracks in the guising process by forming a groove in the passivation film to surround the periphery of the scribe line.Furthermore, by removing the passivation film in areas where there are no patterns in the scribe line area, the guising process can be prevented. It also has the effect of reducing the load on the guising tool during the process, extending its life, and preventing an increase in the number of man-hours for replacement and adjustment of the guising tool, as well as an increase in the amount used.

また、スクライブライン領域にエツチングモニタ一部を
除く所に第2絶縁膜と第3絶縁膜を形成する事により半
導体装置と同じ膜の構造となったのでゲート電極や第1
21電配線や第2導電配線のパターン形成を行なうフォ
トリソグラフィ工程の精度も向上し半導体装置と同様の
パターン形状や寸法を形成する事ができるようになった
。この効果として、スクライブライン領域に形成する半
導体装置の特性を測定する半導体素子の特性が半導体装
置及び半導体装置内にある特性を測定する半導体素子の
特性とよく一致する様になり半導体装置の製造をより正
確に管理することが可能となり半導体装置の品質を向上
させるという効果を有するものである。また、半導体装
置内に、特性を測定する半導体素子を形成しなくても良
くなり半導体装置の大きさを小さくする事ができるよう
になり数を多く一枚のウェハーに形成でき価格の低減と
いう効果を得られるものである6 さらには、スクライブライン領域に第2絶縁膜及び第3
絶縁膜のエツチングモニタ一部を設けた事によりフォト
エツチング工程の外観検査及びにエツチングの速度の測
定と膜形成時の膜厚測定が可能とし、半導体装置の製造
を前述の本発明の目的及び効果を損う事なく管理できる
ものにした。
In addition, by forming the second and third insulating films in the scribe line area except for a part of the etching monitor, the same film structure as the semiconductor device was achieved, so the gate electrode and first insulating film were formed.
The accuracy of the photolithography process for patterning the 21st conductive wiring and the second conductive wiring has also improved, and it has become possible to form patterns with the same shape and dimensions as those of semiconductor devices. As an effect of this, the characteristics of the semiconductor element used to measure the characteristics of the semiconductor device formed in the scribe line region match well with the characteristics of the semiconductor element used to measure the characteristics of the semiconductor device and inside the semiconductor device, making it easier to manufacture semiconductor devices. This has the effect of enabling more accurate management and improving the quality of semiconductor devices. In addition, it is no longer necessary to form semiconductor elements whose characteristics are to be measured in the semiconductor device, and the size of the semiconductor device can be reduced. Many can be formed on a single wafer, resulting in a reduction in cost. 6 Furthermore, a second insulating film and a third insulating film are formed in the scribe line region.
By providing a portion of the etching monitor for the insulating film, it is possible to inspect the appearance of the photoetching process, measure the etching speed, and measure the film thickness during film formation, thereby improving the manufacturing of semiconductor devices. We made it possible to manage it without any damage.

本発明の効果は、以上述べたように構造によるものであ
り半導体装置に使用されるゲート電極・導電配線・絶縁
膜・パッシベーション膜の種類・材質、膜厚、加工方法
、形成方法に関係なく有効なものである。また本発明の
効果は、実施例のゲート電極1層導電配線2層の半導体
装置以外の構造のゲート電極2層の半導体装置から導電
配線1層及び3層以上の半導体装置に応用しても全く同
様の効果を得られるものである。
As described above, the effects of the present invention are due to the structure and are effective regardless of the type, material, film thickness, processing method, and formation method of the gate electrode, conductive wiring, insulating film, and passivation film used in the semiconductor device. It is something. Further, the effects of the present invention are completely obtained even when applied to semiconductor devices with two layers of gate electrodes and semiconductor devices with one layer of conductive wiring and three or more layers of conductive wiring, other than the semiconductor device with one layer of gate electrode and two layers of conductive wiring as in the embodiment. Similar effects can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例のスクライブライン領域の断面
図。 第2図は本発明の実施例の各種パターンがないスクライ
ブライン領域の断面図。 第3図は本発明の実施例の第2絶縁膜と第3絶縁膜の一
部除去領域の平面図。 12・・・第2絶!!膜のエツチングモニタ一部13・
・・第3絶縁膜のエツチングモニタ一部以上 出願人 セイコーエプソン株式会社 代理人 弁理士 上 (卯 雅 誉(他1名)半導体基
板 LOGOS酸化膜 ゲート電極 第2絶縁膜 第1導電配線 第3絶縁膜 第2導電配線 パッシベーション膜 溝部 スクライブライン領域 半導体装置
FIG. 1 is a sectional view of a scribe line area in an embodiment of the present invention. FIG. 2 is a cross-sectional view of a scribe line area without various patterns according to an embodiment of the present invention. FIG. 3 is a plan view of a partially removed region of the second insulating film and the third insulating film in the embodiment of the present invention. 12...Second best! ! Membrane etching monitor part 13.
・・Etching monitor of the third insulating film Part or more Applicant: Seiko Epson Co., Ltd. Agent Patent attorney (Masaho Usa (and one other person)) Semiconductor substrate LOGOS oxide film Gate electrode Second insulating film First conductive wiring Third insulation film second conductive wiring passivation film trench scribe line region semiconductor device

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板上に形成されたLOCOS酸化膜を第
1絶縁膜として有した半導体装置において、スクライブ
ライン領域を第2絶縁膜と第3絶縁膜とパッシベーショ
ン膜で被覆した事を特徴とする半導体装置。
(1) A semiconductor device having a LOCOS oxide film formed on a semiconductor substrate as a first insulating film, in which a scribe line region is covered with a second insulating film, a third insulating film, and a passivation film. Device.
(2)前記パッシベーション膜を前記半導体装置の周囲
に沿って線状に除去し溝部を形成した事を特徴とする請
求項1記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the passivation film is removed linearly along the periphery of the semiconductor device to form a groove.
(3)前記パッシベーション膜をスクライブライン領域
の中に前記LOCOS酸化膜のパターンとゲート電極の
パターンと前記第2絶縁績のパターンと第1導電配線の
パターンと前記第3絶縁膜のパターンと第2導電配線の
パターンが形成された領域の上部のみに形成した請求項
1又は請求項2記載の半導体装置。
(3) Insert the passivation film into the scribe line area, including the LOCOS oxide film pattern, the gate electrode pattern, the second insulation pattern, the first conductive wiring pattern, the third insulation film pattern, and the second insulation film pattern. 3. The semiconductor device according to claim 1, wherein the conductive wiring pattern is formed only on the upper part of the region.
(4)前記第2絶縁膜の一部と前記第3絶縁膜の一部を
除去した領域を配した事を特徴とする請求項1、請求項
2又は請求項3記載の半導体装置。
(4) The semiconductor device according to claim 1, 2, or 3, further comprising a region in which a part of the second insulating film and a part of the third insulating film are removed.
JP63196499A 1988-08-06 1988-08-06 Semiconductor device Pending JPH0245956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63196499A JPH0245956A (en) 1988-08-06 1988-08-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63196499A JPH0245956A (en) 1988-08-06 1988-08-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0245956A true JPH0245956A (en) 1990-02-15

Family

ID=16358776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63196499A Pending JPH0245956A (en) 1988-08-06 1988-08-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0245956A (en)

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