JPH0245846A - Data processing system - Google Patents

Abstract

PURPOSE:To prevent malfunction due to a cache memory access by outputting the data of an added system to a data processing means without interposing a cache memory. CONSTITUTION:When a memory access request is generated, an MPU11 accesses a cache memory 12 and outputs address information. Next, the MPU11 is on standby until the cache memory 12 executes hit or miss, and is judged whether an NCA (non-cacheble area) signal 5 is outputted from an AND gate 4 or not. In the case of YES (when the signal is outputted), the memory access request is judged to be a non-cacheble area. After that, the MPU11 directly accesses a system memory 1 and executes data processing. On the other hand, as the result of the judgement, in the case of NO, an access to the cache memory 12 is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system that performs data processing with a cache memory interposed, and in particular, to a data processing system that includes a memory device having a non-cacheable area such as an I10 area. This relates to cache memory access control when expanding memory.

[Conventional technology]

FIG. 4 is a block diagram illustrating the memory environment of a conventional data processing device, in which 11 is a microprocessor unit (MPLI) serving as data processing means, cache memory 12. It is composed of a first memory system 13, a third memory system 14, etc., and each first memory system 13. Third
The memory system 14 has a non-cashable area 13a.
, 14a, respectively.

In addition, non-cashable areas (NCA) 13a, 14
A stores data such as the I10 area whose consistency with the cache memory 12 cannot be guaranteed.

Next, the non-cashable area (NCA) 13a, 1
Access to 4a will be explained.

Non-cashable area (NCA) 13a.

14a, the cache memory 12 needs to directly or indirectly recognize that caching is not allowed.

Therefore, when adding, for example, a third memory system 14 having a non-cacheable area 14a to an already constructed system as shown in FIG. The bull area (NCA) 13a can be recognized because it has already been stored, but the third memory system 1 to be added
Since the non-cashable area 14a of No. 4 is stored without A, it cannot be recognized.

Therefore, when accessing the non-cacheable area 14a of the third memory system 14, the MPU 11 accesses the cache memory 12 without notifying the cache memory 12 that it is the non-cacheable area 14a. The 4i area 14a is cached (data is taken into the cache memory 12).

In this way, the MPU 11 operates on the third. Since the non-cacheable area 14a of the memory system 14 is not stored,
The non-cacheable area 14a is accessed as a normal memory area.

When the cache memory 12 misses (desired data is not obtained), the data in the non-cacheable area 14a is transferred to the cache memory 12.
At the same time, it is sent to the MPU 11.

For example, if this data is data in the I10 area, the data is frequently rewritten by other devices, so the contents of the cache memory 12 for that data are stored in the non-cacheable area 1 of the third memory system 14.
It will no longer be possible to retain several pieces of data with the contents of 4a. In this state, if the MPU 11 accesses the same area, the cache memory 12 will be hit.
In reality, data whose content is different from the content of the non-cacheable area 14a (if it has already been rewritten) is sent from the cache memory 12 to the MPU 11.

[Problem to be solved by the invention]

In this way, the MPUI 1 accesses the non-cacheable area 14a that is not recognized by the cache memory 12, and the same non-cashable area 14a is accessed for the first time.
When accessing a, data on the cache memory 12 that is different from the actual contents of the non-cacheable area 14a is processed by the MPU II, resulting in a serious problem that the system processing in the MPU 11 malfunctions. For this reason, it is not possible to easily add a new system device (for example, a memory system) that has a non-cacheable area as described above to an already constructed data processing system, and it is not possible to easily add a new system device (for example, a memory system) to an already constructed data processing system. You will be forced to make changes.

This invention was made to solve the above problems, and when adding a system device having a non-cacheable area as described above to an already constructed data processing system, the non-cacheable area of the system device is It is an object of the present invention to provide a data processing system capable of detecting an area and processing data in a non-cacheable area of a desired system device without intervening a cache memory.

(Means for Solving the Problems) A data processing system according to the present invention includes a new system device having an unregistered non-cashable area;
Notifying means for notifying the data processing means of an access control signal indicating the existence of a non-cacheable area of a new system device based on address information output from the data processing means in parallel with an access request from the data processing means to the cache memory. It has been established that

[Operation] In this invention, when a new system device is built in the data processing system and the data processing means issues a request for access to the cache memory in order to access data from the new system device, the access request is processed in parallel with this access request. Then, predetermined address information for the new system device is output from the data processing means. At this time, the notification means causes the data processing means to notify an access control signal indicating the existence of a non-cashable area of the new system device based on the output address information, and thereafter the data processing means directly performs data processing for the new system device. Execute.

(Embodiment) FIG. 1 is a system block diagram showing an example of a data processing system showing an embodiment of the present invention, and the same components as in FIG. 4 are given the same reference numerals.

In this figure, 1 is a new system device, for example, a system memory (hereinafter also referred to as a memory system), which has an unregistered non-cashable area 1a and an NCA signal generator 1b which is a notification means of the present invention. There is.

The above system corresponds to a case where the system memory 1, which is a new system device, is newly added to the data processing system, and the MPU 11, which is a data processing means, uses the cache memory to start data access from the system memory 1. When an access request to the system memory 1 is issued, predetermined address information for the system memory 1 is output from the MPU 11 in parallel with this access request. At this time, the NCA signal generator 1b serving as the notification means is
Based on the address information output from the PU 11, the MPU 11 notifies an access control signal (NCA signal) indicating the existence of a non-cacheable area of a new system device, and thereafter data processing for the system memory 1 is performed using the MPUI.
I executes directly without the intervention of the cache memory 12.

Next, the operation will be explained.

The MPU 11 does not store the non-cashable area 1a of the memory system 1, which is the second memory system. Therefore, when the MPU 11 accesses the non-cacheable area 1a of the memory system 1, it accesses it as a normal memory area, so it first accesses the cache memory 12 and also accesses only the address to the first memory system 13 and the memory system 1. Give the address.

At this time, the cache memory 12 is accessed incorrectly because it is the first access. At this time, the NCA signal generator 1b of the memory system 1 (consisting of the logic circuit shown in FIG. 2, for example) generates the MCA signal from the output address.
The PU 11 is notified.

Therefore, the cache memory 12 recognizes that the next access will be made to the non-cacheable area 1a, and the system memory 12
access. In other words, the cache memory 12 directly accesses M from the system memory 1 without performing caching.
Send data to PU11.

FIG. 2 is a logic circuit diagram explaining the configuration of the NCA signal generator 1b shown in FIG.
AQ), the address line A2. Flip A3.

3a to 3C are NOR gates, and the NOR gate 3a outputs the NOR output of the address lines AO to A3 to the AND gate 4 at the subsequent stage. Noah gate 3b is address line A4-A7
The NOR output of is outputted to the AND gate 4 at the subsequent stage.

Further, the NOR gate 3c outputs the NOR output from the address lines A8 to A8 to the AND gate 4 at the subsequent stage.

AND gate 4 ANDs each NOR output from NOR gates 3a to 3c, and notifies MPU 11 of NCA signal 5.

Next, the operation of generating and outputting the NCA signal 5 will be explained.

For example, if the address space of the memory system 1 is from 3000 to 3FFFF in hexadecimal, and if the address space from 3000 to 300F is the non-cacheable area 1a, then the MPU 11 uses the cache memory 12
When accessing address lines AIl to Ao,
Address line A2. Outputs address information in which A3 is both "1" and all other address lines are "0".

As a result, each NOR output from the NOR gates t-3a to t-3c becomes "1", and the NCA signal 5 becomes the AND gate 4.
It is output from

As a result, the MPU 11 recognizes that the access address is a non-cacheable area, and thereafter directly exchanges data with the system memory 1 without using the cache memory 12.

In the above embodiment, the case where the system device to be added is a system memory device has been described as an example, but it may be another system device.

FIG. 3 is a flowchart illustrating an example of a system device access control procedure according to the present invention. In addition,(
1) to (7) indicate each step.

When a memory access request occurs, the MPU 11 accesses the cache memory 12 and outputs the address information (1). Next, the cache memory 12
2), then wait for N to be a hit or miss.
It is determined whether the CA signal 5 is output from the AND gate 4 (3), and if YES, the memory access request is determined to be a non-cacheable area (4).
accesses the system memory 1 directly (5) and performs data processing (6) On the other hand, if the determination in step (3) is No, accesses the cache memory 12 (7) and performs data processing (6).
).

〔Effect of the invention〕

As explained above, the present invention is based on a new system device having an unregistered non-cacheable area and address information output from the data processing means in parallel with an access request to the cache memory from the data processing means. Since a notification means for notifying the data processing means of an access control signal indicating the existence of a non-cacheable area of a system device is provided, a system device having a non-cacheable area, especially a system memory having a non-cacheable area is newly added. Even if an access control signal can always be generated upon an added system device access request.

Therefore, the data of the added system device can be output to the data processing means without intervening the cache memory, malfunctions due to cache memory access can be prevented, and a system memory having a non-cacheable area can be easily added.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing an example of a data processing system according to an embodiment of the present invention, FIG. 2 is a logic circuit diagram illustrating the configuration of the NCA signal generator shown in FIG. 1,
FIG. 3 is a flowchart illustrating an example of a system device access control procedure according to the present invention, and FIG. 4 is a block diagram illustrating a memory environment of a conventional data processing device. In the figure, 1 is a system memory, 1a is a non-cacheable area, 1b is an NCA signal generator, 11 is an MPU, and 12 is a cache memory. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Agent Masuo Oiwa (2 others) Figure Figure Figure

Claims (1)

[Claims] In a data processing system having a data processing means for processing data from a system device having a non-cacheable area via a cache memory, a new system device having an unregistered non-cacheable area and the data processing means notification means for notifying the data processing means of an access control signal indicating the existence of a non-cacheable area of the new system device based on address information output from the data processing means in parallel with an access request to the cache memory from the data processing means; A data processing system characterized by: