JPH0690684B2 - Data processing system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system for performing data processing by interposing a cache memory, and particularly to a memory device having a non-cacheable area such as an I / O area. The present invention relates to cache memory access control when a memory is expanded by adding the.

[Conventional technology]

FIG. 4 is a block diagram for explaining the memory environment of the conventional data processing apparatus. Reference numeral 11 is a microprocessor unit (MPU) which serves as data processing means, and includes a cache memory 12, a first memory system 13, and a third memory system 14. Etc., each of the first memory system 13 and the third memory system 14
Have non-cachable areas 13a and 14a, respectively.

In the non-cachable area (NCA) 13a, 14a, I /
Data such as the O area in which the consistency of the data with the cache memory 12 cannot be guaranteed is stored.

Next, access to the non-cacheable areas (NCA) 13a and 14a will be described.

It is necessary to directly or indirectly recognize that the cache memory 12 should not cache the non-cacheable areas (NCA) 13a and 14a.

Therefore, in the case where the third memory system 14 having the non-cacheable area 14a is added to the already constructed system as shown in FIG. 4, the MPU 11 has the non-cacher related to the already existing first memory system 13. The bull area (NCA) 13a can be recognized because it is already stored, but the non-cacheable area 14a of the third memory system 14 to be added cannot be recognized because it is not stored.

Therefore, when accessing the non-cacheable area 14a of the third memory system 14, the MPU 11 uses the cache memory.
Since 12 is accessed without notifying that it is the non-cacheable area 14a, the non-cacheable area 14a of the third memory system 14 is cached (cache memory 1
Data is imported to 2).

As described above, since the MPU 11 does not store the non-cacheable area 14a of the third memory system 14, the non-cacheable area 14a is accessed as a normal memory area.

When the cache memory 12 misses (a state in which desired data is not obtained), the data in the non-cacheable area 14a is fetched into the cache memory 12 (caching) and simultaneously sent to the MPU 11.

For example, if this data is data in the I / O area, that data is frequently rewritten by another device, so the contents of the cache memory 12 for that data are:
It becomes impossible to maintain the data consistency with the contents of the non-cacheable area 14a of the third memory system 14.
In this state, when the MPU 11 accesses the same area, the cache memory 12 hits, so in reality, the data of the content different from the content of the non-cacheable area 14a (when already rewritten) is stored in the cache memory 12
Sent to MPU11.

[Problems to be Solved by the Invention]

Thus, when the MPU 11 accesses the non-cacheable area 14a that is not recognized by the cache memory 12 and then accesses the same non-cacheable area 14a for the second time, the contents of the actual non-cacheable area 14a are Since the data on different cache memories 12 are processed by the MPU 11, there is a serious problem that the system processing in the MPU 11 malfunctions. Therefore, it is not possible to easily add a new system device (for example, a memory system) having the non-cacheable area as described above to the already constructed data processing system, and it is possible to significantly change the program and the circuit. It will be forced to change.

The present invention has been made to solve the above problems, and when adding a system device having a non-cacheable area as described above to a data processing system that has already been constructed, a non-cacheable system device is used. An object of the present invention is to obtain a data processing system capable of detecting a region and processing data of a non-cacheable region of a desired system device without interposing a cache memory.

[Means for Solving the Problems]

The data processing system according to the present invention includes a new system device having an unregistered non-cacheable area,
An informing means for informing the data processing means of an access control signal indicating the presence of the non-cacheable area of the new system device based on the address information output from the data processing means in parallel with the access request to the cache memory from the data processing means; Is provided.

[Action]

According to the present invention, when a new system device is built in a data processing system and the data processing means issues a request for access to the cache memory for data access from the new device, the data is processed concurrently with the access request. Predetermined address information for the new system device is output from the processing means. At this time, the notification means causes the data processing means to notify the data processing means of an access control signal indicating the existence of the non-cacheable area of the new system device based on the output address information, and thereafter the data processing means directly performs the data processing for the new system device. Run.

〔Example〕

FIG. 1 is a system block diagram showing an example of a data processing system showing an embodiment of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals.

In this figure, 1 is a new system device, for example, system memory (hereinafter also referred to as memory system)
Then, it has an unregistered non-cachable area 1a and an NCA signal generator 1b which is a notification means of the present invention.

The above system corresponds to the case where the system memory 1 which is a new system device is newly added to the data processing system, and the MPU 11 which is a data processing means starts the data access from the system memory 1 by using the cache memory. When an access request to 12 is issued, in parallel with this access request, the MPU 11 outputs predetermined address information for the system memory 1. At this time, the NCA signal generator 1b serving as the notification means notifies the MPU 11 of an access control signal (NCA signal) indicating the existence of the non-cacheable area 1a of the new system device based on the address information output from the MPU 11, and thereafter. System memory 1
Data processing for MPU11 directly cache memory 12
Execute without intervention.

Next, the operation will be described.

The MPU 11 does not store the non-cacheable area 1a of the memory system 1 which is the second memory system. Therefore,
MPU11 is non-cacheable area 1a of memory system 1
In order to access as a normal memory area, the cache memory 12 is first accessed, and only the address is transmitted to the first memory system 13 and the memory system 1.

At this time, the cache memory 12 is miss accessed because it is the first access. At this time, the NCA signal is notified from the output address to the MPU 11 by the NCA signal generator 1b of the memory system 1 (for example, constituted by the logic circuit shown in FIG. 2).

Accordingly, the cache memory 12 recognizes the next access as the non-cacheable area 1a and accesses the system memory 1. That is, the cache memory 12 directly sends the data from the system memory 1 to the MPU 11 without executing the caching.

FIG. 2 is a logic circuit diagram for explaining the configuration of the NCA signal generator 1b shown in FIG. 1, 2 is an inverter gate, and MP
Of the addresses (address lines A _{0 to} A ₁₁ ) from U11,
Invert address lines A ₂ and A ₃ . 3a~3c is a NOR gate, NOR gate 3a outputs a later stage of the AND gate 4 the NOR output of the address lines A ₀ to A _3. NOR gate 3b outputs a later stage of the AND gate 4 the NOR output of the address lines A ₄ to A _7. Additionally, NOR gate 3c address lines A ₈ ~
The NOR output of A ₁₁ is output to the AND gate 4 in the subsequent stage.

The AND gate 4 ANDs each NOR output from the NOR gates 3a to 3c and notifies the MPU 11 of the NCA signal 5.

Next, the generation and output operation of the NCA signal 5 will be described.

For example, the address space of the memory system 1 is 30 hexadecimal.
It has from 00 to 3FFFF, and 3000 to 3 of this address space
When the area up to 00F is non-cachable area 1a, MPU11
When accessing the cache memory 12, the address lines A _{0 to} A ₁₁ and the address lines A ₂ and A ₃ are both “1”.
Then, the address information in which all the other address lines are "0" is output.

As a result, each NOR output from the NOR gates 3a to 3c becomes "1", and the NCA signal 5 is output from the AND gate 4.

As a result, the MPU 11 recognizes that the access address is in the non-cacheable area, and thereafter directly exchanges data with the system memory 1 without interposing the cache memory 12.

In the above embodiment, the case where the added system device is the system memory device has been described as an example, but it may be another system device.

FIG. 3 is a flow chart for explaining an example of the system device access control procedure according to the present invention. In addition,
(1) to (7) show each step.

When a memory access request occurs, the MPU 11 accesses the cache memory 12 and outputs the address information (1). It then waits for cache memory 12 to hit or miss (2), then NCA signal 5
Is output from the AND gate 4 (3). If YES, it is determined that the memory access request is the non-cacheable area 1a (4), and then the MPU 11 directly accesses the system memory 1 (5), Perform processing.

On the other hand, if NO in step (3), the cache memory 12 is accessed (7), and the process returns to step (6).

〔The invention's effect〕

As described above, the present invention is based on the new system device having an unregistered non-cacheable area and the address information output from the data processing means in parallel with the access request to the cache memory from the data processing means. Since the notifying means for notifying the data processing means of the access control signal indicating the existence of the non-cacheable area of the system device is provided, the system device having the non-cacheable area, particularly the system memory having the non-cacheable area, is newly provided. Even if added, the access control signal can be generated at the time of requesting access to the added system device.

Therefore, the data of the added system device can be output to the data processing means without interposing the cache memory, the malfunction due to the cache memory access can be prevented, and the system memory having the non-cacheable area can be easily added.

[Brief description of drawings]

FIG. 1 is a system block diagram showing an example of a data processing system showing an embodiment of the present invention, FIG. 2 is a logic circuit diagram for explaining the configuration of the NCA signal generator shown in FIG. 1, and FIG. Is a flow chart for explaining an example of a system device access control procedure according to the present invention, and FIG. 4 is a block diagram for explaining a memory environment of a conventional data processing apparatus. In the figure, 1 is a system memory, 1a is a non-cacheable area, 1b is an NCA signal generator, 11 is an MPU, and 12 is a cache memory. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A data processing system having data processing means for processing data from a system device having a non-cacheable area via a cache memory, and a new system device having an unregistered non-cacheable area. An access control signal indicating the presence of a non-cacheable area of the new system device to the data processing means based on address information output from the data processing means in parallel with an access request to the cache memory from the data processing means. A data processing system comprising: a notifying unit for notifying.