JPH0244177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization detection device for extracting frame information from a received data stream.

When transmitting binary data, a predetermined number of bits constitute one frame, which is a unit of transmission, and a data stream is formed by consecutive frames. On the receiving side, in order to process the data, it is necessary to extract the frame information in the data stream.

An object of the present invention is to provide a frame synchronization detection device that can quickly extract accurate frame information from a received data stream by utilizing the autocorrelation of scrambling codes without inserting a frame synchronization signal into data. It is in realization.

An embodiment in which the present invention is applied to data transmission in a control system for a color television camera will be described below.

In FIG. 1, DT ₁ indicates data including camera control information in which one frame consists of 31 bits a ₁ to a ₃₁ . This data DT ₁ has 2t as a 1-bit cell. The data DT ₁ is scrambled by a scrambling code, for example, an M sequence SC ₁ when sent to the transmission path. M series SC ₁ has b ₁ to b ₃₁
It has a period of 31 bits. The 1-bit cell of each bit of b ₁ to b ₃₁ is designated as t, and
A redundant bit (“0” in this example) having t bit cells is added to each bit. t
Assuming that 1 bit cell is, the data DT ₁ mentioned above is
Each of the bits a ₁ to _{a 31} is arranged as two bits each. This means that for each bit of a ₁ to a ₃₁ ,
This means that an even parity bit is substantially added.

Also, to describe an example of the meaning of each bit of data DT ₁ , 8 bits _a1 to _a8 represent the subcarrier phase information, _a9 is the generation log flag bit, and _a10 is the tally flag bit. These are on/off control bits, _A11 is an internal/external flag bit, _A12 to _A15 are data addresses, and 8 bits _A16 to _A23 are camera control data such as white balance. 8 bits _a24 to _a31 are iris control data. This one
The frame data DT ₁ is repeatedly transmitted, and the type of camera control data is changed for each frame, and the data address also changes correspondingly. For example, there can be 16 types of camera control data in 16 consecutive frames of data. Of course, data transmission is performed repeatedly in units of 16 frames. Such data DT ₁ is generated by the camera control unit of the camera control system and given to the camera equipment attached to one or more color television cameras of the terminal via a cable etc., and this color television camera is remotely controlled. be done.

The M sequence is a type of pseudorandom sequence, and
It has a period of (n=2 ^k -1), and in one period (n
= 2 ^k-1 -1) "0"s and (n = 2 ^k-1 ) "1s" are included, and a sequence obtained by shifting the M sequence by K is added to the original M sequence. In the series, K is the period n
When it is divisible by , it is a sequence of all "0"s, and when it is not, it has a characteristic that it is a shifted version of the original M sequence. Furthermore, when the phase difference between two identical M sequences is 0, it has an autocorrelation function of 1, and otherwise it has an autocorrelation function of -1/n.

As already mentioned, the M sequence in this example is (n=31),
[1111100011011101010000100101100] is used.

Scrambling is performed by synchronizing one frame of data DT ₁ and the M sequence SC ₁ in which a redundant bit of "0" is added after each bit to an exclusive OR gate. TDT in FIG. 1 indicates one frame of the transmission data stream obtained by this scrambling. In FIG. 1, + means addition modulo 2.

Such transmission data TDT is descrambled on the receiving side. Descramble is performed using the same M
This is done by supplying the sequence SC ₁ to the exclusive OR gate with the same phase relationship as during scrambling. Under the assumption that no error occurs in the transmitted data TDT during transmission, after descrambling, data DT ₂ in which identical bits are located adjacent to each other as shown in FIG. 1 is obtained. As mentioned above, these two identical bits constitute one original bit of data. Then, the two adjacent bits after descrambling are supplied to the exclusive OR gate to perform a parity check. Under the assumption that the phase relationship between the transmitted data TDT and the M sequence during descrambling is correct and no transmission errors are included, by using even parity, all 31 parities in the parity check result will be It is “0”.

In other words, if all parities are 0, it can be known that the phase relationship between the transmission data TDT and the M sequence during descrambling is correct, and frame synchronization of the transmission data TDT can be detected from this phase relationship. Can be done.

FIG. 2 is a flowchart showing the process when detecting frame synchronization. First, the 62 bits of the received transmission data TDT are converted into an initial phase M sequence SC ₁
The data is descrambled and loaded into the shift register. After this descrambling, the parity between adjacent 62 bits is determined, and the number of "0" parities is counted. Next, it is determined whether this number N is (N31-α). here,
α is a tolerance value determined in consideration of transmission errors. If this condition is satisfied, framing is completed. In other words, frame synchronization can be generated from the phase of the M sequence during descrambling.

Also, if the above conditions are not met, shift (delay) the phase of the M sequence by 1 bit (t),
Descramble the 62 bits of the transmission data TDT again. In this case, the 62 bits are either the same as the 62 bits that were initially descrambled, or they are delayed by one or more frames of the 62 bits, and from the point of view of frame synchronization, This can be said to be the same data.
Next, the phase of the M sequence is restored to its original phase. Then, a parity check is performed on the 62 bits of data obtained by descrambling with the M sequence after the above-mentioned 1-bit shift, and the number of parities of "0" is counted. Regarding this number M,
It is determined whether (M31-α) holds.
If this holds true, the phase of the M sequence is delayed by one bit. Next, when it is descrambled again and parity counted, (N31−α)
is established, and the framing is completed.

When the above (M31-α) holds true, the M sequence at the time of descrambling has a phase that is one bit ahead of the one with the correct phase relationship, as shown by _SC11 in FIG.

Also, if (M31−α) does not hold, then
It is determined whether (M=31-1/2=15) holds. If this relationship is satisfied, then M
The phase of the sequence is shifted by one bit and returns to the beginning of the flowchart. If this (M=15) holds true, it means that a phase shift of an odd multiple of t exists with respect to the correct phase relationship. As an example, as shown by SC ₁₂ in FIG. 1, when an M sequence having a phase delay of 53 bits with respect to the correct phase relationship is descrambled with one bit delayed, data shown as DT ₂ ' is obtained. this data
The output obtained by supplying two adjacent bits of DT ₂ ' to the exclusive OR gate is indicated by PDT in FIG. This output
The PDT is nothing but the sum of the original M sequence consisting of b ₁ to _{b 31} delayed by 54 bits. Considering the nature of the M sequence, the output PDT is:
It is nothing but a phase-shifted version of the original M sequence, and therefore the number M of 0s is 15. Therefore, in such a case, framing is completed by shifting 1 bit and then shifting in units of 2 bits.

The above-described framing process on the receiving side is just one example, and simply the phase of the M sequence used for descrambling may be changed one bit (t) at a time. Also, (M31-α) or (M
=31-1/2) may be performed at the beginning of the frame synchronization detection process, and after correcting deviations of odd multiples of t, the process may proceed to the 2-bit shift process. Furthermore, in the explanation of Figure 1,
Although the phase relationship has been described based on one frame of the transmission data TDT, it goes without saying that the phase relationship between the transmission data TDT and the M sequence at the time of initial descrambling is not determined at all.

Furthermore, a frame synchronization detection device to which the present invention is applied will be explained with reference to FIG. In FIG. 3, 1 indicates a camera control unit as a transmitting side, and 2 indicates a camera equipment side as a receiving side, both of which are connected by a transmission cable 3. Although not shown, color video signals are also transmitted and received between the camera control unit 1 and the camera equipment side 2.

The data DT ₁ containing information for controlling the television camera as described above is supplied from the terminal 4 to the exclusive OR gate 5, and is also supplied to the M-sequence generation circuit 6.
The M sequence SC ₁ from is supplied to the exclusive OR gate 5, where it is scrambled.
Transmission data TDT obtained after scrambling is sent to the camera equipment side 2 via the transmission cable 3. The M-sequence generation circuit 6 is constituted by a linear feedback shift register circuit or a ROM (read only memory).

The transmission data TDT is supplied to each of exclusive OR gates 7 and 8 provided on the camera equipment side 2. In this case, the transmission data TDT is supplied to a bit clock recovery circuit (not shown) composed of a PLL circuit or the like, and the bit clock necessary for processing on the receiving side is extracted. Reference _numeral 9 denotes an M-sequence generation circuit that generates the same M-sequence SC ₁ as used for scrambling. The 62 bits after descramble that are supplied to the exclusive OR gate 8 and appear at their respective outputs are taken into shift registers 11 and 12. Two adjacent bits of the 62 bits stored in these shift registers 11 and 12 are each 31 bits.
The signal is supplied to each exclusive or gate, and a parity check is performed. The result is
Thirty-one parities are supplied to decoders 13 and 14, respectively.

This decoder 13 includes a counter that counts the parity of "0" and detects the number N, and (N
31-α) determination circuit, and provides the determination result to the control signal generation circuit 15. Also, decoder 1
4 is a counter that counts the parity of "0" and detects the number M, and (M31-α) and (M
=31-1/2), and provides the determination results to the control signal generation circuit 15.
The control signal generation circuit 15 generates a control signal for controlling the phase change of the M sequence SC ₁ generated from the M sequence generation circuit 9 based on the determination results from the decoders 13 and 14. At the same time, when the framing is completed, a frame synchronization signal with a determined phase is generated. Although not shown, the descrambled data is processed based on this frame synchronization signal, and the camera is controlled by various data obtained thereby.

The system configuration in Figure 3 is as follows: shift register 1
1, 12, decoders 13, 14, and a control signal generating circuit 15 as separate blocks, which can also be installed by a microcomputer programmed to operate according to the flowchart shown in FIG. It is possible to replace.

As described above, in the present invention, the scramble code (pseudorandom sequence) has an autocorrelation function that is significantly different when the phase difference is 0 and when it is not.
Since the framing is performed using , accurate framing can be performed. In addition, by performing scrambling processing, the original data
Even if _DT1 is all "0" or "1", bit clock reproduction (self-clock) on the receiving side can be performed correctly. Furthermore, even if frame synchronization is lost for any reason, it is possible to recover frame synchronization extremely quickly if the state of frame synchronization is monitored using parity. Therefore, data errors caused by loss of frame synchronization can be reduced, and stable frame synchronization can be achieved. The above-mentioned various effects achieved by this invention are as follows:
Some frame synchronization detection devices transmit a frame synchronization signal with a specific bit pattern added to data, and detect this bit pattern on the receiving side.
It's impossible.

Note that the parity added to the data is not limited to even parity as in the above embodiment, but may be odd parity. However, in the case of even parity, there is an advantage that the length of one bit of data need only be twice the length of one bit of M sequence. Furthermore, it is obvious that the present invention is applicable not only to the transmission of data for controlling a television camera, but also to other types of data transmission.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram used to explain frame synchronization detection according to the present invention, FIG. 2 is a flowchart used to explain frame synchronization detection according to the present invention, and FIG. 3 is a diagram of a frame synchronization detection device to which the present invention is applied. FIG. 2 is a block diagram of an example. 1 is a camera control unit, 2 is a camera equipment side, 5, 7, and 8 are exclusive OR gates, 6 and 9 are M-sequence generation circuits, and 11 and 12 are shift registers.

Claims (1)

[Claims] 1. One frame of data with parity bits added to each bit of a predetermined number N of data bits, and bits equal to the one frame of data with redundant bits added to each bit. In a frame synchronization detection device that receives a transmission data stream sent after being scrambled with a number of scramble codes and detects frame synchronization of the one frame data, a descramble circuit that descrambles data based on data; a parity check circuit that is supplied with an output data stream of the descramble circuit and performs a parity check on each data bit using a corresponding parity bit; a determination circuit that counts the number of positive parities among the outputs and determines whether or not this count output is larger than a predetermined threshold; a phase control circuit that controls the phase of the received data stream, and controls the phase control circuit until the count output obtains a determination output larger than the threshold value, and detects frame synchronization of the transmission data stream. Frame synchronization detection device.