JPH0243627A - Data processor - Google Patents

Abstract

PURPOSE:To execute the zero clear due to the operand full overlapping of an exclusive OR instruction at a high speed by sending the data read earlier to two inputs of a computing element when a first operand and a second operand are coincident, and after the first operand is read, even when the data of the second operand are rewritten to other CPU. CONSTITUTION:The title device has means 6 and 25 to detect that an XC (Exclusive OR Character) instruction is obtained and two operands 16 and 17 are coincident. In the XC instruction, when it is detected that the address of the first operand and the second operand is coincident, the data of one side operand read from the memory earlier are sent to an arithmetic unit, the data of other side operand are not sent to the arithmetic unit and instead, the data read earlier are sent to the arithmetic unit. Thus, the zero clear due to the operand full overlapping of the XC instruction can be executed at a high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a data processing device having an exclusive OR instruction, it is possible to perform zero clearing at high speed by operand full overlap of an exclusive OR instruction, and it always clears zero even in multiple CPUs. A means for detecting an instruction that is an exclusive OR instruction and whose two operands match, the purpose of which is to provide a data processing device that can obtain data;
The data processing device is characterized in that, when the instruction is detected, data of one of the operands is sent to two human power units of an arithmetic unit.

[Industrial application field]

The present invention relates to a data processing device having an instruction to perform exclusive OR.

There is an instruction that performs exclusive OR between a first operand and a second operand and stores the result in the first operand.

This instruction is abbreviated as an XC instruction.

What is XC?Exclusive ORCharacter
It is an abbreviation of

In a data processing device having an XC instruction, zero clearing is very often performed by matching the first and second operands. Therefore, it has been desired to perform zero clearing using the XC command at high speed.

[Prior Art] A case will be described in which, in an XC instruction, the first operand and the second operand are made to match and predetermined data on a storage device is cleared to zero. The XC instruction reads the data of the first operand, then reads the data of the second operand, performs an exclusive OR of the first operand data and the second operand data, and writes the result to the first operand.

Assume that the access data width is 8 bytes, and 1 block of 32 bytes is cleared to zero.

The most orthodox method is to actually read the first 8 bytes of data of the first and second operands, perform the operation, and write the resulting zero data.
Repeat until all data of the operand length is processed. To explain using the time chart of pipeline processing in Figure 2, the first operand is fetched in the first flow,
In the second flow, the fetch of the second operand and the operation of the XC instruction are executed, and in the third flow, zero data as the result of the operation is written. Since 3 flows are required to zero-clear the access data width, 12 flows are required to zero-clear one block.

In order to speed up this process, there is a method of exclusive ORing only the first data of the first and second operands and writing zero data obtained as a result of the operation to the entire range of the operand length. In pipeline processing, the first operand is fetched in the first flow, the second operand is fetched in the second flow, a match of the operands is detected, and the XC instruction is operated, and the operation result is written in the third flow. Fourth
Below the flow, write the zero data obtained in the third flow without fetching or calculating the operands.
Therefore, six flows are required to zero-clear one block.

There is also a method of detecting that the first and second operands match and writing zero data created by some means to the first operand without reading the data of the first and second operands. In pipeline processing, a match between operands is detected in the first flow, zero data is written without reading the operand data, and zero data is written sequentially up to the fourth flow. With this method, one block of zero clearing can be processed in four flows.

[Problem to be solved by the invention]

The method of exclusive ORing only the first data of the first and second operands and writing the zero data obtained as a result of the operation within the range of the operand length has no problem if there is only one CPU, but if there are two CPUs If the number exceeds 100, inconveniences will occur. If another CPU rewrites the data in the second operand after a CPU reads the first operand to execute an XC instruction and before it reads the second operand, zero data will be obtained as the result of the operation. do not have. Furthermore, since the first operation result is written sequentially from the 9th byte of the operand onward, data other than zero is written in the range that should be cleared to zero.

Next, the method of detecting that the first and second operands match and writing zero data to the first operand without reading the data of the first and second operands does not actually perform an operation, so The condition code generated when an operation is executed and the zero data that is the result of the operation must be created by some means other than the operation.

Therefore, the number of circuits required to achieve the above means increases, making it difficult to shorten the machine cycle.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that can execute zero clearing at high speed by operand full overlap of XC instructions, and can always obtain zero data even in multiple CPUs.

[Means to solve the problem]

In order to achieve the above object, there is provided a means for detecting that it is an XC instruction and two operands match, and a means for reading data of one of the operands from the memory when detected by the means, A data processing device is configured in which data is sent to two inputs.

[Effect]

In an XC instruction, when it is detected that the addresses of the first and second operands match, the data of one operand read from memory first is sent to the arithmetic unit, and the data of the other operand is sent to the arithmetic unit. Instead, the data read out first is sent to the arithmetic unit. Therefore, since exclusive OR is performed using the same data, zero data is always obtained. Furthermore, since the calculation is actually performed, there is no need to separately provide means for generating condition codes and zero data.

In addition to the first data in the operand, zero data obtained as a result of the operation is sequentially written.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

In the figure, ■ is an address generator, and the pace register 11
The operand address is calculated from the values of index register 12 and data register 13, and address register 1 is
Send to 4. 2 is a buffer memory from which data specified by the address register 14 is read. Flip-flop 5 is a register set signal generator, and operand data register 16 or 17 (hereinafter referred to as ODR) is a register set signal generator.
, 0DRz) are set to register set signals 51 and 5.
1" and sets ODR and 0DRz alternately. 3 is a data selector and sends out the data of the register specified by the register selection signal. 19 is a working register from which the second operand data is read. 4 is an XC arithmetic unit, and the first operand data of the working register 14 inputted to I1 of the arithmetic unit and the data inputted to I2 through the data selector 3 are controlled by exclusive logic. The sum is calculated and set in the result register 20.

The above configuration is the same as the conventional configuration, and the circuits added to implement the present invention are 7 flip-flops and 21 to 25 logic circuits. Conventionally, the register selection signal input to the data selector 3 is the output of the register set signal generator 5, and the operand data register to which data is newly set is selected. The AND circuit 25 generates an XC operand full overlap signal 53 from the XC detection signal 54 and the operand match signal 93.
Send out. Logic circuits 21 to 24 use the output of the register set signal generator 5 as the register selection signal 52 if the signal 53 is off. In other words, the operand data register in which data is set is selected. Further, if the signal 53 is on, the register selection signal 52 is not inverted where it should be inverted, and the operand data register in which data was set immediately before is selected.

Here, 32-byte zero clearing will be explained using the pipeline processing time chart shown in FIG. 2, as in the conventional example. In the A1 cycle, the first
Calculates the address of the operand and stores it in the address register 14.
Set to . B.

The data specified by the address register 14 is set in ODR in the cycle. Assume that the register set signal generator 5 sends a register set signal to the ODR. In this state, the Xc operand full overlap signal remains off, and the register switching signal generator 7 sends out a signal to select the register in which data is set. In the B1 cycle, the first operand data set in ODR is set in the working register 19.

In parallel with these processes, in the A2 cycle, the second operand address is calculated, and before setting this address in the address register 14, the second operand address and the first operand address set in the address register 14 are compared. , and sends out operand comparison signals 91-93. An XC operand full overlap signal 53 is sent out from the operand match signal and the XC detection signal in this signal.

In the B2 cycle, the second operand data is ODR.

Set to . Conventionally, the register switching signal generator 7 selects the ODR, but in the present invention, the register in which data was previously set is selected. In the B2 cycle, the first operand data of the working register 19 and the first operand data stored in the ODR sent from the data selector are subjected to an exclusive OR operation using the XC operation. Write zero data, which is the operation result, in the W cycle. In the fourth flow and subsequent flows, the zero data obtained in the second flow is sequentially written into the remainder of the first operand.

〔Effect of the invention〕

As explained above, in the present invention, when the first operand and the second operand match, even if the data of the second operand is rewritten by another CPU after reading the first operand, the data is read first. 2 of the arithmetic unit
Since it sends out to two inputs, zero data can be obtained. In addition, since the exclusive OR is actually performed only once at the beginning, there is no need to provide a means for creating a condition code or zero data, and the number of circuits can be reduced, making it possible to shorten the machine cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart of pipeline processing for explaining processing operations. In the figure: Address generator Buffer memory Data selector XC computing unit Register set signal generator Operand comparator Address register First operand data register Second operand data register Working register Set signal Register selection signal/XC operand full overlap signal 54...XC detection signal 93...Operand match signal 52 ・ 1 ・ 2 ・ 3 ・ 4 ・ 5 ・ 6 ・ 14 ・ 16 ・ 17 ・ 19 ・ 51. 53 ・ Dt At Bt Et Wt Dz Az f3z Ez 1AhD3/4J
Eli Ei Wa 04 A4134 fa J scoop? Concave

Claims (1)

[Scope of Claim] A data processing device having an arithmetic unit (4) that inputs data of first and second operands and performs an exclusive OR, which is an exclusive OR instruction and the two operands match. means (6 and 25) for detecting an instruction; and means (3, 7 and 21) for sending data of one of the operands to two inputs of the arithmetic unit (4) when the instruction is detected;
~25) A data processing device comprising: