JPH0243341B2 - - Google Patents
Info
- Publication number
- JPH0243341B2 JPH0243341B2 JP57140105A JP14010582A JPH0243341B2 JP H0243341 B2 JPH0243341 B2 JP H0243341B2 JP 57140105 A JP57140105 A JP 57140105A JP 14010582 A JP14010582 A JP 14010582A JP H0243341 B2 JPH0243341 B2 JP H0243341B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- heterojunction
- superlattice
- doped
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 7
- 239000000969 carrier Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 22
- 239000003362 semiconductor superlattice Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明はヘテロ接合を用いる半導体装置におい
てその接合界面の平坦性を増して電子の高移動度
化を図つたヘテロ接合素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a heterojunction element in which the flatness of the junction interface is increased in a semiconductor device using a heterojunction, thereby increasing the mobility of electrons.
バンドギヤツプの異なる２つの半導体のヘテロ
接合において、バンドギヤツプの大きい半導体の
みを選択的にＮ型にドープすることにより、ヘテ
ロ接合界面に移動度の大きい二次元電子が生じる
ことが知られている。通常、Ｎ型AlxGa(1-x)As
とGaAsとのヘテロ接合が利用され、マイクロ波
素子及びGaAs ICへの研究、開発がなされてい
る。以下、ヘテロ接合としてＮ型AlxGa(1-x)As
−GaAsを例にとつて説明する。 It is known that in a heterojunction of two semiconductors with different band gaps, two-dimensional electrons with high mobility are generated at the heterojunction interface by selectively doping only the semiconductor with a large band gap to N type. Usually N-type AlxGa (1-x) As
Heterojunctions between GaAs and GaAs are being used to research and develop microwave devices and GaAs ICs. Hereinafter, as a heterojunction, N-type AlxGa (1-x) As
-Explain using GaAs as an example.
第１図は従来のこの種のヘテロ接合断面を示
し、図において、１は半絶縁性GaAs基板、２は
高品質ノンドープGaAs、３はＮ型AlxGa(1-x)
As、４は前記GaAs２とAlxGa(1-x)As３とのヘテ
ロ接合界面に生じる二次元電子である。 Figure 1 shows a cross section of a conventional heterojunction of this type. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a high-quality non-doped GaAs substrate, and 3 is an N-type AlxGa (1-x) substrate.
As, 4 are two-dimensional electrons generated at the heterojunction interface between GaAs2 and AlxGa (1-x) As3.
このような従来のヘテロ接合においては、Ｎ型
AlxGa(1-x)As３の下にGaAs２がある場合は接合
界面での二次元電子４は高移動度を有するが、逆
にＮ型AlxGa(1-x)As３の上にGaAs２がある場合
には高移動度を有さない。これは、GaAs２の上
にAlxGa(1-x)As３を成長した時のヘテロ接合界
面は平坦であるが、AlxGa(1-x)As３の上にGaAs
２を成長したときのヘテロ接合界面は平坦でなく
なり、その結果として移動度の高速化が阻止され
ている。 In such a conventional heterojunction, N-type
When GaAs2 is below AlxGa (1-x) As3, two-dimensional electrons 4 at the junction interface have high mobility, but conversely, when GaAs2 is above N-type AlxGa (1-x) As3, does not have high mobility. This is because when AlxGa (1-x) As3 is grown on GaAs2, the heterojunction interface is flat, but when GaAs is grown on AlxGa (1-x) As3,
When 2 is grown, the heterojunction interface is no longer flat, and as a result, high-speed mobility is prevented.
本発明は以上の点に鑑みてなされたもので、バ
ンドギヤツプの異なる２つの半導体の超格子と、
該超格子を構成する半導体のうちバンドギヤツプ
の狭い半導体とのヘテロ接合を用いる半導体装置
において、上記超格子を一様にＮもしくはＰ型の
一導電型にドープし、ヘテロ接合界面に生じる二
次元電子もしくは二次元正孔を二次元キヤリアと
して用いることにより、ヘテロ接合界面の平坦性
を増してキヤリアの高移動度化を図つたヘテロ接
合素子を提供することを目的としている。 The present invention has been made in view of the above points, and consists of two semiconductor superlattices with different band gaps,
In a semiconductor device using a heterojunction with a semiconductor having a narrow band gap among the semiconductors constituting the superlattice, the superlattice is uniformly doped with one conductivity type of N or P type, and the two-dimensional electrons generated at the heterojunction interface are Alternatively, it is an object of the present invention to provide a heterojunction element that uses two-dimensional holes as two-dimensional carriers to increase the flatness of the heterojunction interface and achieve high carrier mobility.
すなわち、本発明に係るヘテロ接合素子は、バ
ンドギヤツプの大きい半導体と該半導体よりバン
ドギヤツプの小さい半導体からなる超格子全体を
一様にＮもしくはＰ型の一導電型にドープし、こ
の一導電型にドープされた超格子と上記バンドギ
ヤツプの小さい半導体とを接合して、その接合面
に生じる二次元キヤリアを利用することを特徴と
するものである。 That is, in the heterojunction device according to the present invention, the entire superlattice consisting of a semiconductor with a large bandgap and a semiconductor with a smaller bandgap than the semiconductor is uniformly doped with one conductivity type of N or P type, and doped with this one conductivity type. The present invention is characterized in that the superlattice formed by the lattice and the semiconductor having a small band gap are bonded together, and two-dimensional carriers generated at the bonding surface are utilized.
以下、本発明の実施例を図に基いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図は本発明による一実施例を示すヘテロ接
合断面図である。この実施例では、半絶縁性
GaAs基板１１にノンドープGaAs、AlAs超格子
１２をバツフア層として形成するとともに、この
GaAs、AlAs超格子１２上にＮ型のGaAs、AlAs
超格子１３をヘテロ接合素子を形成する電子の供
給層として形成し、さらに前記GaAs、AlAs超格
子１３上に高品質ノンドープGaAs１４を形成す
ることにより、Ｎ型GaAs、AlAs超格子１３と
GaAs１４間においてヘテロ接合を作成したもの
である。なお、１５は二次元電子である。 FIG. 2 is a sectional view of a heterojunction showing an embodiment according to the present invention. In this example, semi-insulating
A non-doped GaAs, AlAs superlattice 12 is formed as a buffer layer on a GaAs substrate 11, and this
N-type GaAs, AlAs on GaAs, AlAs superlattice 12
By forming the superlattice 13 as an electron supply layer for forming a heterojunction element, and further forming high quality non-doped GaAs 14 on the GaAs, AlAs superlattice 13, the N-type GaAs, AlAs superlattice 13 is formed.
A heterojunction is created between GaAs layers. Note that 15 is a two-dimensional electron.
このように、上記実施例のヘテロ接合による
と、AlxGa(1-x)Asと同じバンドギヤツプを有す
るGaAsとAlAsとの超格子１３の上にGaAs１４
を成長した場合のヘテロ接合界面は平坦となるた
め、第２図に示す如く、Ｎ型AlxGa(1-x)Asの代
りにＮ型のGaAsとAlAsとの超格子１３を用いる
ことにより、GaAs１４が上の構造においても電
子の移動度の高速化を達成することができる。 In this way, according to the heterojunction of the above embodiment, GaAs 14 is placed on the superlattice 13 of GaAs and AlAs having the same band gap as AlxGa (1-x) As.
Since the heterojunction interface is flat when grown, GaAs14 is grown by using a superlattice 13 of N-type GaAs and AlAs instead of N-type AlxGa (1-x) As, as shown in Figure 2. Even in the above structure, high electron mobility can be achieved.
なお、上述ではGaAs−AlxGa(1-x)Asヘテロ接
合の場合について説明したが、本発明はこれに限
定されるものではないことはいうまでもない。 Note that although the case of a GaAs-AlxGa (1-x) As heterojunction has been described above, it goes without saying that the present invention is not limited to this.
以上説明したように本発明のヘテロ接合素子
は、半絶縁性半導体基板上に、少くともバンドギ
ヤツプの大きい半導体と該半導体よりバンドギヤ
ツプの小さい半導体からなる一導電型にドープさ
れた超格子と、該ドープされた超格子の界面に形
成された上記超格子を構成する半導体のうちバン
ドギヤツプの小さい半導体からなるノンドープ半
導体とを備え、上記一導電型にドープされた超格
子と上記ノンドープ半導体とのヘテロ接合界面に
生じる二次元キヤリアを利用することにより、ヘ
テロ接合界面の平坦性が増して二次元キヤリアの
散乱が少なくなり、キヤリアの高移動度化を図る
ことができる効果がある。 As explained above, the heterojunction device of the present invention has a superlattice doped with one conductivity type consisting of at least a semiconductor with a large bandgap and a semiconductor with a smaller bandgap than the semiconductor, on a semi-insulating semiconductor substrate, and a non-doped semiconductor made of a semiconductor with a small band gap among the semiconductors constituting the superlattice formed at the interface of the superlattice, the heterojunction interface between the superlattice doped to one conductivity type and the non-doped semiconductor; By using the two-dimensional carriers generated in this process, the flatness of the heterojunction interface is increased, scattering of the two-dimensional carriers is reduced, and the mobility of the carriers can be increased.
第１図は従来の一例を示すヘテロ接合の断面
図、第２図は本発明による一実施例を示すヘテロ
接合の断面図である。
１１……半絶縁性GaAs基板、１２……ノンド
ープGaAs、AlAs超格子、１３……Ｎ型GaAs、
AlAs超格子、１４……高品質ノンドープGaAs、
１５……二次元電子。
FIG. 1 is a sectional view of a heterojunction showing a conventional example, and FIG. 2 is a sectional view of a heterojunction showing an embodiment of the present invention. 11... Semi-insulating GaAs substrate, 12... Non-doped GaAs, AlAs superlattice, 13... N-type GaAs,
AlAs superlattice, 14...High quality non-doped GaAs,
15...Two-dimensional electron.
Claims (1)
ヤツプの大きい半導体と該半導体よりバンドギヤ
ツプの小さい半導体からなる一導電型にドープさ
れた超格子と、該ドープされた超格子の界面に形
成された上記超格子を構成する半導体のうちバン
ドギヤツプの小さい半導体からなるノンドープ半
導体とを備え、上記一導電型にドープされた超格
子と上記ノンドープ半導体とのヘテロ接合界面に
生じる二次元キヤリアを利用することを特徴とす
るヘテロ接合素子。1. On a semi-insulating semiconductor substrate, a superlattice doped with one conductivity type consisting of at least a semiconductor with a large bandgap and a semiconductor with a smaller bandgap than the semiconductor, and the superlattice formed at the interface of the doped superlattice. It is characterized by comprising a non-doped semiconductor made of a semiconductor with a small band gap among the semiconductors constituting the lattice, and utilizing two-dimensional carriers generated at the heterojunction interface between the superlattice doped to one conductivity type and the non-doped semiconductor. heterojunction device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14010582A JPS5929462A (en) | 1982-08-10 | 1982-08-10 | Hetero-junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14010582A JPS5929462A (en) | 1982-08-10 | 1982-08-10 | Hetero-junction element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5929462A JPS5929462A (en) | 1984-02-16 |
| JPH0243341B2 true JPH0243341B2 (en) | 1990-09-28 |
Family
ID=15261050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14010582A Granted JPS5929462A (en) | 1982-08-10 | 1982-08-10 | Hetero-junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5929462A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5963769A (en) * | 1982-10-05 | 1984-04-11 | Agency Of Ind Science & Technol | High-speed semiconductor element |
| JPS61289673A (en) * | 1985-06-18 | 1986-12-19 | Sumitomo Electric Ind Ltd | Compound semiconductor device |
| JPS624366A (en) * | 1985-07-01 | 1987-01-10 | Fujitsu Ltd | Hot electron transistor |
| JPH0815212B2 (en) * | 1985-08-30 | 1996-02-14 | ソニー株式会社 | Semiconductor device |
| CN115207089B (en) * | 2022-07-19 | 2023-06-09 | 江苏华兴激光科技有限公司 | Radio frequency chip epitaxial wafer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132074A (en) * | 1979-04-02 | 1980-10-14 | Max Planck Gesellschaft | Hetero semiconductor and method of using same |
| JPS5676581A (en) * | 1979-11-26 | 1981-06-24 | Ibm | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
-
1982
- 1982-08-10 JP JP14010582A patent/JPS5929462A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132074A (en) * | 1979-04-02 | 1980-10-14 | Max Planck Gesellschaft | Hetero semiconductor and method of using same |
| JPS5676581A (en) * | 1979-11-26 | 1981-06-24 | Ibm | Semiconductor device |
| JPS577165A (en) * | 1980-06-17 | 1982-01-14 | Fujitsu Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5929462A (en) | 1984-02-16 |
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