JPH0242882A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent the turbulence of a picture by latching a synchronizing signal storage address inside a memory and executing a reading start from the storage address in synchronizing to an internal synchronizing signal when the synchronizing signal of a method output is made discontinuous and, thereafter, returned. CONSTITUTION:When a video disk player is ordinarily reproduced, a switch 17 is controlled so as to select a terminal (a) side, and a switch 18 is controlled so as to be turned off. Consequently, a digital video signal from a memory 14 is conducted through the switch 17 to a D/A converter 19, analog-converted and conducted out to a terminal 20. When a player is selected in a rapid traverse mode for a high-speed search, the switch 17 is made to select a terminal (b) side. Then, a signal at the terminal (b) side is level-restricted by a pedestal limiter 16, and it is made into a signal in which a synchronizing signal part is removed. At such a time, the switch 18 is controlled to be turned on, the internal composite synchronizing signal of an internal composite synchronizing signal generator 23 is superimposed on the signal conducted out from the switch 17, and the stable signal can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application)] The present invention relates to a synchronization circuit used in a signal processing circuit such as a video disc playback device.

(Prior art) Laser disc players use a constant linear velocity method (a type in which the rotational speed is controlled so that the relative velocity between the pickup and the recording line is kept constant) and a constant rotational speed method (a type in which the relative speed of the pickup and recording line is controlled to be constant). There is a type in which the recording signal density is adjusted between the outer and inner circumferences so that the relative speed of the line is kept constant. With the constant rotation speed method, one frame of video information is recorded per revolution of the recording line of the disk, and the synchronization signals are lined up in a straight line in the radial direction of the disk, but with the constant linear speed method, the synchronization signals are arranged in a straight line in the radial direction of the disk. It is rare to stand in line.

By the way, laser disc players are equipped with functions such as fast forward, fast reverse, and still playback. When performing fast forward, the pickup kicks in the radial direction, which allows the player to play an image at a position far away from the current image position. It has a mechanism that allows it to be played. The problem here is that, especially with the constant linear velocity method, the synchronization signals are not lined up in a straight line in the radial direction, so the synchronization signal after the kick is not permanently in phase synchronization with the synchronization signal before the kick. It is discontinuous. When such a discontinuity occurs, there is a disturbance in synchronization on the screen after the kick, a skew in horizontal synchronization, and wobbling or drifting in the upper limit of vertical synchronization, making the screen very difficult to see. This kind of phenomenon.

This problem may also occur with constant rotation speed systems.

(Problems to be Solved by the Invention) As described above, in conventional video disc players, the synchronization signal becomes temporarily discontinuous due to fast forwarding, fast reversing, etc., and when it is restored afterwards, the screen is disturbed. There are some shortcomings in terms of screen stabilization.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a synchronization circuit that can prevent the screen from being distorted even when the synchronization signal is temporarily disturbed and then restored.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes an analog-to-digital conversion means for digitally converting an input video signal, and an output of the analog-to-digital conversion means based on a write address from a write address generation section. a read address generator for providing a read address to the memory; a synchronization separation means for separating a synchronization signal of a digital image signal read from the memory; and synchronization from the synchronization separation means. composite synchronization signal generating means for obtaining an internal composite synchronization signal in synchronization with the signal; an output digital image signal from the memory is supplied to one terminal, and an output digital image signal from the memory is supplied to the other terminal; A first switch means supplied via a pedestal limiter section, a digital-to-analog conversion means for converting and deriving the output of the first switch means, and one terminal connected to the output of the first switch means. a second switch means connected to the second switch means, the other terminal of which is supplied with an internal composite synchronization signal from the composite synchronization signal generation means, and the synchronization signal of the output digital image signal from the memory is disturbed and becomes discontinuous; synchronous replacement means for controlling the first and second switch means to clamp the synchronization signal and superimpose the internal composite synchronization signal on the output digital image signal from the memory.

Then, when the synchronization signal of the output digital image signal from the memory is disturbed and goes into a discontinuous state and is restored to the primary continuous state, an address from a read address generation unit that provides the read address (address from which the restoration synchronization signal was read)
is latched by a register means, and the address latched in this register means is latched by a synchronization means,
The read address means is reset in synchronization with the internal composite synchronization signal to start the read address of the memory from this set address, and the first and second switch means are controlled to output digital output from the memory. This is to derive an image signal.

(Function) When the synchronization signal of the memory output becomes discontinuous and then recovers by the above means, the synchronization signal storage address inside the memory is latched, and the memory is synchronized with the internal synchronization signal that was being used until then. Since reading starts from the synchronization signal storage address, the synchronization signal of the digital image signal read from the memory and the internal synchronization signal used until just before are in phase synchronization, and the synchronization signal of the output digital image signal is Continuity will be maintained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A video signal reproduced from a video disc is input to the input terminal 11 and supplied to an analog-to-digital (hereinafter referred to as A/D) converter 12 . The digitized video signal is written to the memory 14 where a write address is specified based on the address from the write address generator 13. Data in memory 14 is read based on addresses from read address generator 15.

The memory 14 has a minimum capacity that can store data for one horizontal line, for example. The digital image signal read from the memory 14 is directly supplied to the terminal a of the switch 17, and the synchronous portion is clamped by the pedestal limiter 10, and then supplied to the other terminal of the switch 17.

The output of switch 17 is digital analog (hereinafter referred to as D/A).
) is introduced into a converter 19, converted into an analog signal, and delivered to an output terminal 20.

Furthermore, the output of the memory 14 is also supplied to the synchronous separation circuit 21. The synchronization signal separated here is guided to the control circuit 22. The control circuit 22 outputs a reset pulse RP in synchronization with the synchronization signal from the synchronization separation circuit 21 and supplies it to the internal composite synchronization signal generator 23 . As a result, in the internal composite synchronization signal generator 23, the internal counter is reset in phase synchronization with the reset pulse RP, and the output of the counter is used to generate an internal composite synchronization signal (having horizontal and vertical synchronization signals). This internal synchronization signal can be superimposed on the output of switch 17 if switch 18 is turned on.

Next, in this system, the read address generator 1
The read address obtained from 5 is also directed to register 24. This register 24 can latch the read address when the latch pulse LP is applied from the control circuit 22.

Further, the read address stored in this register 24 is loaded into the read address generator 15 when the load pulse LO is supplied from the control circuit 22 to the read address generator 15.

In this case, the read address generator 15 will start from the loaded address.

This embodiment is constructed as described above. The operation will be explained below with reference to the timing chart of FIG.

First, when the video disc player is playing normally, the switch 17 is controlled to select the terminal a side and the switch 18 is controlled to be turned off.

Therefore, the output digital image signal from the memory 14 is led to the D/A converter 19 via the switch 17, converted into an analog signal, and delivered to the output terminal 20.

Next, when the player is put into fast-forward mode for high-speed search, during the fast-forward period (period Tl shown in FIG. 2),
The synchronization signal of the reproduced image signal is disturbed.

For this reason, the synchronization signal of the signal output from the memory 14 cannot be used on the receiver side. Therefore, at this time, the switch 17 selects the terminal side. Then, the signal on the terminal side is limited by the pedestal level and becomes a signal from which the synchronizing signal portion has been removed. Further, at this time, the switch 18 is controlled to be on. Therefore, the internal composite synchronization signal is superimposed on the signal derived from the switch 17 and then introduced into the D/A converter 19.

Figure 2(a) shows the search period, and Figure 2(b) shows the search period.
shows the output signal from the memory 14, and the synchronization signal during the research period is disturbed. Further, FIG. 2(c) shows an internal composite synchronization signal, which maintains continuity by being phase-synchronized with the reproduction synchronization signal before the search. Further, (d) in the same figure shows the output of the pedestal limiter] 6, from which the synchronizing signal has been removed. FIG. 4E shows a state in which the internal composite synchronization signal (FIG. 1C) and the slope of the pedestal limiter 16 are combined.

Here, as the search period approaches the end, the relative speed between the disc and the pink-up is controlled to be almost the same as in normal playback. Because of this 2), the reproduced video signal is pinked up in a state close to normal. Therefore, the memory 14 outputs a signal having a stable signal as shown by period T2 in FIG. Here, since a synchronization separation output is obtained from the synchronization separation circuit 21, a latch pulse LP is obtained at this time.

The control circuit 22 resets, for example, a flip-flop when a search command is issued at the operation section, and waits for a synchronization signal to be input from the synchronization separation circuit 21 to the set section. As a result, it is possible to detect that the synchronization signal part A in FIG. 2 has been read from the memory, and store the address at that time in the register 24.

Then, when the search period ends, the load pulse LO is output in synchronization with the internal composite synchronization signal that has been employed on the output side so far. This means that the reproduction synchronization signal is read out from the memory 14 at the time when the internal composite synchronization signal is superimposed. Therefore, even if the switch 17 is switched to the terminal a side after this and the switch 18 is turned off,
The internal composite sync signal that was being played until just before and the memory 14
This means that continuity with the playback synchronization signal from In other words, the synchronization signal at point A in FIG.
This means that it is read out again at time B (internal composite synchronization signal) in Figure (c). Therefore, as shown in 2i1 (e), even immediately after the search period ends, the continuity of the synchronization signal is maintained in the video signal of the output unit 20, causing screen disturbances, skew, vertical jitter, etc. Never.

[Effects of the Invention] As explained above, the present invention can prevent the screen from being disturbed when the synchronization signal is temporarily disturbed and then restored.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart shown to explain the operation of the circuit shown in FIG. 12...Analog-digital converter, 13...Write address generator, 14...Memory, 15...Read address generator, 16...Pedestal limiter, 17°18...Switch, 19...・Digital analog converter, 21... Synchronization separation circuit, 22... Control circuit, 2
3... Internal composite synchronization signal generator, 24... Register. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] Analog-to-digital conversion means for digitally converting an input video signal; a memory into which the output of the analog-to-digital conversion means is written based on a write address from a write address generation section; and to the memory. a read address generation unit that provides a read address; a synchronization separation unit that separates a synchronization signal of the digital image signal read from the memory; and a combination unit that obtains an internal composite synchronization signal in synchronization with the synchronization signal from the synchronization separation unit. synchronization signal generating means; and first switch means, one terminal of which is supplied with an output digital image signal from the memory, and the other terminal of which is supplied with an output digital image signal from the memory via a pedestal limiter section. and a digital-to-analog conversion means for converting the output of the first switch means into an analog signal, one terminal of which is connected to the output of the first switch means, and the other terminal of the composite synchronization signal generation means. a second switch means to which an internal composite synchronization signal is supplied from the memory; and a second switch means for controlling the first and second switch means when the synchronization signal of the output digital image signal from the memory is disturbed and becomes discontinuous. a synchronization replacement means for clamping the synchronization signal on the output digital image signal from the memory and superimposing the internal composite synchronization signal on the output digital image signal from the memory; register means for latching the address from the read address generation unit (address from which the restoration synchronization signal was read) that provides the read address when the continuous state is restored; resetting the read address means in synchronization with the signal to start the read address of the memory from this set address, and controlling the first and second switch means to derive an output digital image signal from the memory. 1. A synchronization circuit characterized by comprising a synchronization means for synchronizing the synchronization circuit.