JPH0241550A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPH0241550A
JPH0241550A JP63193131A JP19313188A JPH0241550A JP H0241550 A JPH0241550 A JP H0241550A JP 63193131 A JP63193131 A JP 63193131A JP 19313188 A JP19313188 A JP 19313188A JP H0241550 A JPH0241550 A JP H0241550A
Authority
JP
Japan
Prior art keywords
processor
area
exchange
main memory
trace area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63193131A
Other languages
Japanese (ja)
Inventor
Shinji Kobayashi
信二 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63193131A priority Critical patent/JPH0241550A/en
Publication of JPH0241550A publication Critical patent/JPH0241550A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily discriminate the order in which inter-processor communication is performed by storing the clock value in a trace area at each time of inter-processor communication. CONSTITUTION:Required information is stored in a command area 6, a sequence number area 7, and a data area 8 on a main memory 4 for the purpose of performing inter- processor communication. At the time of information exchange between one processor and the destination processor, the information of a clock area 5 is stored together with the information in a trace area 100 (for exchange from a processor 11 to the processor 11), a trace area 101 (for exchange from the processor 11 to a processor 12), a trace area 102 (for exchange from the processor 11 to a processor 13), a trace area 110 (for exchange from the processor 12 to the processor 11), a trace area 111 (for exchange from the processor 12 to the processor 13), a trace area 112 (for exchange from the processor 12 to the processor 13), a trace area 120 (for exchange from the processor 13 to the processor 11), a trace area 121 (for exchange from the processor 13 to the processor 12), or a trace area 122 (for exchange from the processor 13 to the processor 13), and this processing is repeated at each time of inter-processor communication. Thus, the order in which inter-processor communication is performed is easily discriminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数のプロセッサから成るデータ処理装置に関
し、特に、そのプロセッサ間通信のトレース機能を改良
したデータ処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device comprising a plurality of processors, and more particularly to a data processing device with an improved tracing function for communication between processors.

〔従来の技術〕[Conventional technology]

従来のデータ処理装置における、この種のトレース機能
としては、お互いのプロセッサ間で管理しているシーケ
ンス番号をデータおよびコマンドとともに記録していた
This type of tracing function in conventional data processing devices records sequence numbers managed between processors together with data and commands.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のプロセッサ間通信のトレース機能はシー
ケンス番号を付したコマンドおよびデータを記録してい
るので、コマンドおよびデータが自己または他のプロセ
ッサと交換された順序は解析できるが時刻については不
明となっていた。また、3個所以上のプロセッサにおい
てコマンドまたはデータが入り乱れて交換されると、シ
ーケンス番号だけではその順序を判断することも不可と
なるケースも出てくる。
The conventional inter-processor communication trace function described above records commands and data with sequence numbers, so it is possible to analyze the order in which commands and data were exchanged with the processor itself or with other processors, but the time is unknown. was. Furthermore, if commands or data are exchanged in a mixed manner in three or more processors, there may be cases where it is impossible to determine the order using only the sequence number.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のデータ処理装置は、データ処理装置を構成する
複数のプロセッサのいずれからも読出書込可能なメイン
メモリと、各プロセッサ毎に存在しそのプロセッサから
のみ読出書込が行える複数のローカルメモリと、データ
処理装置の管理のために使用される時刻領域と、この時
刻領域の値を定期的に読取り、前記メインメモリに格納
する時計記録機構とを備え、前記各プロセッサが自分ま
たは他のプロセッサに対してデータおよびコマンドの交
換を行う際に、前記データおよびコマンドの一部または
全部とともに、前記メインメモリの時刻値を自分のプロ
セッサにある前記メインメモリに記録することを特徴と
する。
The data processing device of the present invention includes a main memory that can be read from and written to by any of the plurality of processors constituting the data processing device, and a plurality of local memories that exist for each processor and that can be read and written only by that processor. , a time area used for managing a data processing device, and a clock recording mechanism that periodically reads the value of this time area and stores it in the main memory, and each processor When exchanging data and commands, the time value of the main memory is recorded in the main memory of the own processor along with some or all of the data and commands.

〔実施例〕〔Example〕

第1図、第2図で本発明の一実施例を示す。 An embodiment of the present invention is shown in FIGS. 1 and 2. FIG.

システムバス1に複数個のプロセッサ11,12.13
が接続されており、各々のプロセッサ上の内部バス21
,22.23にローカルメモリ31.32,33が接続
されている。
Multiple processors 11, 12, 13 on system bus 1
is connected to the internal bus 21 on each processor.
, 22, 23 are connected to local memories 31, 32, 33.

時計管理機構2は時計機構3の値を読出し、メインメモ
リ4上の固定アドレスの時刻領域5に格納する。
The clock management mechanism 2 reads the value of the clock mechanism 3 and stores it in the time area 5 at a fixed address on the main memory 4.

プロセッサ間通信を行うためにメインメモリ4上のコマ
ンド領域6.シーケンス番号領域7.データ領域8に必
要な情報を格納し、自己または相手プロセッサに前記情
報の交換を行う際、前記情報とともに時刻領域5の情報
を該当するトレース領域100(プロセッサ11→11
)、101(プロセッサ11→12)、102(プロセ
ッサ11→13)、110 (プロセッサ12→11)
6. Command area on main memory 4 for inter-processor communication. Sequence number area 7. When storing necessary information in the data area 8 and exchanging the information with the self or the other processor, the information in the time area 5 is stored in the corresponding trace area 100 (processor 11→11
), 101 (processor 11 → 12), 102 (processor 11 → 13), 110 (processor 12 → 11)
.

111(プロセッサ12→13)、112 (プロセッ
サ12→13)、120 (プロセッサ13→11)、
121 (プロセッサ13→12)、122(プロセッ
サ13→13)に格納し、プロセッサ間通信の毎に上記
処理をくりかえし行う。
111 (processor 12 → 13), 112 (processor 12 → 13), 120 (processor 13 → 11),
121 (processor 13→12) and 122 (processor 13→13), and the above processing is repeated for each interprocessor communication.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、プロセッサ間通信を行う
毎にそのトレース領域に時計値を入れることにより、プ
ロセッサ間通信が行われた順序を容易に判定できる効果
を奏する。
As described above, the present invention has the effect that the order in which inter-processor communications are performed can be easily determined by inserting a clock value into the trace area each time inter-processor communications are performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の購成図、第2図は第1図中の
メインメモリ上の領域の割当て図である。 1・・・システムバス、2・・・時計管理機構、3・・
・時計段溝、4・・・メインメモリ、5・・・時刻領域
、6・・・コマンド領域、7・・・シーケンス番号領域
、8・・・データ領域、11,12,13・・・プロセ
ッサ、21゜22.23・・・内部バス、31,32,
33・・・ローカルメモリ。
FIG. 1 is a purchase diagram of an embodiment of the present invention, and FIG. 2 is an allocation diagram of areas on the main memory in FIG. 1. 1... System bus, 2... Clock management mechanism, 3...
・Clock step groove, 4... Main memory, 5... Time area, 6... Command area, 7... Sequence number area, 8... Data area, 11, 12, 13... Processor , 21゜22.23...internal bus, 31, 32,
33...Local memory.

Claims (1)

【特許請求の範囲】[Claims] データ処理装置を構成する複数のプロセッサのいずれか
らも読出書込可能なメインメモリと、各プロセッサ毎に
存在しそのプロセッサからのみ読出書込が行える複数の
ローカルメモリと、データ処理装置の管理のために使用
される時刻領域と、この時刻領域の値を定期的に読取り
、前記メインメモリに格納する時計記録機構とを備え、
前記各プロセッサが自分または他のプロセッサに対して
データおよびコマンドの交換を行う際に、前記データお
よびコマンドの一部または全部とともに、前記メインメ
モリの時刻値を自分のプロセッサにある前記メインメモ
リに記録することを特徴とするデータ処理装置。
A main memory that can be read and written by any of the multiple processors that make up the data processing device, multiple local memories that exist for each processor and that can be read and written only by that processor, and a main memory that can be used to manage the data processing device. and a clock recording mechanism that periodically reads the value of this time area and stores it in the main memory,
When each of the processors exchanges data and commands with itself or with another processor, the time value of the main memory is recorded in the main memory of the own processor along with some or all of the data and commands. A data processing device characterized by:
JP63193131A 1988-08-01 1988-08-01 Data processing device Pending JPH0241550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63193131A JPH0241550A (en) 1988-08-01 1988-08-01 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63193131A JPH0241550A (en) 1988-08-01 1988-08-01 Data processing device

Publications (1)

Publication Number Publication Date
JPH0241550A true JPH0241550A (en) 1990-02-09

Family

ID=16302788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63193131A Pending JPH0241550A (en) 1988-08-01 1988-08-01 Data processing device

Country Status (1)

Country Link
JP (1) JPH0241550A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06139116A (en) * 1991-05-01 1994-05-20 Tokyo Electric Co Ltd Program tracing system
JP2007293861A (en) * 2006-04-25 2007-11-08 Seagate Technology Llc Hybrid computer security clock
US7925894B2 (en) * 2001-07-25 2011-04-12 Seagate Technology Llc System and method for delivering versatile security, digital rights management, and privacy services
US8028166B2 (en) 2006-04-25 2011-09-27 Seagate Technology Llc Versatile secure and non-secure messaging
US8429724B2 (en) 2006-04-25 2013-04-23 Seagate Technology Llc Versatile access control system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06139116A (en) * 1991-05-01 1994-05-20 Tokyo Electric Co Ltd Program tracing system
US7925894B2 (en) * 2001-07-25 2011-04-12 Seagate Technology Llc System and method for delivering versatile security, digital rights management, and privacy services
JP2007293861A (en) * 2006-04-25 2007-11-08 Seagate Technology Llc Hybrid computer security clock
US8028166B2 (en) 2006-04-25 2011-09-27 Seagate Technology Llc Versatile secure and non-secure messaging
US8281178B2 (en) 2006-04-25 2012-10-02 Seagate Technology Llc Hybrid computer security clock
US8429724B2 (en) 2006-04-25 2013-04-23 Seagate Technology Llc Versatile access control system

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