JPH0241550A - Data processing device - Google Patents

Abstract

PURPOSE:To easily discriminate the order in which inter-processor communication is performed by storing the clock value in a trace area at each time of inter-processor communication. CONSTITUTION:Required information is stored in a command area 6, a sequence number area 7, and a data area 8 on a main memory 4 for the purpose of performing inter- processor communication. At the time of information exchange between one processor and the destination processor, the information of a clock area 5 is stored together with the information in a trace area 100 (for exchange from a processor 11 to the processor 11), a trace area 101 (for exchange from the processor 11 to a processor 12), a trace area 102 (for exchange from the processor 11 to a processor 13), a trace area 110 (for exchange from the processor 12 to the processor 11), a trace area 111 (for exchange from the processor 12 to the processor 13), a trace area 112 (for exchange from the processor 12 to the processor 13), a trace area 120 (for exchange from the processor 13 to the processor 11), a trace area 121 (for exchange from the processor 13 to the processor 12), or a trace area 122 (for exchange from the processor 13 to the processor 13), and this processing is repeated at each time of inter-processor communication. Thus, the order in which inter-processor communication is performed is easily discriminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device comprising a plurality of processors, and more particularly to a data processing device with an improved tracing function for communication between processors.

[Conventional technology]

This type of tracing function in conventional data processing devices records sequence numbers managed between processors together with data and commands.

[Problem to be solved by the invention]

The conventional inter-processor communication trace function described above records commands and data with sequence numbers, so it is possible to analyze the order in which commands and data were exchanged with the processor itself or with other processors, but the time is unknown. was. Furthermore, if commands or data are exchanged in a mixed manner in three or more processors, there may be cases where it is impossible to determine the order using only the sequence number.

[Means to solve the problem]

The data processing device of the present invention includes a main memory that can be read from and written to by any of the plurality of processors constituting the data processing device, and a plurality of local memories that exist for each processor and that can be read and written only by that processor. , a time area used for managing a data processing device, and a clock recording mechanism that periodically reads the value of this time area and stores it in the main memory, and each processor When exchanging data and commands, the time value of the main memory is recorded in the main memory of the own processor along with some or all of the data and commands.

〔Example〕

An embodiment of the present invention is shown in FIGS. 1 and 2. FIG.

Multiple processors 11, 12, 13 on system bus 1
is connected to the internal bus 21 on each processor.
, 22, 23 are connected to local memories 31, 32, 33.

The clock management mechanism 2 reads the value of the clock mechanism 3 and stores it in the time area 5 at a fixed address on the main memory 4.

6. Command area on main memory 4 for inter-processor communication. Sequence number area 7. When storing necessary information in the data area 8 and exchanging the information with the self or the other processor, the information in the time area 5 is stored in the corresponding trace area 100 (processor 11→11
), 101 (processor 11 → 12), 102 (processor 11 → 13), 110 (processor 12 → 11)
.

111 (processor 12 → 13), 112 (processor 12 → 13), 120 (processor 13 → 11),
121 (processor 13→12) and 122 (processor 13→13), and the above processing is repeated for each interprocessor communication.

〔Effect of the invention〕

As described above, the present invention has the effect that the order in which inter-processor communications are performed can be easily determined by inserting a clock value into the trace area each time inter-processor communications are performed.

[Brief explanation of the drawing]

FIG. 1 is a purchase diagram of an embodiment of the present invention, and FIG. 2 is an allocation diagram of areas on the main memory in FIG. 1. 1... System bus, 2... Clock management mechanism, 3...
・Clock step groove, 4... Main memory, 5... Time area, 6... Command area, 7... Sequence number area, 8... Data area, 11, 12, 13... Processor , 21゜22.23...internal bus, 31, 32,
33...Local memory.

Claims (1)

[Claims] A main memory that can be read and written by any of the multiple processors that make up the data processing device, multiple local memories that exist for each processor and that can be read and written only by that processor, and a main memory that can be used to manage the data processing device. and a clock recording mechanism that periodically reads the value of this time area and stores it in the main memory,
When each of the processors exchanges data and commands with itself or with another processor, the time value of the main memory is recorded in the main memory of the own processor along with some or all of the data and commands. A data processing device characterized by: