JPH0240953A - Semicustomized semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a semicustomized semiconductor integrated circuit in one chip by constituting an island-type semiconductor region having a conductivity type inverse to a substrate, at a wiring region position adjacent to a unit cell, and stretching a part of the island-type semiconductor region into the unit cell. CONSTITUTION:In a unit cell 1, a P-channel MOS transistor constituted of gate polycrystalline silicon 11a and a P-type diffusion layer 11b and an N- channel MOS transistor 12 constituted of gate polycrystalline silicon 12a and an N-type diffusion layer 12b are formed. In wiring regions on both outer sides of the unit cell 1, U-shaped island-type semiconductor regions 6 are formed. In the island-type semiconductor regions 6, impurity having a conductivity type inverse to a semiconductor substrate is diffused, and both ends of the regions 6 are stretched as far as to the inside of the unit cell 1. In this manner, a semicustomized semiconductor integrated circuit can be formed into a chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semi-custom integrated circuits, and particularly to semi-custom semiconductor integrated circuits including digital circuits and analog circuits.

[Conventional technology]

Conventionally, in the field of digital circuits, unit cells made of standardized resistors, transistors, and other elements are regularly arranged on a chip, and desired integration is achieved by forming arbitrary wiring according to various circuit designs. Semi-custom semiconductor integrated circuits called gate arrays are widely used.

For example, FIG. 5 is a plan view showing the configuration of a conventional CMOS gate array. Unit cell 1, usually defined as a rectangle
P-channel and N-channel MO3) transistors are formed inside the cell, and these unit cells 1 are regularly arranged to form a plurality of cell matrices 2. Also, cell matrix 2
A wiring area 3 is defined between them, and an input/output pad 5, a human output buffer circuit, etc. are arranged in the chip outer peripheral area 4. Then, by configuring various circuit blocks using one or more unit cells 1, assigning these to appropriate positions in the cell matrix 2, and connecting them using the wiring area 3, desired results can be realized. The circuit can be realized.

[Problem to be solved by the invention]

By the way, with the recent increase in the scale of semiconductor integrated circuits, for example, it is now required to configure a system in which the digital circuit was conventionally configured with three CMO elements and the analog circuit with bipolar elements on a single chip. Until then, circuit technology that utilizes CMOS processes for digital circuits for analog circuits and BiCMO3 (PiCMOS) process technology that simultaneously forms bipolar elements and CMO3 elements have been developed.

However, since the above-mentioned conventional configuration is designed assuming a digital circuit, all blocks defined using unit cells are gates for digital circuits, and analog A problem has arisen in that the circuit cannot be realized and the recent demands mentioned above cannot be met.

An object of the present invention is to provide a semi-custom semiconductor integrated circuit having a gate array configuration that can realize not only a digital circuit but also an analog circuit.

[Means for Solving the Problems] The semi-custom semiconductor integrated circuit of the present invention forms an island-shaped semiconductor region of a conductivity type opposite to that of the substrate at a wiring region position adjacent to a unit cell. It has a configuration in which a part of it extends inside the unit cell.

[Effect]

In the above-described configuration, the island-shaped semiconductor region can be used as a resistive element or a capacitive element, and by contact-connecting a part of the island-shaped semiconductor region to a unit cell, it becomes possible to configure the unit cell not only as a digital block but also as an analog block. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a first embodiment of the present invention.

In the figure, a P-channel MoS is defined inside a rectangle.
A cell matrix 2 is formed by arranging unit cells 1 including transistors and N-channel MO3I transistors in an array. Further, the plurality of cell matrices 2 are arranged with wiring regions 3 interposed therebetween. In the chip outer peripheral region 4, input/output pads 5, input/output buffer circuits, etc. are arranged.

The unit cell 1 is shown enlarged in FIG. Inside the unit cell l, there is a gate polycrystalline silicon lla and a P-type diffusion layer 11b.
A P-channel MOS transistor 11 made up of the above structure and an N-channel MOS transistor 12 made up of a gate polycrystalline silicon 12a and an N-type diffusion layer 12b are formed. In addition, in the wiring area 3 on both sides of the unit cell l, there are 3
A letter-shaped island-shaped semiconductor region 6 is formed. This island-shaped semiconductor region 6 has impurities of a conductivity type opposite to that of the semiconductor substrate diffused therein, and both ends thereof extend into the unit cell 1.

According to this configuration, the island-shaped semiconductor region 6 can be used as a diffusion resistance element or a diffusion capacitance element. Also,
Since both ends of this island-shaped semiconductor region 6 extend up to 300 degrees inside the unit cell 1, by adding a diffusion layer contact to this part, it is possible to create a configuration in which a resistor or a capacitor is connected to the unit cell 1. .

For example, as shown in FIG. 3(a), by forming internal wirings 7a, 7b, and 7c in the unit cell 1, and forming contacts 8 at both ends of the island-shaped semiconductor region 6, as shown in FIG.
), it becomes possible to make the unit cell 1 have a resistance, and it becomes possible to configure this unit cell 1 as an analog circuit block.

Note that the layer resistance ρ3 of the island-shaped semiconductor region 6 is 50 Ω/2, the capacitance value per unit area is 7
m, the resistance value R when used as a resistance element is
It is expressed as the following formula.

R=ρ, ·L/W, °, R=50x 200/10=I KΩ.

Similarly, the capacitance value C is calculated using the following formula 7 using the area A of the island-shaped semiconductor region 6 and the capacitance CA per unit area. Here, as shown in FIG. The island-shaped semiconductor region 6A formed on the side may be formed in a large area, and the resistance value is smaller than that in the configurations shown in FIGS. 2 and 3.
Alternatively, it becomes possible to obtain a large capacitance value. This island-shaped semiconductor region can be made as large as about 172 times the width of the wiring region 3.

〔Effect of the invention〕

As explained above, in the present invention, an island-shaped semiconductor region of a conductivity type opposite to that of the substrate is formed in a wiring region adjacent to a unit cell, with a portion of the island-shaped semiconductor region extending into the unit cell.
By contact-connecting the island-shaped semiconductor region to a unit cell, it can be used as a resistive element or a capacitive element, and the unit cell can be configured not only as a digital block but also as an analog block. This makes it possible to realize the integration of semiconductor integrated circuits including digital circuits and analog circuits into a single chip, which has been required in recent years. Furthermore, if this configuration is applied to a conventional CMOS gate array, it can be easily manufactured without changing the conventional process.

[Brief explanation of the drawing]

FIG. 1 is an overall plan view of an embodiment of the present invention, FIG. 2 is an enlarged plan view of a unit cell, FIG. 3 shows a state in which island-shaped semiconductor regions are connected, and FIG. FIG. 4 is an enlarged plan view of a modified example of a unit cell, and FIG. 5 is an overall plan view of a conventional semi-custom semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... Unit cell, 2... Cell matrix, 3... Wiring area, 4... Chip outer area, 5... Human output pad,
6... Island-shaped semiconductor region, 7a, 7b, 7c... Internal wiring, 8... Contact, 11... P channel MO
3) Transistor, 12...N channel MO3) Transistor. Figure 2 Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a semi-custom semiconductor integrated circuit formed by arranging unit cells including MOS transistors in an array to form a cell matrix and arranging a plurality of cell matrices via a wiring region, wiring adjacent to the unit cell. A semi-custom semiconductor integrated circuit characterized in that an island-shaped semiconductor region of a conductivity type opposite to that of a substrate is formed at a region position, and a part of this island-shaped semiconductor region extends within a unit cell.