JPH024016A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To keep a reference voltage constant by selecting plural resistance elements in the part, where a constant current flows, of a constant voltage generating circuit to supply the reference voltage to drive semiconductor integrated circuits connected in parallel, in accordance with the using rate of the semiconductor integrated circuit. CONSTITUTION:Plural semiconductor integrated circuits 1a-1n to be connected in parallel are driven by reference voltages VBB and VCB generated by a constant voltage generating circuit 2. A resistance RB 10 in the part, where a constant current IB flows, of the constant voltage generating circuit 2 is composed of plural resistances 10a-10c, and the resistance values are set to be 10a<10b<10c. A wiring 19 is commonly connected to the resistances 10a-10c, and at a wiring 20 side, according to the using frequencies of the semiconductor integrated circuits 1a-1n, the 20c and 20a are selected when the frequency is small and large, respectively. Thus, the reference voltage is made constant, and the performance lowering of a semiconductor element can be effectively prevented.

Description

[Detailed Description of the Invention] Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment First Embodiment of the Present Invention (Figure 1.2) Effects of the Invention [ Summary] To provide a semiconductor integrated circuit that can eliminate deviations in the voltage level of a reference voltage Vl11 and prevent performance deterioration by changing the resistance value of a constant voltage generation circuit depending on the usage rate of cells. In a semiconductor integrated circuit that has a large number of cells that perform logical operations and has a constant voltage generation circuit that supplies reference voltages necessary for the operation of the cells to these cells, the constant current of the constant voltage generation circuit is A plurality of resistance elements are provided in a portion where the current flows, and the resistance value can be selected by selecting one of the plurality of resistance elements and changing the wiring pattern according to the usage rate of the cells of the semiconductor integrated circuit. do.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit.1. For more information,.

The present invention relates to semiconductor integrated circuits applied to large-scale ECL gate arrays and the like.

In recent years, as systems become more integrated and integrated into one chip, gate arrays with a large number of gates are required. For example, ECL gate arrays are one of them, and are valued as logic LSLs for large computers that require high-speed performance. There is a tendency to become more integrated.

For this reason, large-scale ECL gate arrays have been developed, but in large-scale ECL gate arrays, the power supply current flowing through the constant voltage generation circuit that supplies the necessary reference voltage varies depending on the usage rate of the gates. Therefore, there is a problem that the level of the reference voltage (threshold voltage) for the differential input of the ECL shifts.
This needs to be adjusted.

[Conventional technology]

The ECL circuit has a reference voltage (-Vr) on one side of the differential input.
ef, hereinafter referred to as VIIB), and by applying a voltage higher or lower than the reference voltage to the other differential input, the transistor is turned on in the non-saturation region.
, is switched to OFF.

Therefore, in a constant voltage generation circuit, the normal power supply voltage (
It is necessary to generate the above-mentioned reference voltages V, 11, which are different from the reference voltages (VEE, GND).

In conventional large-scale ECL gate arrays, the power supply current flowing through the chip is predicted in advance during design, the power drop is calculated from the predicted power supply current, and the reference voltage VR
When designing a constant voltage generation circuit that creates level II,
The design takes into account the calculated power drop.

[Problem to be solved by the invention]

However, in such semiconductor integrated circuits,
At the time of design, the power supply circuit is designed by predicting the power supply current flowing through the chip, but in reality, the power supply current varies greatly depending on the usage rate of the cell, so there is less margin for the standard of the reference voltage VBB.

That is, FIG. 1 shows a circuit diagram of an ECL gate array, and in this circuit, the reference voltage ■.

is VBB= (IPRll +IIIRB +VaE(t
R++).

In such a circuit, when the gate usage rate changes, the current! , changes significantly. When I changes in this way, the reference voltage VI18 also changes from the relationship shown in the above equation, and the margin becomes smaller than the initially expected margin for the standard of the reference voltage Vl1m.

As a result, there is a problem in that the voltage level of the reference voltage (■) deviates from the standard due to slight manufacturing variations, resulting in a decrease in performance.

Therefore, in the present invention, the reference voltage (2) is adjusted by changing the resistance value RIl of the power supply circuit depending on the usage rate of the cell. It is an object of the present invention to provide a semiconductor integrated circuit that can eliminate deviations in power supply levels and prevent deterioration in performance.

(Means for Solving the Problems) In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a large number of cells that perform logical operations, and a constant voltage that supplies a reference voltage necessary for the operation of the cells to these cells. In a semiconductor integrated circuit having a generation circuit, a plurality of resistance elements are provided in a portion of the constant voltage generation circuit through which a constant current flows, and one of the plurality of resistance elements is provided according to the usage rate of cells of the semiconductor integrated circuit. The resistance value can be selected by selecting and changing the wiring pattern.

[Effect]

In the present invention, in the constant current flowing portion of the constant voltage generation circuit,
A plurality of resistance elements are provided, one of the plurality of resistance elements is selected according to the usage rate of the cell, and a resistance value R8 is selected by changing the wiring pattern.

Therefore, there is no difference in the level of the reference voltage regardless of the cell usage rate, and performance is improved.

〔Example] Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing an embodiment of the semiconductor integrated circuit according to the present invention, particularly an example of application to a large-scale ECL gate array.

First, the configuration will be explained.

FIG. 1 is a circuit diagram of a BCL gate array.

In this figure, 1a to 1n are ECL circuits, and E
CL circuits 1a to 1n correspond to a large number of cells that perform predetermined logical operations. Which cell of the ECL circuits 1a to 1rl is used varies depending on, for example, the user's design requirements.

The differential inputs of the ECL circuits 1a to 1n are, for example, "°H"'
--0.9V, "°L"'=1.5V are used, and the constant voltage generation circuit 2 is used for the ECL circuits 1a to 1n.
to the reference voltage VBII (about Vam-1.3V) and the current source intermediate voltage ■. , is supplied.

Note that the constant voltage generation circuit 2 supplies a reference voltage to GND (OV) and ■.

Since the voltage (-5.2V to -4.5V) is directly supplied from the outside by the external bin of the pancage, there is no need to consider voltage fluctuations. The current source intermediate voltage Vcs is a voltage that should be applied to the base of the current source transistor that constitutes a so-called current source, which is placed on the emitter side of an emitter-coupled transistor, and this also varies from the viewpoint of stability of ECL operation. required not to do so.

The constant voltage generation circuit 2 includes transistors 3 to 8 and a diode 9.
and resistors 10 to 17, and is a constant current power supply circuit that supplies a nearly constant current regardless of changes in ambient temperature or fluctuations in power supply voltage. On the other hand, 18 is a resistor R1 attached to the package, and the resistor 18 is present between the power supply circuit 2 and a GND line to which a GND level voltage from an external pin is applied. Therefore, the entire current supplied to the chip will flow through the resistor 18.

The value of the resistor 10 is determined according to the usage rate of the cell, and the layout pattern of the resistor 10 in the pan cage is shown in FIG.

That is, in FIG. 2, the resistor 10 includes a plurality of (three in this embodiment) resistive elements 10a to 10c having different resistance values.
The resistance values of the resistance elements 10a to 10c increase sequentially from the one on the left side in the figure. Before the gate array is manufactured according to the design specifications, the upper wiring (for example, /M line 19 in the figure is connected to the resistance elements 10a to 10c, but the lower wiring 20 is connected to the resistance elements 10a to 10c). 10c. This connection is made after the cell usage rate is determined. For example, once the cell usage rate is determined according to the user's design specifications, the connection is made using a placement program using CAD etc. Select the wiring pattern of the resistor elements 10a to 10c.For example, connect only the terminal 20c of the wiring 20 to the resistor 10c so that the resistance value is large when the usage rate is low, and the resistance value is small when the usage rate is high. The terminal 20a is connected to the resistor 10a so that

In the above configuration, the resistance value of the resistor 18 is R1, and the resistance value of the resistor 18 is R1.
Assuming that the current flowing through 8 is Il, the resistance value of resistor IO is R8, and the current flowing through resistor 10 is 2, the voltage level of reference voltage VIIB is given by the following equation as described above.

Vga= (Ip XRp + In xRB
+VIE) However, (2) is the voltage between the base and emitter of the resistor 13.As is clear from the above equation, as the gate scale of the ECL gate array increases, the power supply current 1. changes greatly, so the reference voltage VB
The voltage level of II also varies.

On the other hand, in this embodiment, in consideration of the fact that the power drop is large when the gate usage rate is high,
0 terminal 20a is connected to the resistor element 10a, and the resistance value of the resistor 10 is selected to be small.

Conversely, when the usage rate of the gate is small, the terminal 20b or the terminal 20c is connected to the resistive element 10b or the resistive element 10C, and the resistance value of the resistor 10 is selected to be large.

Therefore, the value of the resistor 10 is appropriately selected depending on the usage rate of the gate, and the level of the reference voltage VBIl expressed by the above equation can be kept constant. As a result, it is possible to increase the margin of the reference voltage VBB with respect to the standard level, and it is possible to prevent the performance of the ECL gate array from deteriorating.

In addition, la,...in, on one chip
2a...2nz, 3a+...3n3
, n, n2, and n3 gates are provided respectively, and the constant voltage generating circuit A is provided for the gates of la,...1n1, and the gates of 2a1...2nz are provided. For example, in a gate array in which the constant voltage generating circuit C is connected to the gates of the constant voltage generating circuits B, 3a, . . . 3n, for example, 1a+...ln.
, only a gates are used, 2a+...
・Use only b gates of 2nz, 3a,...
...3n.

When only 0 gates are used (however, a>b>
c) Resistance RBA% through which constant current flows in constant voltage generation circuits A, B, and C. The RIB and RBC resistance values are each RI
It is selected so that A<R1<Rac.

By selecting the resistance value in this way, each constant voltage generating circuit A,
The reference voltages output from B and C can be made to be approximately the same.

Furthermore, although the above embodiment is an example in which the present invention is applied to a gate array, other ICs may be used as long as they have a power supply circuit inside the IC package and supply a reference voltage to a large number of cells. Applicable.

[Effects] According to the present invention, the level of the reference voltage can be kept constant regardless of the usage rate of the cell, and the deterioration of the performance of the semiconductor element can be effectively prevented.

[Brief explanation of the drawing]

1.2 are diagrams showing an embodiment of the semiconductor integrated circuit according to the present invention, FIG. 1 is a circuit diagram of its ECL gate array, and FIG. 2 is a diagram showing its resistor wiring pattern. 1a-1n... ECL circuit, 2... Power supply circuit, 3-8... Transistor, 9... Diode, 10-18...・Resistance, 19.20...Wiring. Ichigo 7 Giants J's bottom 9 Q Enki training Pakushi and the 7th inning 2nd figure

Claims (1)

[Scope of Claims] A semiconductor integrated circuit in which a large number of cells that perform logical operations are arranged and has a constant voltage generation circuit that supplies a reference voltage necessary for the operation of the cells to these cells, comprising: A plurality of resistance elements are provided in a portion through which current flows, and the resistance value can be selected by selecting one of the plurality of resistance elements according to the usage rate of the cells of the semiconductor integrated circuit and changing the wiring pattern. A semiconductor integrated circuit characterized by: