JPH0239809B2 - - Google Patents

Info

Publication number
JPH0239809B2
JPH0239809B2 JP58103152A JP10315283A JPH0239809B2 JP H0239809 B2 JPH0239809 B2 JP H0239809B2 JP 58103152 A JP58103152 A JP 58103152A JP 10315283 A JP10315283 A JP 10315283A JP H0239809 B2 JPH0239809 B2 JP H0239809B2
Authority
JP
Japan
Prior art keywords
invalid
digit
carry
pattern
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58103152A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59226944A (ja
Inventor
Koichi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58103152A priority Critical patent/JPS59226944A/ja
Publication of JPS59226944A publication Critical patent/JPS59226944A/ja
Publication of JPH0239809B2 publication Critical patent/JPH0239809B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49936—Normalisation mentioned as feature only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
JP58103152A 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式 Granted JPS59226944A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58103152A JPS59226944A (ja) 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58103152A JPS59226944A (ja) 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式

Publications (2)

Publication Number Publication Date
JPS59226944A JPS59226944A (ja) 1984-12-20
JPH0239809B2 true JPH0239809B2 (OSRAM) 1990-09-07

Family

ID=14346526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58103152A Granted JPS59226944A (ja) 1983-06-09 1983-06-09 浮動小数点デ−タ加減算方式

Country Status (1)

Country Link
JP (1) JPS59226944A (OSRAM)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758974A (en) * 1985-01-29 1988-07-19 American Telephone And Telegraph Company, At&T Bell Laboratories Most significant digit location
JP2532083B2 (ja) * 1987-02-26 1996-09-11 株式会社日立製作所 フラグ発生回路
JPS63262723A (ja) * 1987-04-20 1988-10-31 Matsushita Electric Ind Co Ltd 演算処理方法
US4858165A (en) * 1987-06-19 1989-08-15 Digital Equipment Corporation Apparatus and method for acceleration of effective subtraction procedures by the approximation of the absolute value of the exponent argument difference
US4926369A (en) * 1988-10-07 1990-05-15 International Business Machines Corporation Leading 0/1 anticipator (LZA)
JP3187402B2 (ja) * 1989-07-26 2001-07-11 株式会社東芝 浮動小数点データ加減算回路
JPH087670B2 (ja) * 1989-07-28 1996-01-29 日本電気アイシーマイコンシステム株式会社 加算回路
JP2665067B2 (ja) * 1991-03-06 1997-10-22 甲府日本電気株式会社 浮動小数点加減算器
US5392228A (en) * 1993-12-06 1995-02-21 Motorola, Inc. Result normalizer and method of operation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983382A (en) * 1975-06-02 1976-09-28 International Business Machines Corporation Adder with fast detection of sum equal to zeroes or radix minus one
JPS5587243A (en) * 1978-12-25 1980-07-01 Fujitsu Ltd Zero detection system of adder output

Also Published As

Publication number Publication date
JPS59226944A (ja) 1984-12-20

Similar Documents

Publication Publication Date Title
JP2508912B2 (ja) 浮動小数点加算装置
US5889690A (en) Multiply-add unit and data processing apparatus using it
CA1324217C (en) Pipelined floating point adder for digital computer
EP0359809B1 (en) Apparatus and method for floating point normalization prediction
JP2008152360A (ja) ３項入力の浮動小数点加減算器
EP0328619B1 (en) Apparatus and method for using a single carry chain for leading one detection and for ''sticky'' bit calculation
US5341319A (en) Method and apparatus for controlling a rounding operation in a floating point multiplier circuit
JPH0239809B2 (OSRAM)
JPH10289096A (ja) 論理回路及び浮動小数点演算装置
EP0145465B1 (en) Floating-point addition/subtraction system
US5117384A (en) Method and apparatus for exponent adder
KR20180064975A (ko) 선두 제로 예측
JP4439060B2 (ja) 浮動小数点加算器
JP2517064B2 (ja) 非正規化数の処理方式
CN111290790A (zh) 一种定点转浮点的转换装置
US5805487A (en) Method and system for fast determination of sticky and guard bits
JPS59121539A (ja) 条件コ−ド決定回路
JP3950920B2 (ja) 積和演算器及びデータ処理装置
JP3555881B2 (ja) 演算回路とそのエラー検出方法
JPH08202530A (ja) 正規化前丸め手段を有する浮動小数点加減算処理装置及び方法
JPH03217938A (ja) 浮動小数点丸め正規化装置
JPS581244A (ja) 浮動小数点命令例外検出方法
JPH05204606A (ja) 浮動小数点演算方式および装置
JPS59125435A (ja) 浮動小数点演算方式
JPH0377534B2 (OSRAM)