JPH0238970B2 - - Google Patents

Info

Publication number
JPH0238970B2
JPH0238970B2 JP59104745A JP10474584A JPH0238970B2 JP H0238970 B2 JPH0238970 B2 JP H0238970B2 JP 59104745 A JP59104745 A JP 59104745A JP 10474584 A JP10474584 A JP 10474584A JP H0238970 B2 JPH0238970 B2 JP H0238970B2
Authority
JP
Japan
Prior art keywords
block
signal
control circuit
transfer
transmitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59104745A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61850A (ja
Inventor
Masaru Inamura
Masahiko Shoji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59104745A priority Critical patent/JPS61850A/ja
Publication of JPS61850A publication Critical patent/JPS61850A/ja
Publication of JPH0238970B2 publication Critical patent/JPH0238970B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
JP59104745A 1984-05-25 1984-05-25 Ｄｍａ送信転送制御方式 Granted JPS61850A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59104745A JPS61850A (ja) 1984-05-25 1984-05-25 Ｄｍａ送信転送制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59104745A JPS61850A (ja) 1984-05-25 1984-05-25 Ｄｍａ送信転送制御方式

Publications (2)

Publication Number Publication Date
JPS61850A JPS61850A (ja) 1986-01-06
JPH0238970B2 true JPH0238970B2 (es) 1990-09-03

Family

ID=14389026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59104745A Granted JPS61850A (ja) 1984-05-25 1984-05-25 Ｄｍａ送信転送制御方式

Country Status (1)

Country Link
JP (1) JPS61850A (es)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5424553A (en) * 1977-07-27 1979-02-23 Omron Tateisi Electronics Co Control system for data transfer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5424553A (en) * 1977-07-27 1979-02-23 Omron Tateisi Electronics Co Control system for data transfer

Also Published As

Publication number Publication date
JPS61850A (ja) 1986-01-06

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