JPH0235529U - - Google Patents
Info
- Publication number
- JPH0235529U JPH0235529U JP11340788U JP11340788U JPH0235529U JP H0235529 U JPH0235529 U JP H0235529U JP 11340788 U JP11340788 U JP 11340788U JP 11340788 U JP11340788 U JP 11340788U JP H0235529 U JPH0235529 U JP H0235529U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- whose
- signal
- inverting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 13
Description
第1図は本考案の原理図で、aはブロツク図、
bは回路図、第2図は本考案によるメタステーブ
ル検出回路の一実施例回路図、第3図はNOTゲ
ート20の内部回路図、第4図はNOTゲート2
1の内部回路図、第5図はフリツプフロツプの回
路図、第6図は第5図のフリツプフロツプのタイ
ムチヤート、第7図はメタステーブル状態を解決
する回路図、第8図は第7図回路によるタイムチ
ヤート、第9図は従来のメタステーブル検出回路
の回路図、第10図はNOTゲートの内部回路図
、第11図はNOTゲートの入出力特性図、第1
2図は第9図回路によるタイムチヤート、を示し
ている。
10…第1反転回路、11…第2反転回路、1
2,22,23,26…フリツプフロツプ、13
…定電圧素子、20,21,27,28…NOT
ゲート、24…EX―OR回路、25…ANDゲ
ート、29〜32…電源、TR1…第1トランジ
スタ、TR2…第2トランジスタ、TR3…第3
トランジスタ、TR4…第4トランジスタ、R1
〜R4…抵抗、D1〜D3…ダイオード。
Figure 1 is a diagram of the principle of the present invention, a is a block diagram,
b is a circuit diagram, FIG. 2 is a circuit diagram of an embodiment of a metastable detection circuit according to the present invention, FIG. 3 is an internal circuit diagram of NOT gate 20, and FIG. 4 is a diagram of NOT gate 2.
1's internal circuit diagram, Figure 5 is a flip-flop circuit diagram, Figure 6 is a time chart of the flip-flop in Figure 5, Figure 7 is a circuit diagram for solving the metastable state, and Figure 8 is based on the circuit in Figure 7. Time chart, Figure 9 is a circuit diagram of a conventional metastable detection circuit, Figure 10 is an internal circuit diagram of a NOT gate, Figure 11 is an input/output characteristic diagram of a NOT gate, and Figure 1 is a diagram of the input/output characteristics of a NOT gate.
FIG. 2 shows a time chart based on the circuit of FIG. 9. 10...First inversion circuit, 11...Second inversion circuit, 1
2, 22, 23, 26... flip-flop, 13
...constant voltage element, 20, 21, 27, 28...NOT
Gate, 24...EX-OR circuit, 25...AND gate, 29-32...power supply, TR1...first transistor, TR2...second transistor, TR3...third
Transistor, TR4...Fourth transistor, R1
~R4...Resistance, D1-D3...Diode.
Claims (1)
から信号を入力する第1トランジスタTR1と、
ベースが前記第1トランジスタTR1のコレクタ
へ接続され、第1トランジスタTR1のコレクタ
からの信号によりオン・オフ制御される第2トラ
ンジスタTR2と、該第2トランジスタTR2に
よりオン・オフ制御されるトーテムポール出力段
の第3及び第4トランジスタTR3,TR4とか
ら成り、且つお互いの反転論理レベルが異なる第
1及び第2反転回路10,11に、フリツプフロ
ツプ12の出力信号を入力し、同一タイミングに
おいて前記第1及び第2反転回路10,11から
の出力論理レベルが異なつたとき、メタステーブ
ル状態であると判定するメタステーブル検出回路
において、 第1反転回路10における第1トランジスタT
R1のコレクタ側と第2反転回路11における第
1トランジスタTR1のエミツタ側の何れか一方
又は両方に定電圧素子13を直列に接続したこと
を特徴とするメタステーブル検出回路。[Claims for Utility Model Registration] A first transistor TR1 to which a bias voltage is applied to the base and receives a signal from the emitter side;
a second transistor TR2 whose base is connected to the collector of the first transistor TR1 and whose on/off is controlled by a signal from the collector of the first transistor TR1; and a totem pole output whose on/off is controlled by the second transistor TR2. The output signal of the flip-flop 12 is input to the first and second inverting circuits 10 and 11, which are composed of the third and fourth transistors TR3 and TR4 of the stage and have different inversion logic levels, and a metastable detection circuit that determines that a metastable state exists when the output logic levels from the second inverting circuits 10 and 11 are different, the first transistor T in the first inverting circuit 10;
A metastable detection circuit characterized in that a constant voltage element 13 is connected in series to one or both of the collector side of R1 and the emitter side of the first transistor TR1 in the second inverting circuit 11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11340788U JPH0235529U (en) | 1988-08-31 | 1988-08-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11340788U JPH0235529U (en) | 1988-08-31 | 1988-08-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0235529U true JPH0235529U (en) | 1990-03-07 |
Family
ID=31353216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11340788U Pending JPH0235529U (en) | 1988-08-31 | 1988-08-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0235529U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014140123A (en) * | 2013-01-21 | 2014-07-31 | Hitachi Ltd | Metastability preventing synchronization circuit |
-
1988
- 1988-08-31 JP JP11340788U patent/JPH0235529U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014140123A (en) * | 2013-01-21 | 2014-07-31 | Hitachi Ltd | Metastability preventing synchronization circuit |
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