JPH0235529U

JPH0235529U -

Info

Publication number: JPH0235529U
Application number: JP11340788U
Authority: JP
Priority date: 1988-08-31
Filing date: 1988-08-31
Publication date: 1990-03-07

Description

[Brief explanation of drawings]

第１図は本考案の原理図で、ａはブロツク図、
ｂは回路図、第２図は本考案によるメタステーブ
ル検出回路の一実施例回路図、第３図はＮＯＴゲ
ート２０の内部回路図、第４図はＮＯＴゲート２
１の内部回路図、第５図はフリツプフロツプの回
路図、第６図は第５図のフリツプフロツプのタイ
ムチヤート、第７図はメタステーブル状態を解決
する回路図、第８図は第７図回路によるタイムチ
ヤート、第９図は従来のメタステーブル検出回路
の回路図、第１０図はＮＯＴゲートの内部回路図
、第１１図はＮＯＴゲートの入出力特性図、第１
２図は第９図回路によるタイムチヤート、を示し
ている。１０…第１反転回路、１１…第２反転回路、１
２，２２，２３，２６…フリツプフロツプ、１３
…定電圧素子、２０，２１，２７，２８…ＮＯＴ
ゲート、２４…ＥＸ―ＯＲ回路、２５…ＡＮＤゲ
ート、２９〜３２…電源、ＴＲ１…第１トランジ
スタ、ＴＲ２…第２トランジスタ、ＴＲ３…第３
トランジスタ、ＴＲ４…第４トランジスタ、Ｒ１
〜Ｒ４…抵抗、Ｄ１〜Ｄ３…ダイオード。 Figure 1 is a diagram of the principle of the present invention, a is a block diagram,
b is a circuit diagram, FIG. 2 is a circuit diagram of an embodiment of a metastable detection circuit according to the present invention, FIG. 3 is an internal circuit diagram of NOT gate 20, and FIG. 4 is a diagram of NOT gate 2.
1's internal circuit diagram, Figure 5 is a flip-flop circuit diagram, Figure 6 is a time chart of the flip-flop in Figure 5, Figure 7 is a circuit diagram for solving the metastable state, and Figure 8 is based on the circuit in Figure 7. Time chart, Figure 9 is a circuit diagram of a conventional metastable detection circuit, Figure 10 is an internal circuit diagram of a NOT gate, Figure 11 is an input/output characteristic diagram of a NOT gate, and Figure 1 is a diagram of the input/output characteristics of a NOT gate.
FIG. 2 shows a time chart based on the circuit of FIG. 9. 10...First inversion circuit, 11...Second inversion circuit, 1
2, 22, 23, 26... flip-flop, 13
...constant voltage element, 20, 21, 27, 28...NOT
Gate, 24...EX-OR circuit, 25...AND gate, 29-32...power supply, TR1...first transistor, TR2...second transistor, TR3...third
Transistor, TR4...Fourth transistor, R1
~R4...Resistance, D1-D3...Diode.

Claims

[Claims for Utility Model Registration] A first transistor TR1 to which a bias voltage is applied to the base and receives a signal from the emitter side;
a second transistor TR2 whose base is connected to the collector of the first transistor TR1 and whose on/off is controlled by a signal from the collector of the first transistor TR1; and a totem pole output whose on/off is controlled by the second transistor TR2. The output signal of the flip-flop 12 is input to the first and second inverting circuits 10 and 11, which are composed of the third and fourth transistors TR3 and TR4 of the stage and have different inversion logic levels, and a metastable detection circuit that determines that a metastable state exists when the output logic levels from the second inverting circuits 10 and 11 are different, the first transistor T in the first inverting circuit 10;
A metastable detection circuit characterized in that a constant voltage element 13 is connected in series to one or both of the collector side of R1 and the emitter side of the first transistor TR1 in the second inverting circuit 11.