JPH0234092A - Processing circuit for movement detection signal - Google Patents

Abstract

PURPOSE:To improve picture quality by converting a movement detection signal from a movement detection means into 1-bit signal by a level comparison means and supplying the result to a coefficient generator of integration type constitution so as to generate a coefficient. CONSTITUTION:A movement detection signal from a movement detection means 50 is converted into a 1-bit signal by a level comparison means 52 and fed to an integration type constitution coefficient generator 51 comprising D flip- flops 511a-511h, an adder 512 and a decoder 513 to generate a coefficient. Thus, an excellent coefficient corresponding to the movement is generated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to television receivers that perform high image quality processing such as motion adaptive scan line interpolation, such as so-called IDTV.
, relates to a circuit that processes motion detection signals.

[gA essentials of invention]

In this invention, a motion detection signal is converted into a 1-bit signal and then supplied to a coefficient generator having an integral type configuration to generate a coefficient, thereby generating a good coefficient corresponding to the amount of movement. It was made so that it could be done.

[Conventional technology]

FIG. 4 shows the configuration of an example of a television receiver.

In the figure, the video signal from the input terminal (62) is A
After being converted into a digital signal by a /D converter (63), it is supplied to a Y/C separation circuit (64) where it is separated into a luminance signal Y and a color signal C. The sampling frequency of the A/D converter (63) is, for example, 14M)lz.

The luminance signal Y output from the Y/C separation circuit (64) is
It is supplied to the scanning line interpolation circuit (65Y). The color signal C output from the Y/C separation circuit (64) is supplied to a chroma decoder (66) and demodulated in color. The time-division signal R-Y/B-Y of the red difference No. 11 RY1 blue difference signal B-Y output from the ROMA decoder (66) is supplied to the scanning line interpolation circuit (65C), and this scanning line interpolation circuit In addition to the main scanning line signals Ym, Rm-Ym/Bm-Ym, interpolated scanning line signals Yc, R,c-Yc/Bc-Yc are simultaneously output from (65Y) and (65C).

Further, the luminance signal Y output from the Y/C separation circuit (64) is supplied to a motion detection circuit (50), and the motion detection signal from this motion detection circuit (50) is sent to a coefficient generator (51).
supplied to Scanning line interpolation circuit (65Y), (65C
) is generated by this coefficient generator (51), and the value is changed depending on the magnitude of the motion detection signal. This coefficient generator (51) is composed of, for example, a ROM, and when the motion detection signal is supplied as an address value, the corresponding coefficient K is read out and output. FIG. 5 shows an example of the characteristics of the ROM.

The motion detection circuit (50) is configured as shown in FIG. In the figure, the luminance signal Y supplied from the Y/C separation circuit (64) is a field memo signal that constitutes a delay line.
J (401) and (402) in series. Field memory (401) and (
The delay time of the series circuit of 402) is 1 Freno, (26
3H+262H).

The input signal of the field memo IJ (401) and the output signal of the field memo IJ (402) are supplied to a subtracter (403) and subtracted therefrom. This subtractor (40
3) The frame difference signal output from Rover
After high-frequency noise components and dot interference components are removed by the filter (404), the absolute value circuit (405)
It is converted into an absolute value. The output signal of this absolute value circuit (405) is used as a motion detection signal.

Note that detecting motion from a frame difference signal in this manner is described in, for example, Japanese Patent Laid-Open No. 55-8124.

The scanning line interpolation circuit (65Y) is configured as shown in FIG. In the figure, a luminance signal Y supplied from a Y/C separation circuit (64) is supplied to a line memory <601) constituting a delay line. This line memo IJ (
The human input signal and output signal of the adder (601)
2) and is averaged, and this adder (602)
The output signal of K (K≦1
) and then supplied to an adder (604).

Furthermore, the luminance signal Y is supplied to a field memory (605) that constitutes a delay line. This field memo U (
605) is set to 263H. The output signal of this field memo U (605) is multiplied by (1-K) by a coefficient unit (606) and then by an adder (
604).

FIG. 8 is a diagram showing the scanning line structure in the time-vertical plane,
The circles indicate the scanning lines of each field. Memo the above human signal on h1 line! The output signal of J (601) is 11 field memo' The output signal of J (605) is J
Then, these signals h-J have the positional relationship shown in FIG.

In the scanning line interpolation circuit (65Y), the adder <60
2), and the output signal J of the field memo U (605) becomes an interpolated scanning line signal for the still image portion. Therefore, the adder (604) outputs an interpolated scanning line signal Yc in which the interpolated scanning line signals of the moving image part and the still image part are added at a ratio according to the degree of movement.

The interpolation scanning line is located at the position marked with ]: in FIG.

Further, the input signal Y is directly used as the main scanning line signal Ym.

Although the description is omitted, the scanning line interpolation circuit (65C) is similarly configured.

Main scanning line signals Ym, Rm -Ym/Bm output from the scanning line interpolation circuits (65Y) and (65C)
-Ym, interpolated scanning line signal Yc, Rc -Yc/
Bc-Yc are time compression circuits (67Y),
(67C). This time compression circuit (67
Y), (67C) is the main scanning line signal Ym.

Rm-Ym/Bm-Ym and interpolated scanning line signal Yc,
Rc-YC/BC-YC are each time-axis compressed to 1/2 and output continuously. In this case, the time compression circuit (67C) separately outputs a red difference signal and a blue difference signal.

The double-speed luminance signal and color difference signal output from the time compression circuits (67Y) and (67C) are converted into analog signals by D/A converters (68Y), (68R), and (68B), respectively.

D/A converter (68Y), (68R), (68B)
The double-speed luminance signal and color difference signal output from the multi-speed IJ circuit (73) are respectively supplied to the IJ circuit (73). The double-speed red, green, and blue signals R1G and B output from this matrix circuit (73) are sent to an amplifier (74R), (
Color picture tube (74G), (74B)
5), and non-interlaced scanning display with twice the number of scanning lines is performed on this color picture tube (75).

[Problem to be solved by the invention]

By the way, the motion detection signal outputted from the motion detection circuit (50) as shown in the example in FIG. 6 does not correspond to the amount of movement, but merely a difference in signal level. Therefore, the coefficients generated by the coefficient generator (51) correspond to the level difference and are not directly related to the amount of movement. For example, the coefficient K may become large even with a small amount of movement (it is determined that a large amount of movement has occurred).

For example, scanning line interpolation may be performed using extremely large coefficients for motion detection signals such as pulse-like noise, which may cause the image to look unnatural.

For example, when a part with a large difference in brightness level from the background moves, the coefficient K rises suddenly, making it impossible to perform smooth scanning line interpolation at the boundary between the still image part and the moving image part, resulting in the boundary part becoming unstable. Sometimes it looks natural.

Therefore, it is an object of the present invention to make it possible to generate a good coefficient corresponding to the amount of movement.

[Means to solve the problem]

This invention comprises a level comparison means (52) for converting the output signal of the motion detection means (50) into a 1-bit signal, and a coefficient generator (51) to which the output signal of the level comparison means (52) is supplied. The coefficient generator (51) includes a series circuit of a plurality of delay elements (511a) to (511h) to which the output signal of the level comparison means (52) is supplied, and the output signal of the level comparison means (52). and a plurality of delay elements (511
an adder (5!) that adds the output signals of a) to (511h);
2) and a decoder (513) that decodes the output signal of this adder (512) and outputs coefficients.

[Effect]

In the above configuration, the motion detection signal from the motion detection means (50) is converted into a 1-bit signal by the level comparison means (52). A plurality of delay elements (511a) to (511) of the coefficient generator (51) are supplied with this 1-bit signal.
h) and the adder (512) constitute a so-called integrator, and the output signal of the adder (512) is a signal corresponding to the amount of movement. Therefore, the coefficient generator (5
The decoder (513) (1) outputs good coefficients corresponding to the amount of movement.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In the figure, a motion detection signal from a motion detection circuit (50) is supplied to a level comparator (52). This level comparator (52) outputs a high level "1" signal when the motion detection signal is above the reference level, and a low level "0" signal when it is below the reference level. That is, this level comparator (52) converts the motion detection signal into a 1-bit signal.

The output signal of this level comparator (52) is the A of the changeover switch (531) constituting the time axis filter (53).
Supplied to the fixed terminal on the side. This changeover switch (531
) output signals from the D flip-flop (532), frame memory (533), and (53) that constitute the delay line.
4) Supplied to the series circuit. In this case, the delay time in the D flip-flop (532) is one sampling period (1714MH2). That is,
D flip-flop (532), frame memory (
The total number of samples in the series circuit of 533) and (534) is an odd number, and this series circuit causes an odd number of stages of delay.

The output signal of the frame memory (534) is supplied to the fixed terminal on the B side of the changeover switch (531). The changeover switch (531) is set to 7 with a duty of 50% as shown in the second diagram! The switching is controlled by a JHz signal, and the switching is performed alternately between the A side and the B side every sampling period (1/14 MHz). That is, the changeover switch (531) alternately selects the output signal of the level comparator (52) and the output signal of the frame memory (534>) for each sample.

Furthermore, the output signal of the level comparator (52) is supplied to the OR circuit (538) via a D flip-flop (535) constituting a delay line, and is supplied to the frame memory (538).
The output signal of 3) is sent directly to the OR circuit (53g) via a D flip-flop (536) that constitutes a delay line.
), and the output signal of the frame memo IJ (534) is directly connected to the D flip 7 which constitutes the delay line.
OR circuit (538) via 0 tube (537)
supplied to In this case, a D flip-flop (535
) to (537) are each set to one sampling period (1/14 MHz>).

In the above configuration, the output signal of the level comparator (52), frame memo! Suppose that the output signals of J (533) and (534) are as shown in FIG. 2A, E, and B, respectively. In this case, frame memory (533), (5
The output signals of 34) are each delayed by an odd number of stages (1 frame + 1 sample) (2 frames + 1 sample).

Since the changeover switch (531) is controlled by a 7 MHz signal as shown in the second figure, the output signal of the changeover switch (531) is as shown in figure C. In this case, the D flip-flop (532)
, frame memories (533), (534) are delayed by an odd number of stages, so the signal that passes through this series circuit twice is delayed by an even number of stages, and is not selected by the selector switch (531) and disappears. . For example, after the signal shown in Figure 2C passes through the series circuit, the signal C,,C3°C
3,... disappear without being selected.

Also, D flip 70 tube (535), (536),
The output signals of (537) are G, F, and H in Figure 2, respectively.
It becomes as shown in . In addition, in B, E, F, and H of the figure, the parts enclosed in parentheses indicate the parts where the current signal is missing.

In the end, in the OR circuit (5'38), B, E, F in Figure 2.

Since the signals in the time direction as shown by G and H are logically summed, the OR circuit (538) outputs a motion detection signal expanded in the time direction.

Further, in FIG. 1, the motion detection signal output from the OR circuit (538) of the time axis filter (53) is supplied to the coefficient generator (51). That is, the motion detection signal is sent to the D flip-flop (511a
) to (511h). The delay time of these D flip-flops <511a) to (511h) is each one sampling period (1/14MHz)
It is said that

The input signal of the D flip-flop (511a) and the output signal of the D flip-flops (511a) to (511h) are as follows.
They are added by an adder (512). In this case, the D flip-flops (511a) to (511h) and the adder (512> constitute a so-called integrator, and the output signal of the adder (512) is 0 (all input signals are at low level "0"). ”) to 9 (all human input signals are at high level “1”).

The output signal of this adder (512>) is sent to the decoder (51
3), and the coefficient K is output from this decoder (513). That is, as shown in FIG. 3, the output signal of the adder (512) is CO), C], 2
) , [3,4] (5,6] , [near, 8.9
], the coefficients are, for example, 0.
1/4.1/2.3/4 1 is output.

According to this example configured as above, the coefficient generator (5
1) is D7 lip 70-)p (511a) ~(51
1h), adder (512), decoder (513)
Since it has an integral type configuration, it is possible to generate a good coefficient K corresponding to the amount of movement.

Further, according to this example, the motion detection signal from the motion detection circuit (50) is converted into a 1-bit signal by the level comparator (52), and the time axis filter (53) is configured by 1-bit processing. Therefore, a signal expanded in the time direction can be obtained with a small memory capacity and a small number of operation bits.

Note that although the coefficient generator (51) in the above embodiment is configured using eight D flip-flops (511a) to (511h), the number is not limited to this. Can be set arbitrarily.

〔Effect of the invention〕

According to this invention, the motion detection signal from the motion detection means is converted into a 1-bit signal by the level comparison means and then supplied to the coefficient generator having an integral type configuration to generate coefficients.
It is possible to generate a good coefficient corresponding to the amount of movement. As a result, good scanning line interpolation can be performed, and image quality can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are explanatory diagrams, FIG. 4 is a block diagram of an example of a television receiver, and FIGS. The figure is a diagram for explaining the same. (50) is a motion detection circuit, (51) is a coefficient generator, (5
2) is a level comparator, (511a) to (511h) are D7 lip flops, (512) is an adder, (51
3) is a decoder. Agent Paige Ito
Hide Matsukuma's 'Hokanin'
&8 to Figure 1 77 "1 Dragon I's Eka-cho Coda Theory B Figure Figure 3-=) Triple Neili Orthography 1. Display of Incidents 1985 Patent Application No. 185169 2. Invention Name of motion detection signal processing circuit 3, relation to the case of the person making the correction Patent applicant address Tokyo Parts 8 Kitashina 6-7-35 Name (2
18) Sony Corporation Representative Director Noriyoshi Ohga 4, Agent 6, Number of hours of invention increased by amendment - Translational edge of vertical plane Figure 8 of 1 to 11

Claims (1)

[Scope of Claims] Level comparison means for converting the output signal of the motion detection means into a 1-bit signal, and a coefficient generator to which the output signal of the level comparison means is supplied, the coefficient generator comprising: a series circuit of a plurality of delay elements to which the output signal of the level comparison means is supplied, an adder for adding the output signal of the level comparison means and the output signal of the plurality of delay elements; 1. A motion detection signal processing circuit comprising a decoder that decodes and outputs coefficients.