JPH0229193A - Picture quality improve circuit for television video signal - Google Patents

Abstract

PURPOSE:To save an expensive 1-frame delay memory composed of three 1-line delay memories, a 260-line delay memory, and a 262-line delay memory memory and to reduce the cost of the whole of the title picture quality improving circuit by sharing the 1-frame delay memory between a noise reducing part and a scanning converting part which are adaptive to motion. CONSTITUTION:The picture quality improving circuit is equipped with first through third 1-line delay memories 5a-5c, a 260-line delay memory 6, and a 262-line delay memory 7 connected in a longitudinal line and is provided with a 1-frame delay memory which delays a two-to-one interlace television video signal composed of noise-reduction-processed components supplied from an input terminal IN through the noise reducing part for one frame in total. Further, this 1-frame delay memory is shared between the noise reducing part and the scanning converting part which are adaptive to the motion. Thus, the expensive 1-frame delay memory can be saved, and the cost of the circuit can be reduced.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a circuit for improving the image quality of television video signals used in high-definition television receivers and the like. (Prior art) High-definition (IDTV, HDTV) television receivers currently under development first convert received television video signals of existing standard formats such as NTSC into digital video signals, and in addition to Y/C separation. After performing various image quality improvement processes such as noise reduction, scan conversion, and contour compensation, the analog video signal is returned to the analog video signal and supplied to the display section. One of the image quality improvement processes described above is noise reduction processing that uses difference signals between adjacent frames. The noise reduction circuit that performs this processing is comprised of a subtracter 61, 62.1 frame delay memory 63, and a motion adaptive coefficient control section 64, as shown in FIG. A television video signal component consisting of components such as a luminance signal, a color difference signal, or three primary color signals R1G and B separated from the received television video signal is supplied to the input terminal IN. The television video signal of the current frame appearing at the input terminal IN and the television video signal of the previous frame outputted from the one-frame delay memory 63 are subtracted by the subtraction circuit 61, resulting in a difference signal between adjacent frames. This difference signal between adjacent frames includes a noise component randomly superimposed on the video signal and a component associated with movement on the display screen. The smaller this difference signal between adjacent frames becomes, the higher the probability that it is a noise component.
Therefore, in the motion adaptive coefficient control unit 64, the noise component is extracted by multiplying the inter-frame difference signal by a large coefficient, and this is subtracted. It is subtracted from the original video signal in a circuit 62.An example of a scan conversion circuit that performs image quality improvement processing by scan conversion is as shown in FIG. High pass filter 74, vertical low pass filter 75, subtraction circuit 76
, an addition circuit 77, a time axis compression/multiplexing circuit 7, and a motion adaptive coefficient control circuit 79. The video signal of one field before is outputted from the one-field delay memory 72 and is supplied to one input terminal of the adder circuit 77 via a vertical high-pass filter 74 . Also,
The video signal of the current frame on the input terminal IN is supplied as is to the time-base compression/multiplexing circuit 78, and in the vertical low-pass filter 75, it becomes an interpolation signal between adjacent lines and is sent to the other input terminal of the addition circuit 77. Supplied. The motion adaptive coefficient control circuit 79 detects the magnitude of interframe motion from the interframe difference signal output from the subtraction circuit 76, and dynamically controls the coefficients of the vertical high-pass filter 74 and the vertical low-pass filter 75. . Another example of a scan conversion circuit that performs image quality improvement processing by scan conversion is, as shown in FIG. It is composed of a directional low-pass filter 85, a subtraction circuit 86, a time axis compression/multiplexing circuit 88, and a motion adaptive coefficient control circuit 89. The video signal of the current frame on the input terminal IN and the video signal of the previous frame output from the 1-field delay memory 82 are added by the adder circuit 83 to become an average value signal between adjacent frames, which is then passed through the vertical high-pass filter 84. The signal is supplied to one input terminal of the adder circuit 87 via the . Further, the output of the 1-field delay memory 81 is supplied as is to the time-base compression/multiplexing circuit 88 , and at the same time, it becomes an interpolation signal between adjacent lines in the vertical low-pass filter 85 and is supplied to the other input terminal of the adder circuit 87 . be done. The motion adaptive coefficient control circuit 87 detects the magnitude of interframe motion from the interframe difference signal output from the subtraction circuit 86, and dynamically controls the coefficients of the vertical high-pass filter 84 and the vertical low-pass filter 85. . (Problems to be Solved by the Invention) In the conventional image quality improvement circuit described above, noise reduction processing and scan conversion processing are performed by separate circuits shown in FIGS. 8 and 9. Therefore, each circuit requires an expensive 1-frame delay memory that causes a 1-frame delay in the video signal to be processed, resulting in an increase in cost. In addition, in the conventional scan conversion circuit shown in Fig. 10, a delay of one field is generated in the video signal based on the correlation between adjacent frames (when generating a line interpolation signal).This delay improves the image quality. When accumulated at each stage of processing, the time lag with the audio signal becomes a problem, and a delay circuit is required in the audio system to remove this time lag. (Means for Solving the Problem) The present invention According to the image quality improvement circuit of 1.
Second. A total of 1 frame for a 2:1 interlaced television video signal consisting of a third 1-line delay memory, a 260-line delay memory, and a 262-line delay memory, and the noise-reduced components are supplied from the input terminal through the noise reduction section. A one-frame delay memory is shared between the motion-adaptive noise reduction section and the scan conversion section, resulting in a delay of 30 minutes. The motion adaptive noise reduction unit detects the difference signal between adjacent frames, which is created by subtracting the output of the shared one-frame delay memory and the television video signal supplied to the input terminal, from the difference signal between adjacent frames. The noise contained in the input television video signal is reduced by multiplying by a coefficient corresponding to the magnitude of the motion between frames and subtracting this from the input television video signal. In addition, the motion adaptive scan converter passes the output of the 260-line delay memory in the shared 1-frame delay memory through a high-pass filter in the line array direction having cascade-connected 1-line delay memories and coefficient circuits. Based on the correlation between fields (a first interpolation signal generation circuit that generates a field interpolated video signal of the previous field, and a first, second, and third one-line delay memory in a shared one-frame delay memory) By combining the video signals of the input/output terminals through a coefficient circuit, based on the correlation between four adjacent lines (a second interpolation signal generation circuit that generates an interpolated video signal between lines, and a first and second interpolation a motion adaptive coefficient control circuit that controls a coefficient circuit in the signal generation circuit according to the magnitude of interframe motion detected from the magnitude of the difference signal between adjacent frames; and first and second interpolation signal generation. An adder circuit that adds the outputs of the circuits, and an output of this adder circuit and a shared one.
Scan conversion processing is performed by a time axis compression/multiplexing circuit that compresses the time axis to 1/2 and multiplexes the output of the first one-line delay memory in the frame delay memory and converts it into sequential scanning scanning lines. be exposed. Hereinafter, the operation of the present invention will be explained in detail together with examples. (Embodiment) FIG. 1 is a block diagram showing the configuration of a television video signal image quality improvement circuit according to an embodiment of the present invention.
．． 2 is a subtraction circuit, 3 and 4 are motion adaptive coefficient control circuits, and 5a
, 5b, 5c are 1 line delay memory, 6 is 260 line delay memory, 7 is 262 line delay memory, 8a, 8b
, 8c, 8d. 11a, llb, llc are coefficient circuits, 9, 12゜13 are adder circuits, ioa, 10b are 1-line delay memories, 15
is a time axis compression/multiplexing circuit. The input terminal IN has R and G of the NTSC standard system. A two-to-one line interlaced television video signal consisting of components such as a B primary color signal, a color difference signal, and a luminance signal is supplied as a television video signal to be subjected to image quality improvement processing. This television video signal is supplied to the addition input terminal of the subtraction circuit 2. A noise component generated based on the interframe difference signal in the motion adaptive coefficient control circuit 3 is supplied to the subtraction input terminal of the subtraction circuit 2. Therefore, the output of the subtraction circuit 2 becomes a noise-reduced 2:1 interlace television video signal and is supplied to the input terminal of the 1-line delay memory 5a. This 1-line delay memory 5a delays the input 2:1 interlaced video signal by 1 in and outputs the delayed signal. Similarly, the subsequent 1-line delay memories 5b, 5c, 260
The line delay memory 6 and the 262 line delay memory 7 are
The input 2:1 interlaced video signal is delayed by each corresponding line and output. Therefore, the video signal output from the 262-line delay memory 7 is a video signal that is one frame (525 lines) before the video signal currently appearing on the input terminal of the 1-line delay memory 5a, that is, the input terminal IN. The video signal appearing at the input terminal IN and the video signal of the previous frame being output from the 262-line delay memory 7 are subtracted by a subtraction circuit 1 to become a difference signal between adjacent frames, which is then sent to a motion adaptive coefficient control circuit for noise reduction. 3 and a motion adaptive coefficient control circuit 4 for scan conversion. As shown in FIG. 2, the motion adaptive coefficient control circuit 3 for noise reduction receiving the difference signal F between adjacent frames includes coefficient circuits 21 and 22, a switch circuit 23, a sign discrimination circuit 24, an absolute value circuit 25, and a limit circuit 25. Value generation circuit 26, dark value holding circuit 27
．． 28, 29, comparison circuits 31, 32, 33, and a decoder 34. The difference signal F between adjacent frames supplied from the subtracter 1 to the input terminal I in FIG.
Supplied to and■. The above-mentioned difference signal F between adjacent frames is
After being converted into a non-polar signal by the absolute value circuit 25, the dark value is supplied to one input terminal of the comparison circuits 31, 32 and 33, and the dark value is supplied to the other input terminal of each from the threshold value holding circuits 27, 28 and 29. Al, Bl, CI (Al<Bl<
C1). If the absolute value of the difference signal F between adjacent frames is less than the dark value A1, the output a of the comparison circuits 31, 32, and 33. b, c are all O as shown in the top row of the table in FIG. 3, and a switching signal (
00) is supplied. If the absolute value of the difference signal F between adjacent frames is greater than or equal to the dark value A1 and less than B1, only the output a of the comparison circuit 3°1 becomes 1, and the decoder 34 supplies the switch 23 with the switching signal [01]. Moreover, if the absolute value of the difference signal F between adjacent frames is greater than or equal to the threshold value B1 and less than CI,
Only the outputs a and b of the comparison circuits 31 and 32 become 1, and a switching signal [10] is supplied to the switch 23. Furthermore, if the absolute value of the difference signal F between adjacent frames is equal to or greater than the dark value 01, the output a of the comparison circuits 31, 32, and 33. Both b and c become l, and a switching signal [11] is supplied to the switch 23. The switch 23 is connected to the decoder 3 as shown in the table of FIG.
The switching signal supplied from 4 is

[00] to Co 1)
, C1O), and (11), the contacts I are sequentially switched to n, m, and rv. The contact point (3) of the switch 23 is supplied with 1.F as the difference signal between adjacent frames whose coefficient has been multiplied by 1 in the coefficient circuit 21 as described above. In addition, the coefficient circuit 22 has a coefficient of 2 at the contact point ■.
(<kl) multiplied by 2・F
is supplied. In addition, the contact point ■ of the switch 23 has
In the limit value generation circuit 26, the threshold value B1 and the sign discrimination circuit 2
The amplitude limit value generated based on the determination result of step 4 is supplied, and the O value is supplied to the contact point (3). Therefore, the output of the motion adaptive coefficient control circuit 3 which is output to the subtraction input terminal of the subtraction circuit 2 in FIG. 1 via the output terminal 0 is as follows.
As shown by the solid line in Figure 4, in the range where the absolute value of the difference signal F between adjacent frames is less than the dark value A1, the coefficient increases in proportion to 1, and in the range from the dark value A1 to less than B1, the coefficient becomes smaller. It increases in proportion to 2, and becomes a constant amplitude limit value in the range of B1 or more and less than 01, and O in the range of darkness value 01 or more.
becomes. The threshold values Al, B1. C1 is changed to a large dark value A2 . B2. By changing to C2, the amplitude limiting characteristic shown by the solid line in FIG. 4 can be changed to the amplitude limiting characteristic shown by the dotted line. As a result, the noise reduction effect is adjusted according to the image quality. The reference pixel in Figure 1 is one line delay memo I75.
If pixel α is being outputted from pixel a, then pixel β1 being outputted from the subsequent one-line delay memory 5b is a pixel displayed one line before pixel α, as shown in FIG. Furthermore, the pixel β2 being input to the one-line delay memory 5a is the fifth pixel β2.
As shown in the figure, the pixel is displayed one line after the pixel α. Furthermore, the pixel β3 being outputted from the one-line delay memory 5C becomes a pixel displayed two lines before the pixel α. Furthermore, as shown in FIG. 5, the pixel T being output from the 260-line delay memory 6 is a pixel that was displayed one field before the pixel α and half a line above its display position. Therefore, the 1-line delay memory 5a is connected in series in three stages.
, 5b, 5c, the pixel signal β2. α, β1
．． β3 is a coefficient bl in coefficient circuits 8a, 8b, 8c, 8d,
When multiplied by b2 and then added by the adding circuit 9, this becomes an interpolated pixel between lines created based on the correlation between four adjacent lines. That is, the adjacent scanning line n in FIG.
The average value inserted between −1 and n (b2・β2+t
)1・α+b1・β1+b2・β2) is an interpolated line n'' generated based on the correlation between adjacent lines. The signal γ is an interpolated pixel based on the correlation between adjacent fields created from the pixel signal of the immediately previous field.In other words, the signal γ is an interpolated pixel based on the correlation between adjacent fields created from the pixel signal of the immediately previous field.
The line that connects the pixel signals of the immediately previous field inserted between the two fields becomes an interpolation line n+1 generated based on the correlation between adjacent and adjacent fields. In reality, interpolated pixel signals generated based on the correlation between adjacent fields are subjected to high-pass filter processing in the line arrangement direction (vertical direction in the display screen). A filter that performs this bypass processing includes one-line delay memories 10a and 10b connected in series, and coefficient circuits 11a and ll.
b, llc, and an adder circuit 12. The coefficient a1 set in the coefficient circuits 11a and llc of this high-pass filter, and the coefficient aO set in the coefficient circuit 11b
is the difference signal F between adjacent frames in the motion adaptive coefficient control circuit 4.
It is dynamically controlled according to the movement detected from the coefficient a
Due to the relationship between O and al, the adder circuit 12 outputs high frequency components in the line arrangement direction. These coefficients aQ, al are
Coefficients bl and b2 set in the coefficient circuits 8a to 8d described above
In relation to this, it also serves as a coefficient that gives a synthesis ratio according to the movement of two types of interpolation signals generated based on the correlation between adjacent fields and the correlation between adjacent lines. For this reason,
The above four types of coefficients are ao+al+2bl+2b2=
It is dynamically controlled according to the magnitude of the movement so as to satisfy the relationship 1. If the display screen is a completely still image with no movement, an interpolation signal is created using only interpolation components generated based on the correlation between adjacent frames (bl=b2=0). On the contrary, if the movement of the display screen is equal to or greater than a predetermined value, an interpolation signal is created using only interpolation components generated based on the correlation between adjacent lines (aO=al=O). The motion adaptive coefficient control circuit 4 for scan conversion that detects the magnitude of the motion in the display screen and performs the corresponding coefficients (aO, al, bl, b2) (7) dynamic control is shown in FIG. As shown, the absolute value circuit 41, the dark value holding circuits 42, 43.4
4. Comparison circuit 45.46° 47, decoder 48, and coefficient generation circuit 49. The adjacent frame difference signal F supplied to the input terminal I from the subtraction circuit 1 in FIG. Dark value holding circuits 42, 43.4 are connected to the input terminals of
4 are compared with threshold values A, B, and C (A<B<C), respectively. If the absolute value of the difference signal F between adjacent frames is less than the dark value A, the outputs a, b, and c of the comparator circuits 45, 56, and 47 all become O as shown in the top row of the table in FIG. , decoded signal from decoder 48

[00] is output. If the absolute value of the difference signal F between adjacent frames is greater than or equal to the dark value A and less than B, only the output a of the comparison circuit 45 becomes 1, and the decoder 48 outputs a decoded signal [01]. Further, if the absolute value of the difference signal F between adjacent frames is greater than or equal to the dark value B and less than C, only the outputs a and b of the comparison circuits 45 and 46 become 1, and a decoded signal [10] is output. Further, if the absolute value of the difference signal F between adjacent frames is equal to or greater than the dark value C, the comparison circuits 45, 46 . 4.7 output a, b,
All of c become 1, and a decoded signal [11] is output. The coefficients (aOlat, b
l, b2) is the decoder 48 as shown in the table of FIG.
The decoded output of

From [00] (01), (1
0), (11), (1,0,
0,0) sequentially from (3/4. -1/4.1/4.1/
8), c 1/2. -1/4.3/8.1/8)
, (0, 0, 1/2, O). Therefore, in a range of small movements where the difference signal F between adjacent frames is less than the dark value A, the interpolation signal between lines output from the adder circuit 13 is composed only of components generated based on the correlation between adjacent fields. be done. Conversely, in a range of large motion in which the difference signal F between adjacent frames exceeds the threshold C, the interpolation signal output from the adder circuit 13 is composed only of components generated based on the correlation between adjacent lines. In an intermediate state where the difference signal F between adjacent frames exists between thresholds A and C, an interpolated component generated based on the correlation between adjacent fields, an interpolated component created based on the correlation between adjacent lines, and are multiplied by a coefficient of a ratio according to the magnitude of the movement, and then synthesized in the adding circuit 13. In the time axis compression/multiplexing circuit 14, the pixel signal for one line output from the one line delay memory 5a and the interpolated pixel signal for one line supplied from the adder circuit 14 are written into the line memory. The data is read out sequentially while being multiplexed at twice the writing speed. As a result, the NTSC standard 2:1 interlaced scan television video signal is converted into a line progressive scan video signal with twice the line density, and is output from the output terminal OUT. (Effects of the Invention) As explained in detail above, the television video signal image quality improvement circuit according to the present invention comprises three cascade-connected circuits that provide delay to a two-part interlaced television video signal. Since the configuration uses a 1-frame delay memory consisting of a line delay memory, a 260-line delay memory, and a 262-line delay memory in common with the motion adaptive noise reduction section and the scan conversion section, only one expensive 1-frame delay memory is required. The cost can be reduced, and the cost of the entire image quality improvement circuit can be reduced. The motion adaptive scan converter generates an interpolation signal between adjacent lines from pixel signals on four adjacent lines, and also applies a high pass in the line arrangement direction to the interpolation signal generated based on the correlation between adjacent fields. Since the configuration performs filter processing, it is possible to prevent image quality deterioration due to line flicker and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image quality improvement circuit for television video signals according to an embodiment of the present invention, and FIG. 2 illustrates the configuration of the motion adaptive coefficient control circuit 3 for noise reduction in FIG. 1. Block diagrams, FIGS. 3 and 4 are conceptual diagrams for explaining the functions of the motion adaptive coefficient control circuit in FIG. 2, and FIG. 5 is a conceptual diagram for explaining the functions of the scan conversion section in FIG. 1. , FIG. 6 is a block diagram illustrating the configuration of the motion adaptive coefficient control circuit 4 for scan conversion shown in FIG. 1, and FIG. 7 is a conceptual diagram for explaining the function of the motion adaptive coefficient control circuit 4 shown in FIG. 6. FIG. 8 is a block diagram showing the configuration of a conventional motion adaptive noise reduction circuit, FIG. 9 is a block diagram showing an example of the configuration of a conventional motion adaptive scan conversion circuit, and FIG. 10 is a block diagram showing the configuration of a conventional motion adaptive noise reduction circuit. FIG. 3 is a block diagram showing an example of another configuration of the type scan conversion circuit. 1.2... Subtractor, 3... Motion adaptive coefficient control circuit for noise reduction, 4... Motion adaptive coefficient control circuit for scan conversion, 5a, 5b, 5c... 1 line delay memory, 6.
...260 line delay memory, 7...262 line delay memory, 8a, 8b, 8c, 8d, lla, llb,
IIC---Coefficient circuit, 9.12.13...Addition circuit, 10a, 10b...1 line delay memory, 14...
・Time base compression/multiplexing circuit. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (1)

[Scope of Claims] A noise-reducing circuit comprising first, second, and third 1-line delay memories, 260-line delay memories, and 262-line delay memories connected in series, and is supplied from an input terminal through a noise reduction section. a 1-frame delay memory for causing a total of 1-frame delay in a 2:1 interlaced television video signal consisting of R, G, B primary color signals and other components; and an output of the 1-frame delay memory and a supply to the input terminal. The difference signal between adjacent frames created by subtraction with the input television video signal is multiplied by a coefficient corresponding to the magnitude of the movement between frames detected from the difference signal between adjacent frames, and this a motion adaptive noise reduction unit that reduces noise contained in an input television video signal by subtracting it from the signal; a 1-line delay memory in which the output of the 260-line delay memory in the 1-frame delay memory is connected in cascade; a first interpolation signal generation circuit that generates a field interpolated video signal one field before based on the correlation between adjacent fields by passing it through a high-pass filter in the line array direction having a coefficient circuit; , second
and a second interpolation signal generation circuit that generates an interline interpolation video signal based on the correlation between four adjacent lines by synthesizing the video signals of the input and output terminals of the third one-line delay memory through a coefficient circuit; a motion adaptive coefficient control circuit that controls coefficient circuits in the first and second interpolation signal generation circuits according to the magnitude of interframe motion detected from the magnitude of the difference signal between adjacent frames; an adder circuit that adds the outputs of the first and second interpolation signal generation circuits; and an adder circuit that adds the outputs of the first and second interpolation signal generators;
Time axis compression, which compresses the time axis of the output of the line delay memory to 1/2, multiplexes it, and converts it to a sequential scanning system scanning line.
1. An apparatus for improving the image quality of a television video signal, comprising: a scan conversion section having a multiplexing circuit;