JPH0234040B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a performance data reading type automatic performance device that can automatically make the tempo of an automatic performance follow the tempo of a manual performance. In this specification, the term "automatic performance" refers not only to automatically playing melody tones or chords based on stored data, but also to automatic bass chords, automatic arpeggios, automatic rhythms, etc. It is used in a broad sense, including

In conventionally proposed automatic performance devices of this type, the tempo of automatic performance can be arbitrarily set by operating a tempo adjustment knob of a tempo signal generator. However, automatic performance is usually used in conjunction with manual performance, and it is extremely difficult for manual players to delicately manipulate the tempo adjustment knob during performance. For this reason, it has been virtually impossible to express music by changing the tempo of automatic performance once set to make the song more exciting.

Therefore, an automatic performance device in which the tempo of automatic performance automatically follows the tempo of manual performance has already been proposed by the same applicant as this application. 33719]).

In the automatic performance device according to this prior application, key press time intervals are measured by counting clock signals obtained by variably dividing a high speed clock signal according to note length information, and multiple key press time intervals are calculated. By controlling and changing the frequency of the tempo clock signal in accordance with the output obtained by averaging the counting information corresponding to the tempo clock signal, the tempo of the automatic performance based on the tempo clock signal is made to follow the tempo of the keyboard performance.

According to such a configuration, (a) it is necessary to variably divide the high-speed clock signal in order to make the count value of the clock signal constant regardless of the note type such as a half note or a quarter note; (b) Since a clock signal with a higher frequency than the tempo clock signal is counted, the number of bits of counting information increases, and it is necessary to use multi-bit registers for averaging operations. For these reasons, the configuration cannot be avoided.

In order to simplify the configuration, the key press time interval is measured by counting the tempo clock signal, and the difference between the obtained key press time interval information and note length information is calculated for each note, and the key press time interval is calculated for each note. It has also been proposed to change and control the frequency of the tempo clock signal in accordance with the output obtained by averaging the differences between the two (see the above-mentioned publication). However, with this configuration, since low-speed tempo clock signals are counted, the accuracy of measuring the key press time interval is low, and the tempo followability is not necessarily sufficient.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved automatic performance device that has a simple configuration and can provide good tempo followability.

The automatic performance device according to the present invention includes: (a) means for generating a tempo clock signal; (b) automatic performance means for automatically performing at a tempo corresponding to the frequency of the signal based on the tempo clock signal; and (c) a plurality of automatic performance means. (d) a storage means that stores a plurality of note length information each representing the length of a note; (d) a readout address of the storage means is sequentially advanced to sequentially read out the plurality of note length information and the notes read out; The output means sequentially outputs note length information, and when certain note length information is output, the note length indicated by the note length information is measured by counting the tempo clock signal, and the counted value becomes a value corresponding to the note length. (e) generating a high-speed clock signal having a higher frequency than the tempo clock signal; and (e) generating a high-speed clock signal having a higher frequency than the tempo clock signal. (f) every time the note length information is output from the output means, the note length indicated by the note length information is measured by counting the high speed clock signal, and the counted value is a value corresponding to the note length; (g) a first measuring means that sends out a measurement output representing a count value corresponding to the note length when the number of notes reaches; A second device that measures the operation time interval for each operation by counting the high-speed clock signal, and when the count value reaches a value corresponding to the operation time interval, sends out a measurement output representing the count value corresponding to the operation time interval. (h) a calculation for calculating the difference between the measurement outputs from the first and second measurement means for each note and representing the value of the difference and a sign corresponding to the magnitude relationship between the two measurement outputs; a first arithmetic means for sending out an output; (i) averaging a plurality of arithmetic outputs sequentially sent from the first arithmetic means to send out an average output representing the average of the plurality of arithmetic outputs; (j) a control means for controlling the frequency of the tempo clock signal in accordance with an average output from the second calculation means, the average output being measured by the first measurement means; When the measured output from the second measuring means is greater than the output, the frequency of the tempo clock signal is decreased corresponding to the value of the average output, and the average output is determined by the first measuring means. and increasing the frequency of the tempo clock signal in accordance with the value of the average output when the measured output from the second measuring means is smaller than the measured output from the means. It is.

According to the configuration of the present invention, when the performance tempo of the musical instrument becomes slower than the tempo of automatic performance (and note length information output), the frequency of the tempo clock signal becomes lower in accordance with the average output from the second calculation means. As a result, the tempo of automatic performance (and note length information output) slows down to follow the musical instrument performance tempo. Conversely, if the performance tempo of the musical instrument becomes faster, the tempo of automatic performance (and output of note length information) becomes faster.

The invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

FIG. 1 shows a keyboard-type electronic musical instrument according to an embodiment of the present invention, which is capable of producing melody tones automatically and/or manually, and also allows an accompanist to play manually. If necessary, it can be played in the form of auto bass chord or auto arpeggio, and it is also possible to play auto rhythm sounds. And the melody sound,
The tempo of automatic performance such as auto bass chord, auto arpeggio, and auto rhythm automatically follows the tempo of manual performance for generating melody sounds.

The reading device 10 reads musical score data from a recording medium 11a such as a magnetic tape provided in the lower margin of the musical score 11, and stores it in the data memory 12. As shown in Figure 2, the musical score data expresses the pitch and note length of each note in binary code according to the note progression. It is located. Pitch data is expressed, for example, in the form of a key code that includes a 4-bit note code and a 3-bit octave code, and note length data is expressed in 32nd note, 16th note, 8th note, 4th note, 2nd note, etc. diacritic,
Whole notes are now represented by binary codes corresponding to 6, 12, 24, 48, 96, and 192, respectively. Note that a rest is expressed by setting all key code bits to "0".

In the initial state, the data memory 12 storing the musical score data and end data as described above is disabled in response to the output Q of the RS flip-flop 14, which is set by the initial clear signal IC via the OR gate 13. (DIS) condition. Further, at this time, since the output Q of the flip-flop 14 is designed to reset the address counter 15, no address signal is supplied from the counter 15 to the memory 12. moreover,
Since the initial clear signal IC is designed to reset the RS flip-flop 17 via the OR gate 16, the output Q of the flip-flop 17 is at the "0" level.

Next, when the start switch 18 is turned on,
The on signal is differentiated by the differentiating circuit 19,
Converted to start signal SS. This start signal SS resets the flip-flop 14 on the one hand and is applied as a reset input R to the flip-flop 17 via the OR gate 16 on the other hand.
Therefore, the output Q of the flip-flop 14 becomes "0", so the data memory 12 and the counter 1
5 becomes operational, and the output Q of the flip-flop 17 maintains the "0" level. Then, the start signal SS is supplied to the address counter 15 via the OR gate 23, so that musical score data corresponding to the first note is read out from the data memory 12 and latched into the latch circuit 25.

Next, when a key-on corresponding to the first note is made, the flip-flop 17 is set by a key-on signal KON synchronized with the key-on timing. Therefore, the flip-flop 17 generates the performance signal PL as the output Q. This performance signal PL becomes "1" at the start of manual performance and then remains at the "1" level until the end of automatic performance.
1 to one input terminal of the AND gate 22. At this time, since the key-on signal KON is supplied to the other input terminal of the AND gate 22, the performance signal is output from the output terminal of the AND gate 22.
A pulse signal synchronized with the rising timing of PL is sent out.

This pulse signal is supplied to the counter 15 via the OR gate 23, so the counter 15 supplies an address signal to the memory 12 to instruct the data read address corresponding to the second note.
Musical score data corresponding to the second note is read from. This musical score data is then latched by the latch circuit 25 in response to the output signal of the OR gate 23. On the other hand, the musical score data corresponding to the first note latched in the latch circuit 25 is latched in the latch circuit 26 in response to the output signal of the OR gate 23.

On the other hand, the counter 27 counts the tempo clock signal TCL from the tempo control circuit 29 after being reset by the output signal of the OR gate 23 in synchronization with the latch timing of the latch circuit 26. Note length data TD from latch circuit 26 and counter 2
The count output of 7 is supplied to a comparison circuit 28 and compared.

The comparison circuit 28 sends out a match signal EQ when the count output of the counter 27 matches the code length data TD from the latch circuit 26.
1. A flip-flop 17 is connected to the other input terminal of this AND gate 31.
Since the performance signal PL is supplied from the
The signal is sent to the OR gate 23. Therefore, an output signal is sent from the OR gate 23 when the time corresponding to the length of the first note is reached by counting the tempo clock signal TCL, and this output signal is sent to the counter 15, latch circuits 25, 26, and It is supplied to the counter 27. Therefore, the counter 15 is
While acting to read out the pitch data and note length data corresponding to the second to third notes, the note length measuring section including the latch circuit 26, counter 27, and comparison circuit 28 reads out the pitch data and note length data corresponding to the second to third notes. Perform note length measurement. Thereafter, data reading from the memory 12 and note length measurement are performed in the same manner, and finally, the end data is read from the memory 12.

When the end data is read, the end detection circuit 32
detects the end data and generates an end signal ED. This end signal ED causes flip-flop 14 to be reset via OR gate 13, so that memory 12 is disabled and counter 15 is reset. Also, the end signal
ED is connected to flip-flop 1 via OR gate 16
7 is reset, the performance signal PL is “0”
The process returns to , and the series of data read operations is completed.

By the way, the latch circuit 25 sequentially latches the musical score data in accordance with the above-described musical score data reading operation, but the pitch data of the latch output is
PD is supplied to a rest detection circuit 33. The rest detection circuit 33 detects that all the key code bits of the pitch data PD are "0" and generates an output signal, and this output signal is sent to the inverter 34.
The signal is supplied to one input terminal of the AND gate 35 via. The other input terminal of AND gate 35 has
A pulse signal synchronized with the data read timing is supplied from the AND gate 31, and an output signal from the rest detection circuit 33 is not generated from the output terminal of the AND gate 35 (that is, note data is read out instead of a rest). Pulse signal LEQ synchronized with the reading timing of musical note data under the condition that
is sent out and supplied to the tempo control circuit 29.

Further, the pitch data PD sequentially latched by the latch circuit 26 is supplied to a comparison circuit 36 and compared with a keying signal KY indicating a key pressed in a manual performance section, which will be described later. Comparison circuit 36 is pitch data
When PD and keying signal KY match, a match signal EQ is supplied to one input terminal of AND gate 37. A key-on signal KON is supplied to the other input terminal of the AND gate 37.
When the comparison circuit 36 generates a matching signal (pitch data PD and keying signal KY
key-on signal KON is sent out when the In addition, the comparison circuit 36 and the AND gate 3
Reference numeral 7 is provided to prevent a key-on signal based on an erroneous key-on operation.

The key-on signal KON from the AND gate 37 is supplied to the fixed contact a of the select switch 38, and the same key-on signal KON as input to the AND gate 37 is supplied to the fixed contact b of the switch 38.
The select switch 38 switches the movable contact to the fixed contact a side in the case of a relatively beginner player.
For relatively advanced players, the movable contact is switched to the fixed contact b side, and switch 3
The key-on signal ON derived through 8 is supplied to one input terminal of an AND gate 39 in addition to the flip-flop 17 described above. Since the performance signal PL is input to the other input terminal of the AND gate 39, the AND gate 39 transfers the key-on signal KON to the tempo control circuit 2 every time a key-on is performed.
Supply to 9.

The pitch data PD sequentially latched by the latch circuit 25 is also supplied to the monitor melody sound generation circuit 40. When the select switch 40a is turned on, the melody sound generation circuit 40 is enabled (EN), and electronically synthesizes a musical sound signal based on input pitch data and sends it out. This musical tone signal is supplied to a sound system 42 via a volume 41 and converted into sound.

The pitch data PD is also supplied to the key display circuit 43. This key display circuit 43 is connected to the select switch 4
3a is turned on, the light emitting element 44a provided for each key of the upper keyboard (UK) 44 becomes enabled.
is selectively lit to display the key position to be pressed. In addition, the melody sound generation circuit 40 for monitoring
The key display circuit 43 is supplied with pitch data one note before the key to be pressed.

The upper keyboard 44 has a key switch (KSW) circuit 4.
5 is attached, and the key switch circuit 45 supplies a keying signal KY indicating the pressed key to the above-mentioned comparison circuit 36 and also to a melody sound generation circuit 46 for manual performance. The melody sound generation circuit 46 electronically synthesizes a musical sound signal in accordance with the input keying signal and sends it out. This musical tone signal is supplied to the sound system 42 via a volume 47 and converted into sound.

In addition to the keying signal KY described above, the key switch circuit 45 supplies an any key-on signal to the differentiating circuit 48 each time any key is pressed. The differentiation circuit 48 differentiates the rise of the any key-on signal and sends out a key-on signal KON synchronized with the key-on timing. This key-on signal KON is applied to the AND gate 37 and select switch 3 mentioned above.
8.

In the above example, a melody tone is automatically played based on the stored data, but it is also possible to automatically play a chord or the like based on the same principle.

The lower keyboard (LK) 50 has a key switch circuit 51
The key switch circuit 51 sends a keying signal indicating the pressed key to the accompaniment sound generating circuit 5.
Supply to 2. The accompaniment sound generation circuit 52 is also supplied with a keying signal from a key switch circuit 54 attached to the pedal keyboard 53. The accompaniment sound generation circuit 52 electronically synthesizes and transmits a musical tone signal according to the keying signals from the key switch circuits 51 and 54, and converts the musical tone signal into an auto base chord (ABC) or an auto arpeggio as necessary. It can now be generated in the form of YO (ARP). Furthermore, the accompaniment sound generation circuit 52 is capable of generating a musical sound signal in a rhythmically rough form in response to a rhythm signal RY from an autorhythm section, which will be described later. The musical sound signal from the accompaniment sound generation circuit 52 is supplied to the sound system 42 via the volume 55 and converted into sound.

The R-S flip-flop 60 receives the aforementioned performance signal.
It is set by the performance start signal ΔPL formed by differentiating the rising edge of PL in the differentiating circuit 61, and is reset by the ON signal from the stop switch 62.
3. The autorhythm device 63 includes a counter 65 that counts a signal obtained by dividing the tempo clock signal TCL from the tempo control circuit 29 by a frequency dividing circuit 64, and a rhythm pattern that generates a rhythm pattern signal according to the count output of the counter 65. A generating circuit 66 and a rhythm sound source circuit 67 driven by a rhythm pattern signal from the circuit 66 are provided. The output Q of the flip-flop 60 is supplied to a counter 65 as an enable signal EN, and the counter 65 starts counting in synchronization with the start timing of the performance, and stops counting in synchronization with the on timing of the stop switch 62. In addition to the rhythm pattern signal, the rhythm pattern generation circuit 66 also generates a rhythm signal RY to be supplied to the accompaniment sound generation circuit 52 described above.
It is also starting to occur. The rhythm sound source circuit 67 is enabled when the select switch 67a is turned on, and sends out a rhythm sound signal in response to the rhythm pattern signal from the rhythm pattern generation circuit 66. is supplied to the sound system 42 and converted into sound. Therefore, when the select switch 67a is turned on, the autorhythm sound is played in synchronization with the start of manual play on the upper keyboard 44, and when the stop switch 62 is pressed, the autorhythm sound is played. The output will be stopped.

Next, the configuration and operation of the tempo control circuit 29 will be explained with reference to FIGS. 3, 4, and 5.

In FIG. 3, the tempo oscillation circuit 70 consists of a voltage-controlled variable frequency oscillator (VCO),
In the initial state, a tempo clock signal TCL of a predetermined frequency is sent out in response to the initial setting voltage signal IS from the variable resistor 70a. And the start signal
When SS is generated, latch circuits 71 and 72 are reset in response to the start signal SS.

Next, the key-on signal corresponds to the first note.
When KON is generated, the performance signal PL and the performance start signal ΔPL are generated as described above. Therefore, the counter 73 is reset by the performance start signal ΔPL supplied via the OR gate 74, and the counter 75 is reset by the performance start signal ΔPL supplied via the OR gate 76. Furthermore, the latch circuit 77 is reset and released by the performance signal PL supplied via the inverter 78, and the latch circuit 79 is reset and released by the performance signal PL supplied via the inverter 80.

The counters 73 and 75 both count the clock signal φ (having a frequency sufficiently higher than TCL) after being reset as described above, and each count output is supplied to the corresponding latch circuits 77 and 79, respectively. It's becoming like that.

When the time corresponding to the length of the first note is reached from the time when the key-on is made corresponding to the first note (corresponding to the time when the note data corresponding to the second note is read), the third note is pressed as described above. A pulse signal LEQ is generated in synchronization with the reading timing of musical note data corresponding to the musical note. This pulse signal
LEQ is supplied to latch circuit 77 as latch command signal L, and is supplied to counter 73 as reset signal R via D-flip-flop 81 and OR gate 74. Therefore, the latch circuit 77 activates the counter 73 in response to the pulse signal LEQ.
The counter 73 is reset with a slight time delay corresponding to the delay of the flip-flop 81 from the latch timing. After this reset, the counter 73 counts the clock signal φ again.

On the other hand, assuming that the key-on corresponding to the second note is made with a slight delay from the time when the pulse signal LEQ is generated, the key-on signal KON synchronized with the key-on timing is sent to the one-shot circuit 82.
The output of this one-shot circuit 82 is supplied to a D-flip-flop 83. The output of the flip-flop 83 is then supplied to an AND gate 84, where it is ANDed with the key-on signal KON. Here, the circuit including the one-shot circuit 82, the flip-flop 83, and the AND gate 84 is provided to prevent a key-on signal based on an erroneous key-on operation such as continuous key-on. Operate. In other words, if the key-on signal KON is generated at time _t1 , this key-on signal KON
In response to this, the output of the one-shot circuit 82 takes the "1" level during the period _T1 . Then, the output of the flip-flop 83 becomes "1" for a short time d, which is the delay of the output of the one-shot circuit 82, so that the key-on signal KON' is derived via the AND gate 84 during this "1" period. Then t ₂ and
Assuming that the key-on signal KON is generated continuously at time t ₃ , the key-on signal at time t ₂ is generated via the AND gate 84 as in the case at time t ₁ .
Although the key-on signal at time _t3 corresponds to the period in which the output of the flip-flop 83 is "0", it is blocked by the AND gate 84.

The key-on signal KON' generated from the AND gate 84 in response to the second note is generated by the latch circuit 79.
is supplied as the latch command signal L, while D-
The reset signal R is supplied to the counter 75 via the flip-flop 85 and the OR gate 76. Therefore, the latch circuit 79 causes a key-on signal.
While the count output of the counter 75 is latched in response to KON', the counter 75 again counts the clock signal φ after this reset with a slight time delay corresponding to the delay of the flip-flop 85 from this latch timing.

The count data latched by the latch circuits 77 and 79 as described above are supplied to the subtraction circuit 86 as inputs A and B, respectively, and the subtraction circuit 86 outputs the absolute value of the difference as a result of the difference operation of (A-B). signal AB indicating the sign of the difference (+ or -) and signal SG indicating the sign of the difference (+ or -)
is generated. In the above example, since the key-on timing of the second note is slightly delayed with respect to the readout timing (automatic performance timing) of the third note, the magnitude relationship between inputs A and B is A<B. Therefore, the absolute value signal AB is generated corresponding to the value of B exceeding A, and the sign signal SG is generated to indicate a minus (-).

By the way, the key-on signal KON' and the pulse signal LEQ from the AND gate 84 are supplied to an OR gate 87, and the output signal of this OR gate 87 is supplied to a one-shot circuit 88. The output of the one-shot circuit 88 is the D-flip-flop 8.
9, the signal is slightly delayed and supplied to an AND gate 90, where it is ANDed with the output signal of the OR gate 87. Here, the circuit including the one-shot circuit 88, flip-flop 89 and AND gate 90 is as follows.
This is for supplying the latch command signal L to the latch circuits 71 and 72 only when the time interval between the key-on signal KON' and the pulse signal LEQ is less than a predetermined value (approximately equivalent to the output duration of the one-shot circuit 88). , for example, operates as shown in FIG.
That is, as shown in the left part of FIG. 5, the key-on signal is generated with a time delay ta smaller than the output duration _T2 of the one-shot circuit 88 with respect to the pulse signal LEQ.
If KON′ is generated, the key-on signal
KON' is derived via AND gate 90,
As shown in the right part of FIG. 5, the output duration of the one-shot circuit 88 with respect to the pulse signal LEQ is T ₂
If the key-on signal KON′ is generated with a larger time delay tb, the key-on signal KON′ is
It is blocked by AND gate 90. Such an operation is performed in the same manner even if the generation timing of the pulse signal LEQ and the key-on signal KON' is reversed.

Now, when the latch command signal L is generated from the AND gate 90 in response to the key-on signal KON' corresponding to the second note, the latch circuit 71 generates the absolute value signal from the subtraction circuit 86 in response to the latch command signal L. Latch AB and code signal SG.

After this, data reading (automatic performance) corresponding to the 4th note is performed, and then a little later, the 3rd note is read out (automatic performance).
When the key corresponding to the note is turned on, an absolute value signal is sent from the subtraction circuit 86 in the same manner as described above.
AB and sign signal SG are generated and the latch circuit 71
is latched to. Here, the subtraction data corresponding to the second note previously latched in the latch circuit 71 is latched in the latch circuit 72 before the latch circuit 71 latches the subtraction data corresponding to the third note.

Therefore, the latch circuit 71 is included in the averaging circuit 91.
and subtraction data (absolute value signal and sign signal) corresponding to the second and third notes from 72, respectively.
are supplied as inputs A and B, and the averaging circuit 91
, an average value signal MV and a code signal SG' are generated as a result of the averaging operation of (A+B)/2.
In the above example, the key-on timing for the second and third notes is slightly delayed relative to the automatic performance timing, so the average value signal MV
is generated corresponding to the amount of delay and the code signal
SG' is generated to indicate a minus (-).

The average value signal MV and code signal SG′ are digital.
The signal is supplied to an analog (D/A) conversion circuit 92 and converted into a corresponding analog signal +ΔV or -ΔV. In the above example, since the code signal SG' indicates manas, an analog signal of -ΔV is generated as the output of the conversion circuit 92.

The analog signal +.DELTA.V or -.DELTA.V is supplied to the tempo oscillation circuit 70 and acts to raise or lower the frequency of the tempo clock signal TCL by an amount corresponding to .DELTA.V, thereby speeding up or slowing down the tempo of the automatic performance, respectively. In the above example, the frequency of the tempo clock signal TCL decreases in accordance with the analog signal -ΔV, so the tempo of automatic performance slows down to follow the tempo of manual performance. Contrary to the above example, if the manual performance tempo is faster than the automatic performance tempo, the same procedure as above is performed so that the signals SG and SG' show plus (+) and the analog signal +ΔV is generated. The automatic performance tempo follows the manual performance tempo and becomes faster.

In the above embodiment, the key-on signal KON was used as a pulse signal synchronized with the performance timing, but for example, a pulse signal synchronized with the performance timing is derived from a non-keyboard instrument such as a guitar, and this pulse signal is used as the key-on signal. It may be used instead of a signal.

In addition, in the embodiment, the melody sound to be played is always monitored and sounded one note earlier by the automatic performance melody sound forming circuit, making it easier for the performer to play the melody. Set up a memorized obbligato generation circuit,
The obbligato may be automatically played to assist the performer's performance.

As described above, according to the present invention, when reading musical score data from a storage device and manually playing a musical instrument while automatically playing melody notes, chords, rhythm notes, etc., it is possible to follow subtle tempo changes in the manual performance. Since the tempo of automatic performance can be controlled automatically, it is not only convenient for beginners to practice, but also extremely useful for intermediate to advanced players in that it provides a rich variety of musical expressions. It is beneficial for

In addition, note length measurement and operation time interval measurement are both performed by counting high-speed clock signals, and a difference calculation is performed between the count information corresponding to the note length and the count information corresponding to the operation time interval, and multiple difference calculation outputs are generated. Since the frequency of the tempo clock signal is controlled by averaging, there is no need for variable frequency division, and registers with a small number of bits can be used for averaging, resulting in a simple configuration. Furthermore, since the operation time interval is measured by counting high-speed clock signals, the operation time interval can be measured with high accuracy and good tempo followability can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a diagram showing a data format used in the electronic musical instrument, and FIG. 3 is a diagram showing a data format used in the electronic musical instrument.
FIGS. 4 and 5, which are circuit diagrams showing details of the tempo control circuit in the electronic musical instrument, are time charts for explaining the operation of the circuit shown in FIG. 3. 29... Tempo control circuit, 40... Melody sound generation circuit for monitoring, 46... Melody sound generation circuit for manual performance, 63... Autorhythm device, 70... Tempo oscillation circuit.

Claims (1)

[Scope of Claims] 1 (a) means for generating a tempo clock signal; (b) automatic performance means for performing automatic performance at a tempo corresponding to the frequency of the signal based on the tempo clock signal; (c) a plurality of (d) a storage means that stores a plurality of note length information each representing the length of a note; and (d) a readout address of the storage means is sequentially advanced to sequentially read out the plurality of note length information and the read note length is read out. The output means sequentially outputs information, and when certain note length information is output, the note length indicated by the note length information is measured by counting the tempo clock signal, and the measured value reaches a value corresponding to the note length. (e) generating a high-speed clock signal having a higher frequency than the tempo clock signal; and (e) generating a high-speed clock signal having a higher frequency than the tempo clock signal. (f) every time the note length information is output from the output means, the note length indicated by the note length information is measured by counting the high speed clock signal, and the measured value becomes a value corresponding to the note length; (g) operations that overlap in time as the musical instrument is sequentially operated in response to the plurality of notes; a second clock that measures the operation time interval by counting the high-speed clock signal, and when the count value reaches a value corresponding to the operation time interval, transmits a measurement output representing the count value corresponding to the operation time interval; (h) a calculation output for calculating the difference between the measurement outputs from the first and second measurement means for each note and representing the value of the difference and a sign corresponding to the magnitude relationship between the two measurement outputs; (i) a first calculation means for averaging a plurality of calculation outputs sequentially sent from the first calculation means and sending out an average output representing the average of the plurality of calculation outputs; (j) a control means for controlling the frequency of the tempo clock signal according to an average output from the second calculation means, the average output being a measurement output from the first measurement means; When the measured output from the second measuring means is larger than the measured output from the second measuring means, the frequency of the tempo clock signal is decreased in accordance with the value of the average output, and the average output is higher than the measured output from the first measuring means. automatic performance comprising: increasing the frequency of the tempo clock signal in accordance with the value of the average output when the measured output from the second measuring means is smaller than the measured output from the second measuring means; Device.