JPH0233666A - Mask pattern verifying method - Google Patents

Abstract

PURPOSE:To shorten the processing time for inspection of mask patterns by limiting the reference position of a slit to a position of a segment parallel to the slit direction, the position of a segment vertical to the slit direction, and a position where the junction between two segments touches the segment parallel or vertical to the slit direction. CONSTITUTION:The slits are decided based on the positions of segments 4, 21, 44 and 52 which are parallel to the slit directions of input mask patterns I and II, the positions of start points (e, b, o, q, u and w) and end points (f, c, p, r, v and x) of segments 23, 39, 40, 42, 46 and 48 which are vertical to said slit directions, and the positions (a, d, k, l and m) where the junction between two segments touches a straight line which is parallel or vertical to the slit directions. When a layout is inspected, the apexes of both patterns I and II which serves as the bases of slits are defined as a-y. Thus the number of slits can be extremely decreased. As a result, the layout can be inspected with a small number of slits and the processing time is shortened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention provides a mask pattern in which a large h1 mask pattern data in a large-scale integrated circuit is divided into regions and layout verification is performed using an electronic computer. It concerns a verification method.

[Prior Art] In recent years, the degree of integration of large-scale integrated circuits (LSI) has increased, and the number of graphic data stars included in LJ in a mask pattern has increased dramatically. Therefore, in electronic computer processing using mask patterns as input data, a large amount of graphic data must be fetched at each time, and data processing requires an enormous amount of time.

Conventionally, in large-scale integrated circuits, rectangular or polygonal masks are formed as mask patterns, and various patterns are formed on a wafer using several of these masks. The design of the mask pattern formed on this mask often involves manual input.

As a result, pattern layout errors are unavoidable.

For this purpose, a layout pattern (
Verification of figure width, spacing, etc.) and Zunawara layout verification are often performed.

In this layout verification, the slit method is a method for efficiently dividing and verifying a huge amount of mask data into 61 regions.

Layout verification of a mask pattern using this conventional slit method will be explained based on FIG.

This layout verification is carried out by arranging the mask patterns ■ to ■ by the X coordinates (or
Divide into Then, the line segment within slits A' to N' is Yp
The relationship between adjacent line segments aligned at the i mark (or X coordinate) is investigated.

[Problem to be solved by the invention]

Using this slit method, the direction of the line segment is 0 with respect to the X axis.
Taisei [f
When verifying the layout of the mask pattern of the fi product circuit, the processing time is approximately proportional to the 1.2 power of the amount of data. However, for a mask pattern with many arbitrary angles, the processing time becomes about 1.5 power of the data amount. One of the reasons for this is that the slit is
This is because the number of slits needs to be created using coordinates (or X coordinates), which increases the number of slits and the amount of mask data.

As described above, layout verification using the Surishito method has problems in that it is inefficient for mask patterns of large-scale integrated circuits with many arbitrary angles and takes a long processing time.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a mask pattern verification method that can efficiently verify the layout of a mask pattern of a large-scale integrated circuit with many angles of repose and shorten processing time.

[Means to solve the problem]

In the mask pattern verification method of the present invention, one of the X-axis and Y-axis directions is determined as the slit direction, and the position of the line segment parallel to the slit direction, the position of the starting point and end point of the line segment perpendicular to the slit direction, and the slit direction are determined. The slit is defined based on the position where the connecting point of two line segments touches a straight line parallel or perpendicular to the direction.

[For production]

According to the method of the present invention, the slit reference is set to the position of a line segment parallel to the slit direction, the start and end points of a line segment perpendicular to the slit direction, and two line segments parallel or perpendicular to the slit direction. Since the number of slits is limited to the positions where the connection points of the two touch each other, the number of slits can be reduced, and the number of mask data points can be reduced.

〔Example〕

An embodiment of layout verification using the mask pattern verification method of the present invention will be described with reference to FIGS. 1 to 3.

In this layout verification, the X-axis direction of the large Kamasufu pattern I, (2) with many arbitrary angles as shown in FIG. 1 is determined as the slit direction. Then, as shown in FIG. 1, mask pattern 1. Positions of line segments 4.2+, 44.52 parallel to the slit direction, and starting points e of line segments 23, 39° 40.42, 46.48 perpendicular to the slit direction,
b, o, q.

u, W and end points r, c, p, r, v
, x position and the position a, (1, k
, 1. m to the LTL ship, as shown in Figure 2,
Slits 8 to r7 are defined.

Hereinafter, this layout verification move 1+IQ will be specifically explained.

Human-powered mask pattern 1. 1 is composed of line segments 1 to 39 and 40 to 55, respectively, as shown in FIG. In this case, since the X111 direction of the mask patterns I and II is defined as the slit direction, the line segments parallel to the slit direction are 4, 21, 44.52. Also, the line segment perpendicular to the slit direction is 23°39.40. /12,46.48
and the positions of these starting and ending points are e
, b, a.

q, u, w and r, c, p, r, v, x.

Furthermore, the positions where the connecting points of the two tree line segments touch the straight line parallel or perpendicular to the slit direction are respectively a.

d, becomes I, m. Then, the boundary line of the slit is determined based on each of these positions.

Therefore, as shown in FIG. 2, slits A to 1. is determined.

The line segments whose starting and ending points are the intersections of the boundary line of each slit A-1 and the line segments 1 to 55 of the mask patterns I and II are 56 to 105, as shown in FIG. The data format of these line segments 56 to 105 is as shown in FIG.
) is given a pointer to. In this way, in this layout verification, the apex of mask pattern
Therefore, the number of slits can be significantly reduced compared to the conventional slit method in which the slit standards are aligned at the vertices or intersections of the mask pattern. As a result, layout verification can be performed with a small number of slits.

Also, in slits A-L, each swan)
When comparing the intervals for each line segment 56 to 105 between A and L, if the interval does not satisfy the rule value,
The intervals between the original line segments 1 to 55 between the slits A and L are examined again. For example, in slit B shown in FIG. 2, when comparing line segment 70 and line segment 82, the interval does not satisfy the rule value. (53, 54, 55)
In this way, this layout verification is performed by checking the spacing again and verifying the mask pattern.
The original line segment series I~55 connected in L is slit A
- Line segment 56 whose starting and ending points are the intersection with the boundary line of L
105, compare the replaced line segments 55 to 105 with the rule value, and j! ! The original line segment sequences 1 to 55 are verified in detail only when there is a possibility that the line segment sequence IA-L is different. Therefore, the line segment sequence in each slit IA-L is replaced with one line segment and verification is performed. This can significantly reduce the amount of masking.

In this layout verification, the slit direction is set in the X-axis direction, and the slit reference position is set as a line segment 4 parallel to the slit direction
Line segment 2 perpendicular to the position of 21, 44, and 52 and the slit direction
3. 39, 40, 42, 46° 48 starting and ending points e, b, o, q, u, w and f, c, p,
r, v, x and the point where the connection point of the two tree segments touches a straight line parallel or perpendicular to the swan I direction, fla, d
, I, and m, it is possible to verify the layout of a mask pattern of 1.degree. square with a small number of slits A-L. As a result, the layout of a mask pattern with many arbitrary angles can be efficiently verified and the processing time can be shortened.

In the layout verification of this embodiment, the slit direction was set in the X-axis direction of the mask pattern 3n, but the same applies if the slit direction is set in the Y-axis direction.

〔Effect of the invention〕

The mask pattern verification method of the present invention connects the reference position of the slit to the position of a line segment parallel to the slit direction, the position of a line segment perpendicular to the slit direction, and the connection of two line segments to a straight line parallel or perpendicular to the slit direction. Since the verification is limited to positions where the points touch, it is possible to efficiently verify the layout of a mask pattern of a large-scale integrated circuit with many arbitrary angles, and the processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a mask pattern diagram for explaining the procedure for verifying the layout of a mask pattern according to an embodiment of the present invention, and FIG.
The figure is a mask pattern diagram to explain the slit in Figure 1, Figure 3 is a block diagram of the data formant of the line segment in Figure 1, and Figure 4 is a diagram to explain layout verification using the conventional slit method. It is a mask pattern diagram. 4.21, 44.52... Line segments parallel to the slit direction, 23.39.40, 42, 46.48... Line segments perpendicular to the slit direction, b, , c, e, r, o . p, q, r, u, v, w, x') start and end points of a line segment perpendicular to the slit direction, a, d, l, m... to a straight line parallel or perpendicular to the slit direction. The position where the connection point of two line segments touches;

Claims (1)

[Claims] One of the X-axis direction and the Y-axis direction is set as the slit direction,
Based on the position of the line segment parallel to the slit direction, the position of the start and end points of the line segment perpendicular to the slit direction, and the position where the connection point of two line segments touches a straight line parallel or perpendicular to the slit direction. A mask pattern verification method characterized by defining slits.