JPH0555378A - Cell layout method of integrated circuit - Google Patents

Abstract

PURPOSE:To enable an LSI formed through a computer-aided automated arrangement wiring method to be easily modified in circuit when the circuit is required to be modified by evaluation and to be lessened in manufacturing term. CONSTITUTION:In an automated arrangement wiring method, a pseudo-logic circuit composed of two or three cells is constituted. The cell 10 of the pseudo- logic circuit is arranged on both the ends of a cell row 12 as shown in the figure 4. The wiring 11 of the pseudo-logic circuit is laid out traversing a wiring region 13. By this setup, an LSI can be easily modified in circuit taking advantage of the cell is and wiring of the pseudo-logic circuit. A glass mask is required only to be modified in a process carried out after a wiring process. An LSI can be manufactured in a process carried out after wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of laying out cells of an integrated circuit for laying out various cells formed on a semiconductor substrate by computer processing.

[0002]

2. Description of the Related Art A logic circuit having a certain function such as a NAND or flip-flop is called a cell. In an integrated circuit, especially a large scale integrated circuit, a plurality of types of cells are mounted on a semiconductor substrate (chip). A computer is introduced into the design of such an integrated circuit, and lines or points (grid) having a certain vertical and horizontal intervals are assumed on the surface of the chip to facilitate the computer processing. Wiring is promised to follow said line or point. In addition, a rectangular frame (cell frame) that defines the contour of each cell is assumed, and each element that constitutes the cell is defined so as to be within the cell frame (some parts may protrude). By using this kind of cell frame concept and storing the pattern of each element of the cell configuration in the computer, all you need to do is input the size of the cell frame and the name of the logic circuit to be stored in it. It is possible to output the pattern. FIG. 2 shows a layout structure of such a computer-based integrated circuit design. Reference numeral 20 is a cell frame, and reference numeral 12 is a cell column. The cells are laid out in one row adjacent to each other in the cell frame. Reference numeral 21 is a wiring, and 13 is an area in which the wiring is laid out (wiring area)
Is. In the computer integrated circuit design, the layout and wiring are laid out so that the cells used in the logic circuit are minimized in the semiconductor substrate.

[0003]

If a circuit modification is required in the evaluation of a chip created by such a computer-based integrated circuit design, 1) the computer-based integrated circuit design is performed again.

2) Manual correction is made on the computer.

Is considered. In the manual correction of 2), the wiring area is designed to be the minimum by computer processing, and it takes a huge amount of time to correct only the wiring or to lay out one wiring in the wiring area. Further, since correction such as moving a cell is a very difficult correction, the work time can be shortened by redesigning the integrated circuit using the computer in 1). Also, when a cell is newly added, the work time can be shortened by performing the process 1). However, in 1), all the period from the integrated circuit design to the chip production and the glass mask used for the photolithography method are recreated. If only the wiring is corrected in 2), the glass mask will be the glass mask after the wiring. From the above, when the integrated circuit used for the computer is re-executed by the evaluation of the chip, a period for re-creating the chip and an extra glass mask are required.
Further, the manual correction has a problem that the correction takes a huge amount of time.

Therefore, the present invention solves such a problem, and an object of the present invention is to reduce the time until the chip is recreated by the circuit modification, which is caused by the evaluation of the chip created by the integrated circuit design using the computer. It is an object of the present invention to provide a method of laying out cells of an integrated circuit which is shortened.

[0007]

According to the present invention, there is provided a method for performing a layout of various cells formed on a semiconductor substrate and a layout of wirings between the cells by a calculation process along a grid having a predetermined interval. In addition to the cells formed on the substrate, a pseudo logic circuit composed of two or more cells is created, and the cells of the pseudo logic circuit are laid out at both ends of a cell row in which each cell is adjacent to the pseudo logic circuit on a computer. And a method of laying out cells of an integrated circuit characterized by processing.

[0008]

The present invention has the above-mentioned means. When a pseudo logic circuit is created, and the pseudo logic circuit is arranged and wired, when the logic circuit needs to be modified by chip evaluation, the correction period and This will shorten the chip production period.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 is a flow chart of computer processing according to an embodiment of the present invention. 30 is cell information (cell frame, cell data,
This is a data input means for inputting data necessary for layout and wiring such as pin information) and logic circuits to a computer. Reference numeral 31 is a cell layout means for laying out the cells of the logic circuit input at 30, and lays out as shown in the conventional cell layout structure of FIG. Reference numeral 32 is a pseudo logic circuit creating means for creating a pseudo logic circuit.
As shown in FIGS. 4A and 4B, as many pseudo logic circuits as two or three cells are formed as many as the number of cell rows laid out at 31. 4 (a) and FIG.
FIG. 4B shows an example of the pseudo logic circuit, and FIG.
Pseudo logic circuit with two 2-input NAND of 0, FIG.
(B) is a pseudo logic circuit having a configuration of 41 3-input NAND and 42 2-input NOR. Reference numeral 33 is a cell layout means of the proceedings logic circuit for laying out the cells of the pseudo logic circuit created in 32. As shown in the layout structure of the present invention in FIG.
One of the cells of the set of pseudo logic circuits is arranged at the right end and the other cell is arranged at the left end so as to contact both ends of the twelve cell columns. The cell columns in which the cells of the pseudo logic circuit are arranged are arranged in all cell columns or designated cell columns. Reference numeral 34 is a wiring layout means for laying out wirings based on the logic circuit and the pseudo logic circuit. As shown in FIG. 1, the wirings of the pseudo logic circuit of 11 are laid out so as to cross the wiring region of 13. .. Reference numeral 35 is a data output means for outputting the layout result from the computer.

In the evaluation of the chip created by the integrated circuit design using the computer of the present invention, when the circuit correction is required, the wiring is corrected by using the wiring of the pseudo logic circuit. .. In this case, since the wiring crossing the wiring area is used, it is not necessary to newly lay out the wiring in the very crowded wiring area, and the wiring can be easily corrected. A cell of a pseudo logic circuit is used to add a new cell. In this case, it is not necessary to add a new cell to the layout of the chip, and it is not necessary to re-design an integrated circuit using a computer, so that the chip can be easily modified.

[0011]

As described above, according to the present invention, it is possible to easily correct a chip created by a computer-aided integrated circuit design, reduce the number of glass masks to be repaired, and shorten the chip creation period. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a layout structure of the present invention.

FIG. 2 is an explanatory diagram showing a conventional cell layout structure.

FIG. 3 is a flowchart of computer processing according to the present invention.

FIG. 4 is an explanatory diagram of a pseudo logic circuit according to the present invention.

[Explanation of symbols]

 10 Pseudo-Logic Circuit Cell 11 Pseudo-Logic Circuit Wiring 12 Cell Row 13 Wiring Area 20 Cell Frame 21 Wiring 30 Data Input Means 31 Cell Layout Means 32 Pseudo Logic Circuit Creating Means 33 Pseudo Logic Circuit Cell Layout Means 34 Wiring Layout Means 35 Data output means 40 2 input NAND 41 2 input NOR 42 3 input NAND

Claims (1)

[Claims] 1. A method of performing a layout of various cells formed on a semiconductor substrate and a layout of wirings between the cells based on a logic circuit by a calculation process along a grid at predetermined intervals, the method comprising: In addition to the cells formed in the above, a pseudo logic circuit composed of two or more cells is created, and the cells of the pseudo logic circuit are laid out at both ends of a cell row in which each cell is adjacent, on a computer, A method for laying out a cell of an integrated circuit characterized by processing.