JPH0233641A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0233641A JPH0233641A JP63183463A JP18346388A JPH0233641A JP H0233641 A JPH0233641 A JP H0233641A JP 63183463 A JP63183463 A JP 63183463A JP 18346388 A JP18346388 A JP 18346388A JP H0233641 A JPH0233641 A JP H0233641A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor memory
- state
- memory device
- switch
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000013500 data storage Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005284 excitation Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】 る。[Detailed description of the invention] Ru.
第1図は本発明の一実施例を示す。図において、1は半
導体メモリ装置、2はCPUである。3はコネクタ4を
介して人力されたデータを格納するメモリ、5はメモリ
3をバックアップするバックアップ電源としてのバック
アップ電池である。FIG. 1 shows an embodiment of the invention. In the figure, 1 is a semiconductor memory device and 2 is a CPU. Reference numeral 3 denotes a memory for storing data input manually through the connector 4, and reference numeral 5 denotes a backup battery as a backup power source for backing up the memory 3.
6はバックアップ電池5をオン/オフするスライドスイ
ッチで、スイッチロッド7が第2図(a)の状態から右
方向に移動されたときオンされ、第2図(b)の状態か
ら左方向に移動されたとき、オフされる。スライドスイ
ッチ6のスライダは、メモリ3の誤消去を考慮して、通
常は、外部から触れられないようにしである。スイッチ
ロッド7は半導体メモリ装置lがデータ記憶再生装置8
に装填されたとき、第2図(a)の状態から右方向に移
動され、半導体メモリ装置1がデータ記憶再生装置8か
ら抜脱されても、移動された位置に残留する。また、ス
イッチロッド7は全消去装置9に装填されたとき、第2
図(a)の状態から左方向に移動され、半導体メモリ装
置1が全消去装置9から抜脱されても、移動された位置
に残留す2る。lOは接点で、半導体メモリ装置1をデ
ータ記憶再生装置8に装填した場合、データ記憶再生装
置8の接点11と接触し、全消去装置9に装填した場合
、全消去装置9の接点12と接触するようになっている
。13はソレノイドで、全消去装置9に設けてあり、ス
イッチ6がオフするようにスイッチロッド7を移動させ
るものである。Reference numeral 6 denotes a slide switch for turning on/off the backup battery 5, which is turned on when the switch rod 7 is moved to the right from the state shown in FIG. 2(a), and to the left from the state shown in FIG. 2(b). is turned off when The slider of the slide switch 6 is normally not touched from the outside in consideration of erroneous erasure of the memory 3. The switch rod 7 connects the semiconductor memory device l to the data storage and reproducing device 8.
When the semiconductor memory device 1 is loaded into the device, it is moved rightward from the state shown in FIG. Moreover, when the switch rod 7 is loaded into the total eraser 9, the second
Even if the semiconductor memory device 1 is moved leftward from the state shown in FIG. 2A and removed from the all-erasing device 9, it remains at the moved position 2. IO is a contact, and when the semiconductor memory device 1 is loaded into the data storage and playback device 8, it comes into contact with the contact 11 of the data storage and playback device 8, and when it is loaded into the total eraser 9, it comes into contact with the contact 12 of the total eraser 9. It is supposed to be done. A solenoid 13 is provided in the total eraser 9 and moves the switch rod 7 so that the switch 6 is turned off.
まず、メモリ3に何も記録されていない場合は、第2図
(a)に示すように、スライドスイッチ6はオフされて
いる。従って、この状態においてはバックアップ電流は
流れない。First, when nothing is recorded in the memory 3, the slide switch 6 is turned off, as shown in FIG. 2(a). Therefore, no backup current flows in this state.
次に、この半導体メモリ装置1をデータ記録再生装置8
に装填すると、スイッチロッド7は第2図(a) にお
いて右方向に突出部8tにより移動され、スライドスイ
ッチ6のスライダは閉位置まで移動されてスライドスイ
ッチ6がオンされる。すると、CPII 2によりメモ
リ3等の初期化が行なわれ、データの記録再生が可能な
状態にされる。他方、半導体メモリ装置1がデータ記録
再生装置8から抜脱されても、スライドスイッチ6のス
ライダは自動復帰せず残留し、スライドスイッチ6はオ
フすることなく、メモリ3のバックアップが続けられる
。半導体メモリ装置1をデータ記録再生装置8に装填し
た状態を第3図に示す。Next, this semiconductor memory device 1 is transferred to a data recording/reproducing device 8.
When loaded, the switch rod 7 is moved to the right in FIG. 2(a) by the protrusion 8t, and the slider of the slide switch 6 is moved to the closed position and the slide switch 6 is turned on. Then, the memory 3 and the like are initialized by the CPII 2, making it possible to record and reproduce data. On the other hand, even if the semiconductor memory device 1 is removed from the data recording/reproducing device 8, the slider of the slide switch 6 does not return automatically and remains, and the backup of the memory 3 continues without turning off the slide switch 6. FIG. 3 shows a state in which the semiconductor memory device 1 is loaded into the data recording/reproducing device 8.
次に、記tiされているデータを全て消去する場合、半
導体メモリ装置を全消去装置9に装填する。全消去の場
合は、ソレノイド13の励磁コイルに電流が流れてソレ
ノイド13が飛び出し、スイッチロット7を第2図(b
)の状態から左方向に移動させ、スライドスイッチ6を
オフする。従って、メモリ3のバックアップかなされな
くなり、メモリ3は全消去されることになる。この状態
を第4図に示す。Next, when erasing all of the recorded data, the semiconductor memory device is loaded into the total erasing device 9. In the case of complete erasure, current flows through the excitation coil of the solenoid 13, causing the solenoid 13 to pop out, causing the switch lot 7 to move as shown in Figure 2 (b).
) to the left and turn off the slide switch 6. Therefore, the memory 3 will no longer be backed up, and the memory 3 will be completely erased. This state is shown in FIG.
本実施例の半導体メモリ装置は、このように構成したの
で、工場から出荷した後、ユーザか実際に使用するまで
の間、電池の消耗を防止することができる。Since the semiconductor memory device of this embodiment is configured in this manner, it is possible to prevent battery consumption from being shipped from the factory until it is actually used by a user.
また、−旦、全データを消去した後、再ひ、使用するま
での間も、電池の消耗を防止することができる。Furthermore, even after erasing all data, the battery can be prevented from being consumed until it is used again.
[発明の効果]
以上説明したように、本発明によれば、上記のように構
成したので、未記録状態から最初のデータが記録される
までの間のTL源の消耗を防止することができるという
効果がある。[Effects of the Invention] As explained above, according to the present invention, with the above configuration, it is possible to prevent consumption of the TL source from the unrecorded state until the first data is recorded. There is an effect.
第1図は本発明実施例の半導体メモリ装置を示すブロッ
ク図、
第2図は実施例におけるスライドスイッチ6のオンオフ
を説明する説明図、
第3図は半導体メモリ装置tをデータ記録再生装置8に
装填した状態を示す一部破断断面図、第4図は半導体メ
モリ装置1を全消去装置9に装填した状態を示す断面図
である。
3・・・メモリ、
5・・・バックアップ電池、
6・・・スライドスイッチ。
6ス斗什゛スイ・干
第1図
第3図
第2図
第4図FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram illustrating on/off operation of a slide switch 6 in the embodiment, and FIG. 3 is a block diagram showing a semiconductor memory device t in an embodiment of the present invention. FIG. 4 is a partially cutaway cross-sectional view showing the loaded state. FIG. 4 is a cross-sectional view showing the semiconductor memory device 1 loaded into the full eraser 9. 3...Memory, 5...Backup battery, 6...Slide switch. 6 Sui Sui・Kan Figure 1 Figure 3 Figure 2 Figure 4
Claims (1)
前記バックアップ電源をメモリに電気的に接続し、開状
態で前記バックアップ電源を半導体メモリから電気的に
切り離し、かつ、与えた操作力を解除しても、前記開状
態または閉状態を保持するスイッチ を備えたことを特徴とする半導体メモリ装置。[Scope of Claims] 1) A semiconductor memory device having a semiconductor memory for storing data and a backup power source for backing up the semiconductor memory, the semiconductor memory device being capable of being turned from open to closed or from closed to open by operating force, and in a closed state. A switch that electrically connects the backup power source to the memory, electrically disconnects the backup power source from the semiconductor memory in an open state, and maintains the open state or the closed state even if the applied operating force is released. A semiconductor memory device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63183463A JPH0233641A (en) | 1988-07-25 | 1988-07-25 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63183463A JPH0233641A (en) | 1988-07-25 | 1988-07-25 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0233641A true JPH0233641A (en) | 1990-02-02 |
Family
ID=16136223
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63183463A Pending JPH0233641A (en) | 1988-07-25 | 1988-07-25 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0233641A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6044129B2 (en) * | 1980-10-16 | 1985-10-02 | ワイケイケイ株式会社 | Slide fastener element manufacturing method and equipment |
JPS61150088A (en) * | 1984-12-25 | 1986-07-08 | Toshiba Corp | Memory card |
JPS61269292A (en) * | 1985-05-24 | 1986-11-28 | Nec Corp | Mos random access memory device |
-
1988
- 1988-07-25 JP JP63183463A patent/JPH0233641A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6044129B2 (en) * | 1980-10-16 | 1985-10-02 | ワイケイケイ株式会社 | Slide fastener element manufacturing method and equipment |
JPS61150088A (en) * | 1984-12-25 | 1986-07-08 | Toshiba Corp | Memory card |
JPS61269292A (en) * | 1985-05-24 | 1986-11-28 | Nec Corp | Mos random access memory device |
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