JP4461836B2 - Disk drive device - Google Patents

Description

  The present invention relates to a disk drive device for recording or reproducing a disk-shaped recording medium such as a magneto-optical disk.

  As a recording medium for recording and reproducing digital audio data, a mini disk (MD), which is a magneto-optical disk having a diameter of 64 mm, housed in a cartridge is widely used. A system for recording / reproducing audio data with respect to a mini-disc is very excellent as a portable audio data recording / reproducing device because the disc itself is small and inexpensive.

  In a disc recording / reproducing system such as an MD, when reproducing audio data recorded on a disc, it is necessary to first read out disc management information such as TOC and FAT, and then read out audio data. This reading time is usually spent several seconds to several tens of seconds. For this reason, when the recording / reproducing system enters the sleep state, the memory storing the disk management information is cleared, so that it takes several seconds to several tens of seconds as the read time again at the next operation.

  In order to reduce the reading time of such disc management information such as TOC and FAT, in a general disc recording / reproducing system, a memory holding function for supplying power only to a memory for storing disc management information even during sleep Is provided.

  In order to provide such a memory holding function, a sub power circuit with a small capacity is provided in addition to the main power circuit, and the sub power circuit is started immediately before the main power circuit is turned off, and the disk management information It is sufficient to turn on the power to the memory for storing.

  As a result, when returning from the sleep state, it is not necessary to read out disc management information such as TOC information or FAT again, and audio data can be recorded or reproduced immediately.

  By the way, the power supply circuit is normally configured to supply a high level signal to the chip enable terminal for voltage output and to supply a low level signal to the chip enable terminal to stop voltage output.

  Therefore, in order to start the sub power supply circuit immediately before the main power supply circuit is turned off and then continue to operate the sub power supply circuit, the power supply to the system controller is stopped. A signal cannot be supplied directly to the chip enable terminal, but a high level signal must be supplied to the chip enable terminal via a special logic circuit such as a flip-flop circuit.

  The present invention solves such a problem. A power supply voltage is applied only to a memory storing disk management information in a sleep state with a very simple circuit configuration without using a special logic circuit. An object of the present invention is to provide a disk drive device that can be continued.

  A disk drive device according to the present invention is a disk drive device that records or reproduces a removable disk-shaped recording medium, and includes a volatile memory that stores management information of the disk-shaped recording medium, and a control that performs control processing. A circuit, a main power supply circuit for generating a DC power supply voltage for operating each circuit including the control circuit and the volatile memory, and a sub power supply for generating at least a DC power supply voltage for operating the volatile memory A sub-power supply circuit that outputs at least a DC power supply voltage for operating the volatile memory; and when the terminal level is high, the sub power supply circuit outputs the DC power supply voltage from the output terminal. A chip enable terminal that stops the output of the DC power supply voltage from the output terminal when the terminal level is low. The diode has an anode connected to the output terminal of the sub power supply circuit, a cathode connected to the chip enable terminal, and the control circuit receives a DC power supply voltage generated from the main power supply circuit. When stopping, the operation of the main power supply circuit is stopped after setting the chip enable terminal to high level.

  In the disk drive device according to the present invention having such a configuration, the output of the sub power supply circuit is connected to the chip enable terminal of the sub power supply circuit that generates a DC power supply voltage for operating the volatile memory storing the management information. By supplying the voltage via the diode, the operation of the sub power supply circuit is maintained.

  As a result, in the disk drive device according to the present invention, the power supply voltage can be continuously applied only to the memory storing the disk management information in the sleep state with a very simple circuit configuration without using a special logic circuit. it can.

  Hereinafter, a magneto-optical disk recording / reproducing apparatus (disk recording / reproducing apparatus), which is a disk-shaped magneto-optical recording medium to which the present invention is applied, will be described as the best mode of the present invention.

  The disk recording / reproducing apparatus of this embodiment is an apparatus for recording and reproducing data with respect to a magneto-optical disk (hereinafter simply referred to as disk 1) having a diameter of about 6.4 cm housed in a cartridge.

  The disc recording / reproducing apparatus of this embodiment is a small portable device, and its housing is large enough to be held by one person with one hand. The disk recording / reproducing apparatus of this embodiment can incorporate a battery, and can record and reproduce music and audio by itself. The disc recording / reproducing apparatus of this embodiment can be connected to a host device such as a personal computer via a USB interface. In this case, the disc recording / reproducing device functions as an external storage device of the host device.

  Next, the configuration of the disk recording / reproducing apparatus 10 according to the embodiment of the present invention will be described.

  FIG. 1 is a block diagram of the disk recording / reproducing apparatus 10.

  A disc recording / reproducing apparatus 10 is connected via a USB cable 3 between a media drive unit 11 for writing and reading data to / from the disc 1 and a personal computer (hereinafter referred to as a PC) 2 serving as a host device of the apparatus. USB (Universal Serial Bus) interface circuit 12 that performs data transfer, cache memory 13, management information memory 14, memory transfer controller 15 that controls data transfer, and audio that is written to and read from media drive unit 11 An audio processing unit 16 that performs processing on data, a system controller 17 that performs central control of the apparatus, an operation / display unit 18, and a power management unit 20 are provided.

  The media drive unit 11 is loaded with a disk 1 stored in a cartridge. The disc 1 can be freely attached to and detached from the media drive unit 11. The media drive unit 11 writes and reads data to and from the loaded disk 1.

  The USB interface circuit 12 is a circuit that performs data transmission / reception control with the PC 2 via the USB cable 3 connected to the USB connector 12a in accordance with the USB data transfer standard. The USB connector 12a is a connector into which the USB cable 3 is inserted. The disc recording / reproducing apparatus 10 functions as one of external devices having the host device as the PC 2 by connecting the USB cable 3 to the USB connector 12a and connecting the USB cable 3 to the PC 2. It becomes.

  The cache memory 13 is a buffering circuit that temporarily stores audio data read from the disk 1 by the media drive unit 11 and audio data to be written to the disk 1.

  The management information memory 14 is a volatile memory composed of a so-called DRAM. The management information memory 14 stores disk management information read from the disk 1 by the media drive unit 11 and various special information. For example, disk management information such as TOC (Table Of Contents) and FAT (File Allocation Table) read from the disk 1 by the media drive unit 11 is stored.

  The memory transfer controller 15 controls writing and reading of data with respect to the cache memory 13 and the management information memory 14.

  The audio processing unit 16 is an encoder and a decoder that are used when data is recorded / reproduced with the USB cable 3 removed. The audio processing unit 16 includes, as an audio signal input system, an analog audio signal input unit such as a line input circuit / microphone input circuit, an A / D conversion circuit that converts an analog input audio signal into digital, and digital audio. It has a data input part. The audio processing unit 16 includes, as an audio output system, an analog audio signal output unit such as a digital audio data output unit, a D / A conversion circuit that converts digital audio data into an analog signal, and a line output circuit / headphone output circuit. Have. The audio processing unit 16 has an ATRAC compression / decompression circuit.

  The system controller 17 performs overall control in the disk recording / reproducing apparatus 10 and communication control with the connected PC 2. Further, the system controller 17 can communicate with the PC 2 connected via the USB interface circuit 12, and receives a command such as a write request and a read request, and transmits status information and other necessary information. .

  The system controller 17 instructs the media drive unit 11 to read the disc management information such as TOC and FAT when the disc 1 is loaded in the media drive unit 11, and the disc read by the media drive unit 11 is read out. Management information is stored in the management information memory 14. The system controller 17 can grasp the track recording state of the disk 1 by referring to the disk management information. Further, by referring to the disk management information such as FAT, the cluster structure of the user area can be grasped, and the PC 2 can respond to an access request to the user area. Further, the system controller 17 executes the disk authentication process and other processes using the unique ID and the hash value, transmits these values to the PC 2, and executes the disk authentication process and other processes on the PC 2.

  The operation / display unit 18 includes various operation units such as a play button, a stop button, a pause button, a recording start button, a jog dial (rotary push switch), and a display unit including, for example, an LCD (Liquid Crystal Display). Has been. The operation / display unit 18 supplies input information from various operation units by the user to the system controller 17. Further, the operation / display unit 18 displays information such as text data and GUI provided from the system controller 17 on the display unit.

  Such a disc recording / reproducing apparatus 10 performs two operations: a stand-alone operation that operates without being connected to the PC 2, and a slave operation that operates by being connected to the PC 2 via the USB cable 3.

  When recording an audio signal on the disc 1 by the stand-alone operation, the disc recording / reproducing apparatus 10 receives an audio signal input from the outside via the input system of the audio processing unit 16 and the audio processing unit 16 uses the ATRAC method. The compressed audio data is transferred to the media drive unit 11. The media drive unit 11 records the transferred audio data in an empty area of the user area.

  When the audio signal is reproduced from the disc 1 in the stand-alone operation, the disc recording / reproducing apparatus 10 sends a reproduction instruction of the audio data of the title designated by the user via the operation / display unit 18 to the media drive unit 11. give. The media drive unit 11 reads data from the disc 1 in accordance with a given reproduction command. The audio processing unit 16 expands the audio data read from the media drive unit 11 by the ATRAC method, and outputs the expanded audio signal to the outside through the output system.

  When data is recorded from the PC 2 to the disk 1 in the slave operation, a write command is input from the PC 2 to the disk recording / reproducing apparatus 10 via the USB interface circuit 12 together with the write data. The disc recording / reproducing apparatus 10 temporarily stores the input write data in the cache memory 13 and then transfers it to the media drive unit 11. The media drive unit 11 writes the input data to the cluster at the address specified by the write command.

  When data is transferred from the disk 1 to the PC 2 in the slave operation, a read command is input from the PC 2 to the disk recording / reproducing apparatus 10 via the USB interface circuit 12. The media drive unit 11 reads data from the address specified by the read command. The read data is temporarily stored in the cache memory 13 by the memory transfer controller 12. However, when the data has already been stored in the cache memory 13, reading by the media drive unit 11 is not necessary. The disk recording / reproducing apparatus 10 transfers the data stored in the cache memory 13 to the PC 2 via the USB cable 3.

  Next, the power management unit 20 of the disk recording / reproducing apparatus 10 will be described.

The disc recording / reproducing apparatus 10 includes the power management unit 20 as described above. The power supply circuit unit 20 is a DC voltage source that supplies a stabilized DC power supply voltage (V _DD ) to the entire apparatus and manages the supply state.

  The power management unit 20 manages three states: a normal operation state in which power is supplied to all circuits, a power stop state, and a sleep state.

The normal operation state is a state in which a normal operation that can perform a recording operation, a reproduction operation, and the like is possible. In the normal operation state, the power management unit 20 supplies the power supply voltage (V _DD ) to all the circuits in order to operate all the circuits of the disc recording / reproducing apparatus 10. That is, in the normal operation state, the power management unit 20 includes the media drive unit 11, the USB interface circuit 12, the cache memory 13, the management information memory 14, the memory transfer controller 15, the audio processing unit 16, the system controller 17, and the operation / display. A stabilized power supply voltage (V _DD ) is supplied to the unit 18.

The power supply stop state is a state in which supply of power supply voltage (V _DD ) to all circuits is stopped and no operation is performed. In the power stop state, the power management unit 20 stops supplying the power supply voltage (V _DD ) to all the circuits and stops its own operation, and stops the operation of all the circuits of the disc recording / reproducing apparatus 10.

  The sleep state is a state in which the operation is temporarily stopped and power is supplied only to the minimum necessary circuits. By being able to enter the sleep state, current consumption while the operation is stopped can be suppressed, and the startup time at the time of restart can be made shorter than when starting from the power stop state.

Specifically, the power supply management unit 20 supplies the power supply voltage (V _DD ) to the volatile management information memory 14 in which disk management information such as TOC and FAT is stored in the sleep state. Supply of power supply voltage (V _DD ) to the circuit is stopped. By supplying the power supply voltage (V _DD ) to the management information memory 14, the disk management information such as TOC and FAT stored in the management information memory 14 is not erased, and the information is used after restarting. Can do. Therefore, in the disk recording / reproducing apparatus 10, it takes several seconds to several tens of seconds to read disk management information such as TOC and FAT, but since this reading time is not required, the starting time at the time of restart can be shortened.

  A circuit configuration of the power management unit 20 that realizes the sleep state as described above will be described.

A circuit configuration of the power management unit 20 is shown in FIG. In FIG. 2, a thick line is a power line through which a power supply voltage (V _DD ) flows, and a thin line is a control line through which a control signal is transmitted.

  The power management unit 20 is provided with a main power terminal 21 and a sub power terminal 22.

The main power supply terminal 21 is a terminal from which a power supply voltage (V _DD ) is output during a normal operation state. The main power supply terminal 21 is connected to the power supply input terminal of each circuit in the disc recording / reproducing apparatus 10 including the system controller 17.

The sub power supply terminal 22 is a terminal from which a power supply voltage (V _DD ) is output during the sleep state. The sub power supply terminal 22 is connected to a power supply input terminal of a circuit that operates during the sleep state, including at least the management information memory 14.

  The power management unit 20 also includes a battery 23, a main power circuit 24, a sub power circuit 25, a first switch 26, a first diode 27, a second diode 28, and a third diode 29. And a second switch 30 and an activation control circuit 31.

The main power supply circuit 24 is a circuit that generates a power supply voltage (V _{DD — 1} ) for operating each circuit during a normal operation state. The output voltage of the battery 23 is input to the main power supply circuit 24 from the input terminal (IN_1). The main power supply circuit 24 steps up or down the input battery voltage and generates a power supply voltage (V _{DD — 1} ), which is a stabilized DC voltage regardless of the load, from the output terminal (OUT — 1).

The output terminal (OUT_1) of the main power supply circuit 24 is connected to the main power supply terminal 21. Accordingly, the power supply voltage (V _{DD — 1} ) generated from the main power supply circuit 24 is supplied to each circuit connected to the main power supply terminal 21.

The output terminal (OUT_1) of the main power supply circuit 24 is also connected to the sub power supply terminal 22 via the first switch 26. The first switch 26 is controlled to be turned on and off by an FFCLR signal that is a control signal output from the system controller 17. Specifically, the first switch 26 connects between the output terminal (OUT_1) of the main power supply circuit 24 and the sub power supply terminal 22 when the logic level of the FFCLR signal is high, and the logic level of the FFCLR signal is When it is low, the output terminal (OUT_1) of the main power supply circuit 24 and the sub power supply terminal 22 are opened. Therefore, the power supply voltage (V _{DD — 1} ) generated from the main power supply circuit 24 is supplied to the management information memory 14 connected to the sub power supply terminal 22 when the logic level of the FFCLR signal is high, and the logic level of the FFCLR signal is When it is low, it is not supplied to the management information memory 14 connected to the sub power terminal 22. Note that the logic level of the FFCLR signal is low when the power supply voltage (V _DD ) is not supplied to the system controller 17.

The sub power supply circuit 25 is a circuit that generates a power supply voltage (V _{DD — 2} ) for operating the management information memory 14 during the sleep state. The output voltage of the battery 23 is input to the sub power circuit 25 from the input terminal (IN_2). The sub power supply circuit 25 boosts or steps down the input battery voltage, and generates a power supply voltage (V _{DD_2} ), which is a stabilized DC voltage regardless of the load, from the output terminal (OUT_2).

The output terminal (OUT_2) of the sub power supply circuit 25 is connected to the sub power supply terminal 22 via the first diode 27. The first diode 27 has an anode connected to the output terminal (OUT_2) and a cathode connected to the sub power supply terminal 22. Therefore, the power supply voltage (V _{DD — 2} ) generated from the sub power supply circuit 25 is supplied to each circuit connected to the sub power supply terminal 22. Further, since the first diode 27 is provided, even when the first switch 26 is closed, the current generated from the main power supply circuit 24 is supplied to the output terminal (OUT_2 of the sub power supply circuit 25). ) Is prevented from flowing back.

The voltage level of the output terminal (OUT_2) of the sub power supply circuit 25 is input to the system controller 17 as a DRAM_HOLD_DET signal that is a control signal. Therefore, the system controller 17 can determine that the sub power supply circuit 25 is operating if the logic level of the DRAM_HOLD_DET signal is high, and the sub power supply circuit 25 is operating if the logic level of the DRAM_HOLD_DET signal is low. It can be judged that there is no. The voltage (V _{DD_1} ) generated from the main power supply circuit 24 is set to be the same as or lower than the voltage (V _{DD_2} ) generated from the sub power supply circuit 25. As a result, even when the first switch 26 is closed, the output current of the sub power supply circuit 25 flows back to the output terminal (OUT_1) of the main power supply circuit 24 due to the voltage drop caused by the first diode 27. There is nothing.

The second diode 28 has an anode connected to the output terminal (OUT_2) of the sub power supply circuit 25 and a cathode connected to the chip enable terminal (CE) of the sub power supply circuit 25. The sub power supply circuit 25 operates when a control signal having a high logic level is input to the chip enable terminal (CE), and operates when a control signal having a low logic level is input to the chip enable terminal (CE). Stop. That is, when a control signal having a high logic level is input to the chip enable terminal (CE), a stabilized power supply voltage (V _{DD_2} ) is generated from the output terminal (OUT_2), and the logic level is _supplied to the chip enable terminal (CE). When a low control signal is input, no voltage is generated from the output terminal (OUT_2).

That is, in the sub power supply circuit 25, the generated power supply voltage (V _{DD —} 2) is _fed back to the chip enable terminal (CE) as a control signal having a high logic level via the second diode. For this reason, once the operation of the sub power supply circuit 25 starts, self-feedback is applied to the chip enable terminal (CE), and the operation continues even if no control signal is given from the outside.

  A DRAM_ALONE signal, which is a control signal generated from the system controller 17, is input to the chip enable terminal (CE) of the sub power supply circuit 25 via the third diode 29. The third diode 29 has an anode connected to the system controller 17 and a cathode connected to a chip enable terminal (CE).

  Therefore, the sub power supply circuit 25 starts the operation when the logic level of the DRAM_ALONE signal becomes high, and thereafter continues the voltage generation operation even if the logic level of the DRAM_ALONE signal becomes low.

  The chip enable terminal (CE) of the sub power supply circuit 25 is connected to the ground via the second switch 30. The second switch 30 is ON / OFF controlled by a DRAM_VDD_CLR signal that is a control signal output from the system controller 17. Specifically, the second switch 30 connects the chip enable terminal (CE) and the ground when the logic level of the DRAM_VDD_CLR signal is high, and the chip enable terminal when the logic level of the DRAM_VDD_CLR signal is low. Open between (CE) and ground.

  Therefore, when the logic level of the DRAM_VDD_CLR signal is high, the sub power supply circuit 25 sets the logic level of the chip enable terminal (CE) to low, thereby stopping the voltage generation operation, and thereafter, the logic level of the DRAM_VDD_CLR signal. Even if becomes low, the operation continues to stop.

The activation control circuit 31 is a circuit for causing the main power supply circuit 24 to start a voltage generation operation. The activation control circuit 31 receives an activation start command from the user using the operation button of the operation / display unit 18 when the power supply is stopped or in the sleep state (in this case, the operation of the main power supply circuit 24 is stopped). Then, the main power supply circuit 24 is activated. As a result, a power supply voltage (V _{DD — 1} ) is generated from the main power supply circuit 24, and the power supply voltage (V _DD ) is input to all the circuits of the disc recording / reproducing apparatus 10.

  Next, the control contents of the operation when shifting from the normal operation state to the sleep state and vice versa will be described with reference to the timing charts of FIGS. 3 and 4, the timing charts in FIGS. 3 and 4 are: (A) DRAM_ALONE signal, (B) DRAM_VDD_CLR signal, (C) DRAM_HOLD_DET signal, (D) FFCLR signal, (E) SLEEP signal, (F) Is the output voltage (VDD_1) of the main power supply circuit 24, (G) is the output voltage (VDD_2) of the sub power supply circuit 25, (H) is the terminal voltage of the main power supply terminal 21, and (I) is the terminal voltage of the sub power supply terminal 22. , (J) show the types of power supply circuits driving the management information memory 14, respectively.

  First, the control operation when transitioning from the normal operation state to the sleep state will be described with reference to the timing chart of FIG.

  During the normal operation state (time t11), the main power supply circuit 24 operates and the sub power supply circuit 25 stops. At time t11, the DRAM_ALONE signal and the DRAM_VDD_CLR signal are both low, and the FFCLR signal is high. Since the FFCLR signal is high, the first switch 26 is closed, and the output voltage (VDD_1) of the main power supply circuit 24 is supplied to each of the main power supply terminal 21 and the sub power supply terminal 22. That is, the management information memory 14 is driven by the voltage generated by the main power supply circuit 24. At time t11, since the sub power supply circuit 25 is stopped, the DRAM_HOLD_DET signal is low.

  Subsequently, a transition operation to the sleep state is performed by the user at time t12. When a transition operation to the sleep state is performed, the system controller 17 that has received the operation sets the DRAM_ALONE signal to high. When the DRAM_ALONE signal becomes high, the sub power supply circuit 22 starts operating in response to it and generates an output voltage (VCC_2). The generated output voltage (VCC_2) is supplied to the sub power terminal 22. That is, the management information memory 14 is driven by the voltages generated by both the main power supply circuit 24 and the sub power supply circuit 25. Further, since the sub power supply circuit 25 operates, the DRAM_HOLD_DET signal also becomes high.

  When the operation of the sub power supply circuit 22 is started at time 12, the output voltage (VCC_2) is fed back to the chip enable terminal (CE). Therefore, after that, the DRAM_ALONE signal goes low, but the sub power supply circuit 22 continues to operate.

  Subsequently, the system controller 17 detects that the DRAM_HOLD_DET signal becomes high, and sets the FFCLR signal to low at time t13 after a predetermined time. When the FFCLR signal becomes low, the first switch 26 is opened, and the voltage supply from the main power supply circuit 24 to the sub power supply terminal 22 is cut off. When the voltage supply from the main power supply circuit 24 to the sub power supply terminal 22 is cut off, only the voltage from the sub power supply circuit 25 is supplied to the sub power supply terminal 22. That is, the management information memory 14 is driven by the voltage generated only by the sub power supply circuit 25.

  Subsequently, the system controller 17 issues a sleep command at time t14 after a predetermined time has elapsed after setting the FFCLR signal to low. When the sleep command is issued from the system controller 17, the operation of the main power supply circuit 24 is stopped.

As a result, the main power supply circuit 24 is completely stopped, and a sleep state in which only the sub power supply circuit 25 is operating is entered. The first switch 26 is open. Therefore, the output voltage (VDD_2) of the sub power circuit 25 is output from the sub power terminal 22 and no voltage is output from the main power terminal 21. Thus, although the power supply voltage in the management information memory 14 (V _DD) is supplied, the supply of the power supply voltage (V _DD) is stopped in the other circuit (system controller 17, etc.).

  Next, the control operation when transitioning from the sleep state to the normal operation state will be described with reference to the timing chart of FIG.

  In the sleep state (time t21), the sub power supply circuit 25 operates and the main power supply circuit 24 is stopped. At time t21, the DRAM_ALONE signal and the DRAM_VDD_CLR signal are both low, and the FFCLR signal is also low. Since the FFCLR signal is low, the first switch 26 is open, and the output voltage (VDD_2) of the sub power circuit 25 is supplied only to the sub power terminal 22. That is, the management information memory 14 is driven by the voltage generated by the sub power supply circuit 25. At time t21, since the sub power supply circuit 25 is operating, the DRAM_HOLD_DET signal is high.

Subsequently, a transition operation to the normal operation state is performed by the user at time t22. When the transition operation to the normal operation state is performed, the main power supply circuit 24 starts operation. For this reason, the power supply voltage (V _DD ) is supplied to other circuits including the system controller 17, and the operation of these circuits starts.

  Subsequently, at time t23, the system controller 17 that has started operating due to the supply of the power supply voltage first sets the FFCLR signal to high. When the FFCLR signal becomes high, the first switch 26 is closed and voltage supply from the main power supply circuit 24 to the sub power supply terminal 22 is started. That is, the management information memory 14 is driven by voltages generated by both the main power supply circuit 24 and the sub power supply circuit 25.

  Subsequently, after setting the FFCLR signal to high, the system controller 17 sets the DRAM_VDD_CLR signal to high at time t24 after a predetermined time has elapsed. When the DRAM_VDD_CLR signal becomes high, the second switch 30 is closed and the chip enable terminal of the sub power supply circuit 25 becomes low. For this reason, the operation of the sub power supply circuit 25 is stopped.

  As a result, the operation of the sub power supply circuit 25 is completely stopped, and a normal operation state in which only the main power supply circuit 24 is operating is entered. Accordingly, the output voltage (VDD_1) of the main power supply circuit 24 is output from the main power supply terminal 21 and the sub power supply terminal 22.

As described above, in the disk recording / reproducing apparatus 10, the output voltage of the sub power circuit 25 is connected to the chip enable terminal (CE) of the sub power circuit 25 that generates the power voltage (V _DD ) for operating the management information memory 14. (OUT_2) is supplied via the second diode 28, and this maintains the operation of the sub power supply circuit 25 in the sleep state.

  For this reason, the disc recording / reproducing apparatus 10 can continue by applying a power supply voltage only to the management information memory 14 in the sleep state with a very simple circuit configuration without using a special logic circuit.

  Note that the disc recording / reproducing apparatus 10 may hold the power source of the management information memory 14 only when the disc 1 is loaded and when the transition is made from the normal state to the sleep state. That is, when the disk 1 is not loaded, the management information memory 14 may not be held.

It is a block block diagram of the disc recording / reproducing apparatus of embodiment of this invention. It is a circuit diagram of a power management part. It is the timing chart which showed the control and operation | movement content at the time of changing from a normal operation state to a sleep state. It is the timing chart which showed the control and operation | movement content at the time of changing from a sleep state to a normal operation state.

Explanation of symbols

  1 disc, 10 disc recording / reproducing apparatus, 11 media drive unit, 14 management information memory, 17 system controller, 18 operation / display unit, 20 power management unit, 21 main power supply terminal, 22 sub power supply terminal, 23 battery, 24 main power supply Circuit, 25 sub power supply circuit, 26 first switch, 27 first diode, 28 second diode, 29 third diode, 30 second switch, 31 start control circuit

Claims (3)

In a disk drive device for recording or reproducing a detachable disk-shaped recording medium,
A volatile memory for storing management information of the disk-shaped recording medium;
A control circuit for performing control processing;
A main power supply circuit for generating a DC power supply voltage for operating each circuit including the control circuit and the volatile memory;
A sub power supply circuit for generating a DC power supply voltage for operating at least the volatile memory;
A diode and
The sub power supply circuit outputs at least a DC power supply voltage for operating the volatile memory, and outputs the DC power supply voltage from the output terminal when the terminal level is high, and the terminal level is low. A chip enable terminal for stopping the output of the DC power supply voltage from the output terminal,
The diode has an anode connected to the output terminal of the sub power supply circuit and a cathode connected to the chip enable terminal.
When the DC power supply voltage generated from the main power supply circuit is stopped, the control circuit stops the operation of the main power supply circuit after setting the chip enable terminal to a high level. . A first inflow prevention circuit for preventing a current output from the main power supply circuit from flowing into an output terminal of the sub power supply circuit when the operation of the sub power supply circuit is stopped;
And a second inflow prevention circuit for preventing a current output from the sub power circuit from flowing into an output terminal of the main power circuit when the operation of the main power circuit is stopped. 1. The disk drive device according to 1. 3. The disk drive device according to claim 2, wherein the control circuit sets the chip enable terminal to a low level after the main power supply circuit is activated.

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