JPH02232752A - Memory control method - Google Patents

Abstract

PURPOSE:To reduce the power consumption by selecting a memory element in a memory area which is not used so that unnecessary electric power is not supplied. CONSTITUTION:A queued state detecting means 33 judges whether an apparatus body is being operated or a power source is disconnected, and outputs a queued state instructing signal, when it is disconnected. To each memory element, electric power is supplied from a battery 32 through a switch 34. An instruction of opening/closing of the switch 34 is executed by a memory element instructing signal from a memory element instructing means 35, and when the switch 34 is in an open state, no electric power is supplied to the memory element connected to the switch 34 of an open state.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides that, when there is a memory area that is not used for storing information in a memory space made up of a plurality of memory elements, unnecessary power is not supplied to the corresponding memory element. The present invention relates to a memory management method.

BACKGROUND OF THE INVENTION Memory management devices that implement conventional memory management methods include, for example, memory management devices for battery-backed RAM disks in laptop computers and the like.

FIG. 6 shows a configuration diagram of this conventional memory management device, in which 61 is a memory element, 62 is a storage battery, and 63 is a standby state detection means.

In the conventional memory management device configured as described above, the standby state detection means 63 monitors the power supply voltage supplied from the device main body and determines whether the device main body is in operation or is powered off. , if the main body of the device is powered off, a standby state instruction signal is output. The memory element 61 is supplied with power from the storage battery 62, and although it continues to hold stored information in response to the standby state instruction signal, it enters a low power consumption state in which reading and writing operations are not performed, reducing power consumption of the storage battery.

Problems to be Solved by the Invention However, with the above configuration, even when there is only a small amount of information to be stored, power is supplied to memory elements that are not used to store information, so there is a problem that unnecessary power is consumed. had.

In view of this, it is an object of the present invention to provide a memory management method characterized by selecting memory elements in a memory area that are not used for information storage and not supplying unnecessary power.

Means for Solving the Problems The present invention provides that when there is a memory area that is not used for storing information in a memory space that is composed of a plurality of memory elements, the memory area is selected from among the memory elements that make up the memory space. This is a memory management method characterized by selecting a memory element completely included in an address assigned to a memory element, and not supplying unnecessary power to the selected memory element.

Effect: By using the method described above, the present invention allows normal operation to be performed regardless of whether the main body of the device is in operation or the power is turned off, without supplying unnecessary power to memory elements that are not used for storing information. , power consumption can be reduced.

Embodiment FIG. 1 shows a configuration diagram of a RAM disk management device which is a memory management device that implements a memory management method according to an embodiment of the present invention. In FIG. 1, 31 is a memory consisting of memory elements 0 to 1!5, 32 is a storage battery that supplies power to each memory element 31, 33 is a standby state detection means, and 34 is a link between each memory element and the storage battery 32. The switch provided, 35, is a memory element indicating means.

The operation of the memory management device of this embodiment configured as described above will be explained below.

The standby state detection means 33 monitors the power supply voltage supplied from the main body of the device, determines whether the main body of the device is in operation or in a state where the power is turned off, and if the main body of the device is in a state where the power is turned off, it is in a standby state. Outputs an instruction signal. Each memory element is supplied with power from the storage battery 32 via the switch 34, and the standby state instruction signal continues to hold stored information, but it enters a low power consumption state in which reading and writing operations are not performed, reducing power consumption of the storage battery. . The opening/closing instruction of the switch 34 is performed by a memory element instruction signal from a memory element instruction means 35. When switch 34 is open, no power is supplied to memory elements connected to switch 34 that is open.

FIG. 2 shows a block diagram of the memory element indicating means 35. As shown in FIG. The operation will be explained below using FIG. 2. In FIG. 2, numeral 36 is a register that holds information instructing the memory element, and the information to be held is input from the data path of the main body of the device and is instructed to be held by a write control signal.

Next, a method of creating information indicating a memory element to be held in the register 36 will be explained. FIG. 3 shows the address assignment of each memory element in the memory space shown in FIG. Figure 4 (a>r (b). (c), (d
) indicates the relationship between the memory area not used for information storage and the power supply to the memory element.

In the memory space addressed as shown in Fig. 4, if an unused memory area is indicated by a start address and an end address, and a memory area as shown in Fig. 4(a) is pointed, the lower address of memory element 2 and the memory Since the upper address of element 3 is used for information storage, power supply to memory elements 2 and 3 must not be stopped. Similarly, the fourth
In the case of FIG. 2B, the upper and lower addresses of the memory element 2 are used to store information, so the power supply must not be stopped. In the case of FIG. 4(C), the lower address of memory element 2 and the upper address of memory element 4 are used for information storage, so memory element 2. However, the address assigned to memory element 3 is completely included in the area indicated by t between the start address and the end address, so it is not used for information storage. , power supply may be stopped. In the case of FIG. 4(d), the lower address of mesori element 1 and the upper address of memory element 4 are used for information storage, so memory elements 1 and 4
The power supply to the memory elements 3 and 4 shall not be interrupted.
Since the address assigned to is completely included in the area pointed to by the start address and the end address, it is not used for information storage, and the power supply may be stopped.

As described above, according to this embodiment, the only change to the operator nog system running in the main body of the device is the addition of software for managing the memory element indicating means 35. Is the device operating without supplying any power to memory elements that are not used for memory?1! Normal operation can be performed even when the power is turned off, and power consumption can be reduced slightly.

Note that the storage capacity of each memory element does not have to be the same,
Furthermore, in consideration of the versatility of the memory management method of the present invention when porting it to various operating systems, it is also possible to create memory element instruction information using a management table as shown in FIG. Further, although a semiconductor memory is used as the memory element in this embodiment, the present invention can be applied to any information recording medium such as a hard disk.

Effects of the Invention As described in 2, according to the present invention, it is possible to control whether the device is in operation or when the power is turned off, without supplying unnecessary power to memory elements that are not used for storing information. Normal operation can be performed regardless of the situation, and power consumption can be reduced, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a memory management device according to a first embodiment of the present invention, FIG. 2 is a configuration diagram of a memory element indicating means of the same embodiment, and FIG. A diagram showing the address assignment of each memory element in the memory space, Figure 4 is a diagram showing the relationship between the memory area not used for information storage and the power supply of the memory element, and Figure 5 is a diagram showing the storage capacity of each memory element. FIG. 6 is a diagram illustrating an example of a management table used to create instruction information for a memory element even when the numbers are not the same. FIG. 6 is a diagram showing the structure of a conventional memory management device. 31...Memory, 32...Storage battery, 33.
...standby state detection means, 34...switch,
35...Memory element instruction means, 36...Register. Name of agent Patent attorney Shigetaka Awano

Claims (1)

[Claims] If there is a memory area that is not used for information storage in a memory space made up of a plurality of memory elements, the address allocated to the memory area from among the memory elements that make up the memory space completely encompasses the memory area. A memory management method comprising selecting a memory element and not supplying unnecessary power to the selected memory element.