JPH01154396A - Refresh control circuit for dynamic ram - Google Patents

Abstract

PURPOSE:To prohibit a refresh to an area except a storing area and to reduce a refresh current by providing an information storing area specifying means, a gate circuit disposed in the pre-stage of the inverse of RAS, the inverse of CAS inputs and a gate control means. CONSTITUTION:A DIP switch 25 is operated to specify the using area of a DRAM 21. At the time of supplying a power, the setting contents of the switch 25 are held to a memory managing latch 23 and a specific RAM 21 or only an element area determined by an input signal is refreshed through a gate 22. In the gate circuit 22, the initial one of the inverse of RAS signal, the inverse of CAS signal is masked by a control signal and a next inputted one is directly applied to the inverse of RAS input and the inverse of CAS input by the control signal 'L' to refresh to the element area determined by an input according to a second gate input. According to this constitution, a consuming current is reduced by a required minimum refresh.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention [Summary] The present invention is based on a dynamic RAM. The purpose of this invention is to reduce the current required for refreshing the dynamic RAM, and for this purpose, it includes an information storage area specifying means for specifying the information storage area of the dynamic RAM, and a dynamic control signal. a gate circuit that prohibits refreshing of areas other than the area by manipulating signals for the RAS input and σλ master power according to the above; and gate control means that outputs the control signal according to the specified content of the information storage area specifying means to the gate circuit; It is characterized by having.

[Industrial Field of Application] The present invention relates to a circuit that controls refresh of a dynamic RAM and limits its refresh area.

Unlike the case of static RAM, dynamic R
In AM, it is necessary to refresh this periodically in order to maintain the stored information.

[Prior Art] For this reason, dynamic RAM is refreshed, and conventionally all storage elements of dynamic RAM were refreshed.

[Problems to be Solved by the Invention] However, if all memory elements are not used for storing information, unnecessary memory elements that are not used for this purpose are also refreshed, so the refresh current supplied to the dynamic RAM is wasted. be done.

Therefore, there is a problem in that the dynamic RAM backup battery is exhausted and a large-sized backup power source is required.

The present invention has been made in view of the above-mentioned conventional problems,
The purpose is to reduce the refresh current of dynamic RAM.

[Means for Solving the Problems] In order to achieve the above object, a circuit according to the present invention is configured as shown in FIG.

The positive information practice area identifying means 10 in the figure is a dynamic RAM.
Identify the information storage area.

Furthermore, the gate circuit 11 operates the dynamic RAM and prohibits refresh of areas other than the above area.

The gate control means 12 is the information storage area specifying means 10.
The control signal corresponding to the specific content is output to the gate circuit 11.

[Operation] In the present invention, refreshing of areas other than the information storage area of the dynamic RAM is prohibited.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

FIG. 2 shows an example of a computer system to which the present invention is applied, in which dynamic RAM 21-1, 21-2...21-n is
is supplied with refresh current.

And dynamic RAM21-1.21-2...2
Gate circuits 22-1, 22-2, . A signal is given.

Figure 3 shows gate circuits 22-1, 22-2...22-n.
As can be understood from the figure, the gate circuits 22-1, 22-2---22-n are
It is composed of R gate elements 22R and 22C, and the signal is inputted to these.

Roughly speaking, a control signal for the gate elements 22R and 22C is given to these from the memory management latch 23 in FIG.

This management data is given from the CPU 24, and the
U24 generates this from the settings of the DIP switch 25.

The DIR switch 25 is operated in advance by the operator before turning on the power, and thereby the dynamic RA~I21
-1.21-2 . . . 21-n, settings are made to specify those that are not used for recording the information, or the element areas that are used for arranging the information.

Then, when the power is turned on and the operating system starts up, the settings of the DIR switch 25 are read and the management data is held in the memory management latch 23.

After that, dynamic RAM21-1, 21-2...
The signal for 21-n is connected to the gate circuit 22-1.22.
-2...22- When given to the mouth, the gate circuit 22-
1.22-2... Dynamic RAM 21-1.21-2- is masked according to the control signal by the 22- port.
-21-n.

As a result, the dynamic RAM 21 determined by the input signal
-1.21-2...2l-ns or only those element regions are refreshed.

For example, in Figure 4, the first of the signals in (A>, (B)) is masked by the control signal of 1 level as shown in (C), and the next input signal is Since the control signal is at the L level, it is directly applied to the RAS input and σ.

Therefore, refresh is not performed with the first gate input, and refresh is performed with the second input of the gate to the element region determined by that input.

As mentioned above, refresh is performed using the dynamic RAM 211°21-2...2 set by the DIR switch 25.
This is carried out only for 1-n or those element regions.

Therefore, the refresh current is not consumed by unnecessary items that are not used for storing information, and only the necessary items used for this purpose are refreshed.

Therefore, according to this embodiment, the necessary minimum refresh can be performed without causing any trouble to the RAM operation, and the current consumption can be used effectively.

As a result, consumption of the backup battery 20 can be significantly suppressed, and it is also possible to use a smaller battery.

In this embodiment, the RAM or RAM area to be refreshed is specified by manual operation of the DIR switch 25, but it is also possible to automatically perform this specification for the used area on the operating system side.

Moreover, when the polarity of each signal is reversed, the gate circuit 22-
1. NOR to 22-2...22-n.

AND and NAND gate elements are used.

[Effects of the Invention] As explained above, according to the present invention, dynamic RA
Since consumption of unnecessary current for refreshing M can be avoided, consumption of the backup battery power source can be significantly suppressed, and a compact backup power source can be used.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the invention, FIG. 2 is an explanatory diagram of the structure of the body groove of the embodiment, FIG. 3 is an explanatory diagram of the configuration of the gate circuit, and FIG. 4 is an explanatory diagram of the operation of the embodiment. 20...Backup battery, 21-1.21-2...21-n...Dynamic RAM. 22-1.22-2...22-n...gate circuit,
23...Memory management latch, 24...CPU, 25...DIP switch. Diagram for explaining the principle of the invention Fig. 1 Control signal ■ Diagram for explaining the structure of the gate circuit Fig. 4 for explaining the operation of the embodiment

Claims (1)

[Scope of Claims] Information storage area specifying means (10) for specifying an information storage area of the dynamic RAM; ,@
A gate circuit (11) that manipulates a signal for the CAS@ input to prohibit refreshing of areas other than the area, and outputs the control signal according to the specified content of the information storage area specifying means (10) to the gate circuit (11). Gate control means (12
); A refresh control circuit for a dynamic RAM, comprising: