JPH0363994A - Memory control circuit - Google Patents

Abstract

PURPOSE:To save energy consumption by prohibiting refresh to a memory, for which the preservation of information is not required, and setting the memory in a standby state. CONSTITUTION:While the information are not written into a DRAM 12 after the end of initialization, the refresh operation of the DRAM 12 is prohibited since an interruption control circuit 30 and an interruption circuit 20 interrupt access control signals RAS and CAS to the DRAM 12 even when a refresh cycle is periodically applied. Then, the DRAM 12 is maintained in the standby state. Since any information are not stored into the DRAM 12, any trouble is not generated in memory function by prohibiting the refresh operation and further, useless power is prevented form being consumed for useless refresh. Thus, the power can be widely saved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control circuit that saves power consumption of a memory that requires refreshing.

[Prior Art] DRAM (dynamic RAM) stores information by storing charge in a capacitor, so it is necessary to refresh and rewrite the stored information before the information disappears due to leakage current.

The refresh operation is inserted as a refresh cycle at regular intervals in software or hardware, and the memory access control signal R is activated at a predetermined timing.
AS, CAS and refresh addresses are provided as needed.

[Problems to be Solved by the Invention] Incidentally, in conventional systems, a refresh operation is always performed in response to a refresh cycle, regardless of whether or not the DRAM actually stores information. However, the french operation during a period when no information is stored is not only meaningless as a memory operation, but also wastes a large amount of power, which is not desirable.

The present invention has been made in view of such problems, and an object of the present invention is to provide a memory control circuit that prohibits meaningless refreshes and significantly saves memory power consumption.

[Means for Solving the Problems] In order to achieve the above object, the memory control circuit of the present invention controls the writing of data to the memory in a system having a memory that requires refreshing in order to save stored information. A write detection means detects and holds the detection result, and refreshes the memory according to the state of the signal instructing refresh and the state of the write detection means.
The configuration includes refresh control means for controlling access.

[Operation] While no information is written to the memory yet, the output signal of the write detection means is in a predetermined state (for example, inactive level)
It has become. During this period, refresh cycles are periodically inserted, and each time the refresh signal becomes a predetermined state (for example, active level), the refresh control means changes the state of the output signal of the write detection means (inactive level). It is possible to set the logic of the state (for example, active level) of the refresh signal and to prohibit refresh access to the memory, thereby preventing refresh from occurring. Thus, memory that does not require the storage of information is maintained in a standby state until written to.

In this standby state, no information is stored in the memory yet, so there is no problem of information loss even if refresh is not performed, and in fact, wasteful power consumption is reduced by eliminating meaningless refreshes.

When writing is performed in the memory, the writing detection means detects this writing and holds the detection result.

The refresh control means enables refresh access to the memory when the refresh signal becomes active under the output state (active level) of the write detection means. As a result, the information stored in the memory is saved.

Embodiment FIG. 1 shows the main configuration of a system to which a memory control circuit according to an embodiment of the present invention is applied.

The memory controller 10 is connected to a CPU (not shown) via a system bus 14 and has an address bus 16 . Data bus 18, DRAM control line 2
1.22. These memory controllers 10. The configuration and functions of the DRAM 12 are common.

This embodiment is different from the conventional one in that a cutoff circuit 20 is provided between the memory controller 10 and the DRAM 12 with respect to the DRAM access control line 22 that transmits the DRAM access control signals RAS and CAS, and this cutoff circuit 20 is controlled. The reason is that a cutoff control circuit 30 is provided for this purpose. The cutoff control circuit 30 includes a reset control circuit 32. Delay circuit 34, latch circuit 38, and control signal output circuit 3
Contains 8.

When the system is powered on, a system reset signal "1" is supplied to the reset control circuit 32 and delay circuit 34 of the cut-off control circuit 30 via the system bus 14. As a result, the latch output signal LA of the latch circuit 36 is determined to the inactive level "H".The delay circuit 34 outputs a dummy signal on the output side for a predetermined period T after inputting the reset signal R8. The cycle signal DM is set to the active level “L”.The control signal generation circuit 38
Dummy cycle signal DM is active level “L”
During this period, the output cutoff control signal CO is set to the inactive level "H". Thereby, the cutoff circuit 20 becomes OFF state (conducting state). On the other hand, at this time, the access control signals RAS and CAS are sent from the memory controller 10.
are output, and these control signals RAS and CAS are supplied to the DRAM 12 through the cutoff circuit 20.
allows initialization. Then, when the predetermined time T has elapsed, the dummy cycle signal DM becomes the inactive level "
In response, the control signal generation circuit 38 once sets the cutoff control signal C to the active level "L" and switches the cutoff circuit 20 to the ON state (cutoff state). Instead, when the previously written information is no longer needed, it is also possible to reset the latch circuit 36 via the reset control circuit 32 by accessing the control port by software.

After completing the initialization as described above, for a while < DR
Assume that no write is performed to AMl 2. During this time as well, refresh cycles are inserted by the CPU at regular intervals. When a refresh cycle is started, a refresh signal REF instructing refresh is sent from the CPU via the system bus 14. This refresh signal REF is supplied to the memory controller 1o and also to the control signal generation circuit 38 of the cutoff control circuit 3o. The memory controller 10 outputs DRAM access control signals RAS and CAS in response to the refresh signal REF.

On the other hand, the control signal generation circuit 38 generates a refresh signal RE
Based on the state of F (active level "L") and the state of latch output signal LA (inactive level "H"), the cutoff control signal 5 is set to active level "L". As a result, the cutoff circuit 20 is cut off during the refresh cycle, and the DRAM access control signal R
AS and CAS are not input to DRAM12. As a result, despite the refresh cycle, the DRAM l
2, no refresh is performed. The refresh cycle ends and the refresh signal REF becomes inactive.
When the level becomes "H", the control signal generating circuit 30 returns 1 to the inactive level "H" with the cutoff control signal and switches the cutoff circuit 2o to the OFF state.

In this way, while no information is written to the DRAM12 after initialization is completed, even if a refresh cycle is given periodically, the cutoff control circuit 30 and the cutoff circuit 20
is the access control signal RAS, CA for DRAM12
By cutting off S, the refresh operation of DRAM12 is inhibited, and DRAM12 is maintained in a standby state. Since no information is stored in the DRAM 12, the prohibition of the refresh operation will not cause any trouble to the memory function. On the contrary, there is no need to waste power for pointless refresh, so power can be significantly reduced.

When information is written to the DRAM12, the memory controller 10 receives a memory address and a control signal from the CPU, sends the memory address onto the address bus 16, and sends a write control signal W1 and access control signals RAS and CAS, respectively. The active level is set to "L" at a predetermined timing. Further, data to be written is provided on the data bus 18. At this time, the refresh signal REF is in an inactive state.

Therefore, the control signal generating means 38 generates the control value No. 1 CO
is set to an inactive level "H", and the cutoff circuit 20 is made conductive. As a result, the DRAM access control signals RAS and CAS are applied to the DRAM 12 through the cutoff circuit 20, so that a write operation is performed in the DRAM 12, and data is written to the addressed address.

On the other hand, the latch circuit 36 of the cutoff control circuit 30 detects writing in response to the fall of the write control signal WE, and switches the latch output signal "I" to the active level "L". Thereafter, the circuit 38 maintains the cutoff control signal at the inactive level "H" and keeps the cutoff circuit 20 in the conductive state.Therefore, even if a periodic refresh cycle occurs, the write mode may be arbitrarily switched off. Even if the access control signals RAS and CAS from the memory controller 10 are connected to the DR, they pass through the cutoff circuit 20 in a conductive state.
A refresh or write operation is performed in DRAM12, and the stored information is safely saved.

The list in FIG. 2 is as described above, and the fresh signal R
EF, indicates the relationship between the state of the Lasochi output signal "I" and the state of the cutoff circuit 20.

FIG. 3 shows a system according to another embodiment.

While the system of the previous embodiment had one DRAM chip 12, the system of this embodiment has a plurality of DRAM chips 12A to 12N. In FIG. 3, cutoff circuits 20A to 2ON and cutoff control #30A to
3ON has substantially the same circuit configuration as the cutoff circuit 20 and cutoff control circuit 30 shown in FIG. 2, respectively. However, the third
The cut-off control units 30A to 30B in the figure have a write control signal WE.
and an access control signal RAS for each DRAM.

CAS will also be given. In a system having multiple DRAM chips, the write control signal WE is always at an active level "L" whenever any DRAM is written, and the access control signals RAS and CAS are applied only to the DRAM that is actually accessed. becomes active level "L". Therefore, each cutoff control circuit 30A to 3ON is
Write control signal WE and active control signals RAS, CAS
When the DRAMs 1 and 2 simultaneously reach the active level, it can be detected that each corresponding DRAM 12 is in the write mode.

In this way, even in a system with multiple DRAM chips, refresh access can be controlled independently for each DRAM chip, and chips that do not store information can be put on standby by prohibiting unnecessary refreshes. can be maintained and save power consumption.

[Effects of the Invention] By having the above-described configuration, the present invention provides the following effects.

Among one or more memories that need to be refreshed to save information, memory that does not need to be refreshed (for example, memory that has not yet been written or information that has been written is no longer needed) By prohibiting refreshing of the memory (memory) and keeping it in standby mode, it is possible to significantly save power consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the main parts of a system to which a memory control circuit according to an embodiment of the present invention is applied; FIG. 2 is a diagram for explaining the operation of the memory control circuit of the embodiment; FIG. 3 is a block diagram illustrating a system according to another embodiment. 10.10'...Memory controller, 12...
・DRAM (chip), 22... DRAM access control line, 26... Cutoff circuit, 30... Cutoff control circuit, 32... Reset control circuit, 36... Latch circuit, 38...Control signal generation circuit.

Claims (1)

[Scope of Claims] A system having a memory that requires refreshing in order to save stored information, comprising: write detection means for detecting writing of data to the memory and holding the detection result; and instructing refresh. A memory control circuit comprising: refresh control means for controlling refresh access to the memory according to a state of a signal and a state of the write detection means.