JPH023343B2 - - Google Patents

Info

Publication number
JPH023343B2
JPH023343B2 JP57002573A JP257382A JPH023343B2 JP H023343 B2 JPH023343 B2 JP H023343B2 JP 57002573 A JP57002573 A JP 57002573A JP 257382 A JP257382 A JP 257382A JP H023343 B2 JPH023343 B2 JP H023343B2
Authority
JP
Japan
Prior art keywords
character
out shift
shift memory
register
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57002573A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58120346A (ja
Inventor
Masaki Tsucha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57002573A priority Critical patent/JPS58120346A/ja
Publication of JPS58120346A publication Critical patent/JPS58120346A/ja
Publication of JPH023343B2 publication Critical patent/JPH023343B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
JP57002573A 1982-01-11 1982-01-11 回線アダプタ Granted JPS58120346A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57002573A JPS58120346A (ja) 1982-01-11 1982-01-11 回線アダプタ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57002573A JPS58120346A (ja) 1982-01-11 1982-01-11 回線アダプタ

Publications (2)

Publication Number Publication Date
JPS58120346A JPS58120346A (ja) 1983-07-18
JPH023343B2 true JPH023343B2 (de) 1990-01-23

Family

ID=11533109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57002573A Granted JPS58120346A (ja) 1982-01-11 1982-01-11 回線アダプタ

Country Status (1)

Country Link
JP (1) JPS58120346A (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105923B2 (ja) * 1986-08-08 1994-12-21 日本電気株式会社 通信制御装置
JPH06105922B2 (ja) * 1986-08-08 1994-12-21 日本電気株式会社 通信制御装置

Also Published As

Publication number Publication date
JPS58120346A (ja) 1983-07-18

Similar Documents

Publication Publication Date Title
US5019966A (en) Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data
US4494190A (en) FIFO buffer to cache memory
US4864495A (en) Apparatus for controlling vacant areas in buffer memory in a pocket transmission system
GB2213294A (en) Data processor
US4145755A (en) Information transferring apparatus
EP0067302B1 (de) Einrichtung zur Aktualisierung einer Anzeigeeinrichtung in einem Datenübertragungssystem
US20060047754A1 (en) Mailbox interface between processors
US5228129A (en) Synchronous communication interface for reducing the effect of data processor latency
AU596459B2 (en) Data transfer system having transfer discrimination circuit
JPH023343B2 (de)
JPS634379B2 (de)
JPS6359042A (ja) 通信インタ−フエイス装置
EP0532431A1 (de) Multiplexierungsverfahren und -anordnung
EP0441533A2 (de) Datensortier- und -speichergerät
US5208808A (en) Method of assigning slots in a ucol-type star network and electronic device for carrying out such method
KR100335389B1 (ko) 비동기 전송모드 시스템의 셀 데이터 처리 장치 및 방법
JPS5819063A (ja) 回線アダプタ
US5896381A (en) Instantaneous switching unit and switching method for delay/priority control buffer
EP0285335B1 (de) Datenübertragungssystem und - verfahren
RU97119654A (ru) Способ и устройство для уменьшения времени ожидания на интерфейсе посредством наложения передаваемых пакетов
JPS58120347A (ja) 回線アダプタ
JPH01212994A (ja) 通信制御装置
JPH0235500B2 (de)
KR100243322B1 (ko) 실시간 처리장치용 데이터 처리방법
JPS6129242A (ja) 通信制御装置