JPH0232550A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0232550A
JPH0232550A JP18401688A JP18401688A JPH0232550A JP H0232550 A JPH0232550 A JP H0232550A JP 18401688 A JP18401688 A JP 18401688A JP 18401688 A JP18401688 A JP 18401688A JP H0232550 A JPH0232550 A JP H0232550A
Authority
JP
Japan
Prior art keywords
layer
diffusion
epitaxial growth
type
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18401688A
Other languages
Japanese (ja)
Inventor
Shinji Minami
眞嗣 南
Yukio Shima
島 幸男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18401688A priority Critical patent/JPH0232550A/en
Publication of JPH0232550A publication Critical patent/JPH0232550A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve integration by forming an oxide film on a foundation before forming an epitaxial growth layer and by forming a polysilicon layer on the oxide film during epitaxial growth. CONSTITUTION:A buried layer 2 is formed by diffusing n-type impurity at a specified area on a P-type Si substrate 1 and, at the same time, P<+> diffusion layer 4a is formed by diffusing P-type impurity of high concentration on a periphery of the layer 2 to enclose the layer 2. Then an n-type epitaxial growth layer 3 is formed on a part of the layer 2 and all over the substrate 1 which includes the layer 4a. Of the layer 3, poly-Si layers 4b, 6b are made to grow respectively on the oxide film 7. P-type impurity is diffused from the upper part of the layer 4b, and impurity if diffused from the layer 4a at the same time. A P-type dispersion and diffusion region 4 is thereby formed by simultaneous diffusion from both the upper and lower sides of the layer 3. Since an impurity diffusion coefficient against poly-Si is much larger than that against single crystal Si, diffusion to a rock crystal Si layer, that is, transverse diffusion is controlled, thus reducing a width of the region 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の製造方法、特に分離拡散領域
やコレクタウオール領域などを持つ半導体装置の製造方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having an isolation diffusion region, a collector all region, and the like.

(従来の技術〕 第2図は従来の製造方法によって得られたバイポーラ集
積回路の一部を示す断面図である。第2図において、p
型シリコン基板1上の全面にわたって、n型エピタキシ
ャル成長11f3が形成されている。p型シリコン基板
1とn型エピタキシャル成長層3との界面の所定部分に
はn型の埋込層2が形成されるとともに、この埋込層2
を取り囲むようにn型エピタキシャル成長層3内にp型
の分離拡散領域4が形成されている。この分離拡散領域
4は、n型エピタキシ1フル成良層3の上面と下面から
同時にp型の不純物を拡散させることにより形成された
ものである。この分離拡散領域4によって、n型エピタ
キシャル成長層3の所望領域が他の部分から島状にpn
接合分離される。分離されたn型エピタキシャル成長層
3の上面には選択的にn型不純物を拡散することにより
ベース領域5が形成されるとともに、n型不純物を拡散
することによりコレクタウオール領域6が形成されてい
る。
(Prior Art) Fig. 2 is a sectional view showing a part of a bipolar integrated circuit obtained by a conventional manufacturing method.
An n-type epitaxial growth layer 11f3 is formed over the entire surface of the type silicon substrate 1. An n-type buried layer 2 is formed at a predetermined portion of the interface between the p-type silicon substrate 1 and the n-type epitaxial growth layer 3, and this buried layer 2
A p-type isolation diffusion region 4 is formed in the n-type epitaxial growth layer 3 so as to surround it. This isolation diffusion region 4 is formed by simultaneously diffusing p-type impurities from the upper and lower surfaces of the n-type epitaxy 1 fully grown layer 3. By this isolation diffusion region 4, a desired region of the n-type epitaxial growth layer 3 is isolated from other parts in an island-like pn
The junction is separated. On the upper surface of the separated n-type epitaxial growth layer 3, a base region 5 is formed by selectively diffusing n-type impurities, and a collector all region 6 is also formed by diffusing n-type impurities.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記した従来の製造方法では、分離拡散領域4やコレク
タウオール領域6の形成プロセスにおいて、不純物がn
型エピタキシャル成長層3の縦方向(深さ方向)だけで
なく横方向にも同程度に拡散するため、出来Fがる分離
拡散領域4やコレクタウオール領域6の幅寸法がどうし
ても大きくなってしまう。そのため、集積回路の集積度
が低くなって、1枚の半導体基板から得ることのできる
チップ数も制限されるという問題点があった。
In the conventional manufacturing method described above, in the process of forming the isolation diffusion region 4 and the collector all region 6, impurities are
Since the diffusion occurs not only in the vertical direction (depth direction) of the type epitaxial growth layer 3 but also in the horizontal direction, the width of the resulting isolation diffusion region 4 and collector all region 6 inevitably becomes large. Therefore, there is a problem in that the degree of integration of the integrated circuit becomes low, and the number of chips that can be obtained from one semiconductor substrate is also limited.

この発明は、このような問題点を解決するためになされ
たもので、分離拡散領域やコレクタウオール領域の幅寸
法を小さくすることのできる半導体装置の製造方法を提
供することを目的とする。
The present invention has been made to solve these problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the width of the isolation diffusion region and the collector all region.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、エピタキシャ
ル成長層に選択的に不純物を拡散させて前記エピタキシ
ャル成長層を貫通する拡散領域を形成する半導体装置の
製造方法であって、エピタキシャル成長層の形成前の下
地上の前記拡散領域に相当する部分に選択的に酸化膜を
形成したあとでエピタキシャル成長層を形成することに
より、前記拡散領域内にポリシリコン層を設けたもので
ある。
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which impurities are selectively diffused into an epitaxial growth layer to form a diffusion region penetrating the epitaxial growth layer, the method comprising: forming a diffusion region that penetrates the epitaxial growth layer; A polysilicon layer is provided in the diffusion region by selectively forming an oxide film in a portion corresponding to the diffusion region and then forming an epitaxial growth layer.

〔作用〕[Effect]

この発明においては、エピタキシャル成長時に酸化膜上
にはポリシリコン層が形成されるので、このあとエピタ
キシャル成長層に不純物を拡散させて、分離拡散領域や
コレクタウオール領域などの、エピタキシャル成長層を
貫通する拡散領域を形成する際に、ポリシリコン層内へ
の不純物の拡散は単結晶シリコン層内への拡散よりも早
く行われ、したがって前記拡散領域の横方向への拡がり
が小さく抑えられる。
In this invention, since a polysilicon layer is formed on the oxide film during epitaxial growth, impurities are then diffused into the epitaxial growth layer to form diffusion regions that penetrate the epitaxial growth layer, such as isolation diffusion regions and collector all regions. During formation, the impurity diffuses into the polysilicon layer faster than into the single crystal silicon layer, so that the lateral expansion of the diffusion region is kept small.

〔実施例〕〔Example〕

第1図(A)〜(D)はこの発明による半導体装置の製
造方法の一実施例の工程を示す断面図であり、ここでは
バイポーラ集積回路の製造工程が示されている。
FIGS. 1A to 1D are cross-sectional views showing steps in an embodiment of the method for manufacturing a semiconductor device according to the present invention, in which the steps for manufacturing a bipolar integrated circuit are shown.

この製造方法では、先ず第1図(A)に示す工程におい
て、n型シリコン基板1上の所定部分にn型の不純物を
拡散させて埋込層2が形成されるとともに、この埋込層
2を取り囲むようにその周囲に高濃度のn型不純物を拡
散させてp゛拡敢層4aが形成される。
In this manufacturing method, first, in the step shown in FIG. A p-expansion layer 4a is formed by diffusing a high concentration of n-type impurity around it so as to surround it.

ついで、第1図(B)に示すように、埋込M2の上面の
一部およびp+拡散層4aの上面のほぼ全面に酸化膜7
が形成される。
Next, as shown in FIG. 1B, an oxide film 7 is formed on a part of the upper surface of the buried M2 and almost the entire upper surface of the p+ diffusion layer 4a.
is formed.

このあと、上記の埋込層2およびp+拡散層4aを含む
n型シリコン基板1上の全面に、第1図(C)に示すよ
うに、n型エピタキシャル成長層3が形成される。この
とき、形成されるn型エピタキシャル成長層3のうち、
上記の酸化膜7上にはポリシリコン層4b、6bがそれ
ぞれ成長する。
Thereafter, as shown in FIG. 1C, an n-type epitaxial growth layer 3 is formed over the entire surface of the n-type silicon substrate 1, including the buried layer 2 and the p+ diffusion layer 4a. At this time, of the n-type epitaxial growth layer 3 formed,
Polysilicon layers 4b and 6b are grown on the oxide film 7, respectively.

次に、ポリシリコン層4bの上方からn型不純物を拡散
させる。このとき同時にp+拡散層4aからも不純物が
拡散することにより、n型1ビタキシャル成長層3の上
面と下面の両方からの同時拡散によってn型の分離拡散
領域4が形成される。
Next, n-type impurities are diffused from above polysilicon layer 4b. At this time, impurities are also diffused from the p+ diffusion layer 4a at the same time, so that the n-type isolation diffusion region 4 is formed by simultaneous diffusion from both the upper surface and the lower surface of the n-type 1 bitaxial growth layer 3.

このとき、F T、 1.にamins et、al 
J、^p1. phys、 43゜83(1972)J
にも開示されているように、ポリシリコンに対する不純
物の拡散係数は単結晶シリコンに対する拡散係数よりも
ほぼ100倍大ぎいことから、ポリシリコンl1db内
へはまわりの単結晶シリコン層よりも早くn型不純物が
拡散し、したがって単結晶シリコン層への拡散つまり横
方向への拡散は小さく抑えられ、形成される分離拡散領
域4の幅寸法は小さくなる。また、このときの拡散処理
は従来に比べて低温でかつ高速に行うことができる。な
お、この場合の分離拡散領域4のp“拡散層4aとの接
続は、p+拡散層4aが酸化膜7で覆われていない両端
部8を介して行われる。
At this time, F T, 1. amins et al.
J, ^p1. phys, 43°83 (1972) J
As disclosed in the literature, the diffusion coefficient of impurities to polysilicon is approximately 100 times larger than that to single-crystal silicon, so that n-type impurities enter polysilicon l1db faster than the surrounding single-crystal silicon layer. The impurity is diffused, and therefore the diffusion into the single crystal silicon layer, that is, the diffusion in the lateral direction, is suppressed to a small level, and the width dimension of the formed isolation diffusion region 4 is reduced. Further, the diffusion treatment at this time can be performed at a lower temperature and at a higher speed than in the past. In this case, the isolation diffusion region 4 is connected to the p" diffusion layer 4a through both ends 8 of the p+ diffusion layer 4a which are not covered with the oxide film 7.

このようにして形成された分離拡r11領域4によって
、n型エピタキシャル成長層3の所望領域が他の部分か
ら島状にpn接合分離される。
By the isolation expansion r11 region 4 thus formed, a desired region of the n-type epitaxial growth layer 3 is isolated from other parts by a pn junction in the form of an island.

分離されたn型エピタキシャル成長層3の上面の一部に
はn型不純物が拡散され、これによって第1図(D)に
示すようにベース領145が形成される。また、ポリシ
リコンIIU6bの上方から高濃度のn型不純物を拡散
させることによってコレクタウオール領域6が形成され
る。このコレクタウオール領域6においても前述した分
離拡散領域4の場合と同様に、n型不純物のポリシリコ
ン層6bへの拡散がまわりの単結晶シリコン層への拡散
よりも早く、形成されるコレクタウオール領域6の幅寸
法は小さく抑えられる。コレクタウオール領域6と埋込
層2との接合は酸化膜7の両端部9を介して行われる。
An n-type impurity is diffused into a part of the upper surface of the separated n-type epitaxial growth layer 3, thereby forming a base region 145 as shown in FIG. 1(D). In addition, collector all region 6 is formed by diffusing high concentration n-type impurities from above polysilicon IIU 6b. In this collector all region 6, as in the case of the isolation diffusion region 4 described above, the n-type impurity diffuses into the polysilicon layer 6b faster than into the surrounding single crystal silicon layer, and the collector all region is formed. 6 can be kept small. Collector all region 6 and buried layer 2 are bonded via both ends 9 of oxide film 7 .

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、エピタキシャル成長
層形成前の下地上に酸化膜を形成し、エピタキシャル成
長時にこの酸化膜上にポリシリコン層を成長させている
ので、このポリシリコン層を含むエピタキシャル成長層
の部分に不純物を拡散させて、分離拡散領域やコレクタ
ウオール領域などの、エピタキシャル成長層を貫通する
拡散領域を形成する際、該拡散領域の幅寸法が小さくな
り、それだけ得られる半導体装置の集積度を高くするこ
とができる。
As described above, according to the present invention, an oxide film is formed on the base before forming an epitaxial growth layer, and a polysilicon layer is grown on this oxide film during epitaxial growth, so that an epitaxial growth layer including this polysilicon layer is formed. When an impurity is diffused into a region to form a diffusion region penetrating the epitaxial growth layer, such as an isolation diffusion region or a collector all region, the width dimension of the diffusion region becomes smaller, which increases the degree of integration of the semiconductor device obtained. It can be made higher.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)〜(D)はこの発明による半導体装置の製
造方法の一実施例の工程を示す断面図、第2図は従来の
製造方法によって得られた半導体装置を示す断面図であ
る。 図において、1はp型シリコン基板、3はn型エピタキ
シャル成長層、4は分離拡散領域、6はコレクタウオー
ル領域、4b、6bはポリシリコン層、7は酸化膜であ
る。 なお、各図中同一符号は同一または相当部分をボす。
FIGS. 1A to 1D are cross-sectional views showing the steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view showing a semiconductor device obtained by a conventional manufacturing method. . In the figure, 1 is a p-type silicon substrate, 3 is an n-type epitaxial growth layer, 4 is an isolation diffusion region, 6 is a collector all region, 4b and 6b are polysilicon layers, and 7 is an oxide film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] (1)エピタキシャル成長層に選択的に不純物を拡散さ
せて前記エピタキシャル成長層を貫通する拡散領域を形
成する半導体装置の製造方法において、 前記エピタキシャル成長層の形成前の下地上の前記拡散
領域に相当する部分に選択的に酸化膜を形成したあとで
前記エピタキシャル成長層を形成することにより、前記
拡散領域内にポリシリコン層を設けたことを特徴とする
半導体装置の製造方法。
(1) In a method for manufacturing a semiconductor device in which impurities are selectively diffused into an epitaxial growth layer to form a diffusion region penetrating the epitaxial growth layer, a portion corresponding to the diffusion region on a base before formation of the epitaxial growth layer is A method of manufacturing a semiconductor device, characterized in that a polysilicon layer is provided in the diffusion region by selectively forming an oxide film and then forming the epitaxial growth layer.
JP18401688A 1988-07-22 1988-07-22 Manufacture of semiconductor device Pending JPH0232550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18401688A JPH0232550A (en) 1988-07-22 1988-07-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18401688A JPH0232550A (en) 1988-07-22 1988-07-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0232550A true JPH0232550A (en) 1990-02-02

Family

ID=16145864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18401688A Pending JPH0232550A (en) 1988-07-22 1988-07-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0232550A (en)

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