JPH023231A - Thin film transistor and manufacture thereof - Google Patents
Thin film transistor and manufacture thereofInfo
- Publication number
- JPH023231A JPH023231A JP63150094A JP15009488A JPH023231A JP H023231 A JPH023231 A JP H023231A JP 63150094 A JP63150094 A JP 63150094A JP 15009488 A JP15009488 A JP 15009488A JP H023231 A JPH023231 A JP H023231A
- Authority
- JP
- Japan
- Prior art keywords
- film
- protective film
- silicon
- layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 73
- 230000001681 protective effect Effects 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 238000010276 construction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 14
- 239000002356 single layer Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241001239379 Calophysus macropterus Species 0.000 description 1
- 229910016024 MoTa Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
この発明は、薄膜トランジスタ及びその製造方法に関す
る〇
（従来の技術）
エレクトロルミネッセンス、発光ダイオード。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a thin film transistor and a method for manufacturing the same.〇 (Prior Art) Electroluminescence, light emitting diode.
プラズマ、螢光表示管、液晶等の表示デバイスは表示部
の薄型化が可能であり計測機器、事務機器やコンピュー
タ等の端末表示装置あるいは特殊な表示装置への用途と
して要求が高まっている。これらの中で薄膜トランジス
タのスイッチング素子マトリックスアレイを用いたエレ
クトロルミネッセンスや液晶表示装置は、低消費電力化
や低コスト化が可能であるために表示デバイスとして注
目されている。Display devices such as plasma, fluorescent display tubes, and liquid crystal display devices can have thinner display sections, and are increasingly in demand for use in terminal display devices such as measuring instruments, office equipment, and computers, or special display devices. Among these, electroluminescent and liquid crystal display devices using switching element matrix arrays of thin film transistors are attracting attention as display devices because they can reduce power consumption and cost.
このようなスイッチングトランジスタの材料としては結
晶、多結晶、アモルファス状態のＳｉ＋ＣｄＳｅ ＃
Ｔｅ ＊ ＣｄＳ等が用いられる。この中でも多結晶半
導体やアモルファス半導体の薄膜技術は、低温プロセス
が可能なためｌこガラス基板等の比較的低温で取扱うこ
との必要な基板上にもスイッチングトランジスタのアク
ティブマトリ、クス素子を形成することができ、低価格
で大面積の表示装置を実用段階にした。Materials for such switching transistors include Si+CdSe in crystalline, polycrystalline, and amorphous states.
Te*CdS or the like is used. Among these, thin film technology for polycrystalline semiconductors and amorphous semiconductors allows for low-temperature processes, making it possible to form active matrices of switching transistors and switching elements even on substrates that need to be handled at relatively low temperatures, such as glass substrates. This brought a low-cost, large-area display device to the practical stage.
第３図は、従来の薄膜トランジスタ（ＴＦＴ）の断面図
である。FIG. 3 is a cross-sectional view of a conventional thin film transistor (TFT).
先ず、例えばガラス板のような透光性絶縁基板＋１）上
にＭｏやＣｒのような合端パターンでゲート電極（２１
を形成し、ゲート電極（２）上をＳｉＮｘ等のゲート絶
縁ｇ（３１で覆う。First, a gate electrode (21
is formed, and the gate electrode (2) is covered with a gate insulator g (31) such as SiNx.
次にゲート１１ｔ極（１）上ｌこ位置するところに、非
晶質シリコン（ａ−８目の半導体薄膜（４）を形成し、
この半導体薄膜（４）上にＳｉＮｘあるいはＳｉＯｘの
単層からなる保書膜（５）を形成する。次いで、半導体
薄膜（４）とソース電極（６）、ドレイン電極（７）と
のオーミック接触を得るためのｎ＋ａ−８ｔ層（８）を
形成し、そθ）上ｆこソース１！極（６）、ドレイン′
這極（刀を形成する〇又、ドレイン電極（７）はＩＴＯ
等の透明導電膜からなる画素電極（９）に接続して、表
示装置用駆動回路基鈑を構成している。Next, an amorphous silicon (a-8th semiconductor thin film (4) is formed at a position above the gate 11t pole (1),
On this semiconductor thin film (4), an insulating film (5) consisting of a single layer of SiNx or SiOx is formed. Next, an n+a-8t layer (8) is formed to obtain ohmic contact between the semiconductor thin film (4), the source electrode (6), and the drain electrode (7), and then the f-source 1! Pole (6), drain′
The drain electrode (7) that forms the sword is made of ITO.
It is connected to a pixel electrode (9) made of a transparent conductive film such as, and constitutes a drive circuit board for a display device.
（発明が解決しようとする課題）
このような従来構造のＴＦ’Ｔでは、保１引こ５１０Ｘ
単層を用いた場合ｌこは、ａ−８１の半導体薄膜を耐光
性向上のために薄＜ （１００ＯＡ 以下〕すると、保
護膜の影響が現われるようになり、ＴＰＴのしきい値電
圧が高くなるという問題があった。また、保護膜ｌこＳ
ｉＮｘ単層を用いた場合ｆこは、ａ−８ｉＭを薄くし
てもしきい値′１圧が高くなることはないがｓ ＳｉＮ
ｘ膜にクラックや膜はがれが発生しゃ丁いという問題が
あった。(Problem to be solved by the invention) In a TF'T with such a conventional structure, the
When using a single layer, if the A-81 semiconductor thin film is made thinner (less than 100 OA) to improve light resistance, the effect of the protective film will appear and the threshold voltage of TPT will increase. There was also the problem that the protective film
When using an iNx single layer, the threshold '1 pressure does not increase even if the a-8iM is made thinner, but sSiN
There was a problem that cracks and film peeling occurred in the x film.
この発明は、上記事情を考慮してなされたもので、その
目的とするところはＴＰＴのしきい値電圧を制御でき、
保護膜のクラックや膜はがれを抑えることのできる薄膜
トランジスタ及びその製造方法を提供することにある。This invention was made in consideration of the above circumstances, and its purpose is to be able to control the threshold voltage of TPT,
An object of the present invention is to provide a thin film transistor that can suppress cracks and peeling of a protective film, and a method for manufacturing the same.
（課題を解決するための手段）
本発明は、薄膜トランジスタの保護膜をシリコン窒化物
からなる層とシリコン酸化物からなる層の２層構造とし
、半導体薄膜と接する層をシリコン窒化物からなる層と
する。(Means for Solving the Problems) The present invention provides a protective film of a thin film transistor with a two-layer structure of a layer made of silicon nitride and a layer made of silicon oxide, and a layer in contact with the semiconductor thin film is a layer made of silicon nitride. do.
（作用）
本発明の如く、保護膜をシリコン窒化物からなる層とシ
リコン酸化物からなる層の２層構造とすることにより、
保護膜に起因するＴＰＴのしきい値電圧の変化を抑える
ことができる。(Function) As in the present invention, by forming the protective film into a two-layer structure consisting of a layer made of silicon nitride and a layer made of silicon oxide,
Changes in the threshold voltage of TPT caused by the protective film can be suppressed.
（実施例〉 以下、本発明の絆細を図示の実施例によって説明する。(Example> Hereinafter, the bond details of the present invention will be explained with reference to illustrated embodiments.
第１図は、本発明の一実施例に係わる薄膜トランジスタ
の断面図、第２図（ａＪ〜（りはその製造工程を示す断
面図である。第１図および第２図を併用１て説明すると
、先ず、例えばガラス基板からなる透明性絶縁基板（２
０）上にスパッタリング法や電子ビーム蒸着法により厚
さ約２００ＯＡのＭｏあるいはＭｏＴａ合金等の金Ｉｊ
４膜を形成し、ホトレジストパターンを形成して第２図
（ａ）に示すようなゲート電極（２１）を作る。FIG. 1 is a sectional view of a thin film transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process thereof. , First, a transparent insulating substrate (2
0) Gold Ij such as Mo or MoTa alloy with a thickness of about 200 OA is deposited on top by sputtering or electron beam evaporation.
A photoresist pattern is formed to form a gate electrode (21) as shown in FIG. 2(a).
次Ｉζ例えばプラズマ已の法により％第１のゲート絶縁
膜であるシリコン酸化膜（２２）を約３００ＯＡ。Next, a silicon oxide film (22), which is the first gate insulating film, is deposited to a thickness of about 300 OA by, for example, a plasma method.
第２のゲート絶縁膜であるシリコン窒化Ｎ （Ｚ３）を
約５０ＯＡ、活性層であるアモルファスシリコン膜（２
４）を約５０ＯＡ 、第１の保護膜であるシリコン窒化
膜（２５）を約５０ＯＡ 、第２の保護膜であるシリコ
ン酸化Ｍ （２６）を約２００ＯＡ、順次大気に触れる
ことなく連続的に堆積する（第２図Ｃｂ） ）。The second gate insulating film, silicon nitride N (Z3), is about 50 OA, and the active layer is an amorphous silicon film (2
4) at approximately 50 OA, the first protective film, silicon nitride film (25), at approximately 50 OA, and the second protective film, silicon oxide M (26), at approximately 200 OA. (Figure 2Cb)).
次Ｊこ、ホトリソグラフィー技術ｌこより、ゲート電極
（２１）上ｌこ位置するように、第２のゲート絶縁膜（
２３１、活性層（２４）、第１の保護膜（２５）、第２
の保護膜（２６）からなるパターンを形成する（第２図
（ｃｌ ） 。Next, using photolithography technology, a second gate insulating film (21) is deposited on the gate electrode (21).
231, active layer (24), first protective film (25), second
A pattern consisting of a protective film (26) is formed (FIG. 2 (cl)).
次に、厚さおよそ２０００ＡのＩＴＯ（Ｉｎｄｉｕｍ
Ｔｉｎ０ｘｉｄｅ ）等の透明４電膜をスパッタリング
法や電子ビーム蒸着法ｆこより堆積させ、ホトリフグラ
フィー技術により、第２図（ｄ）に示すような画素電極
（２７）を作る。Next, ITO (Indium) with a thickness of approximately 2000A
A transparent 4-electrode film such as TinOxide is deposited by sputtering or electron beam evaporation, and a pixel electrode (27) as shown in FIG. 2(d) is formed by photolithography.
次に、第２図（ｅＪに示すようｌζ第１の保護膜（２５
八第２の保護膜（２６）からなるパターンを形成する。Next, as shown in FIG. 2 (eJ), the lζ first protective film (25
8. A pattern consisting of the second protective film (26) is formed.
次ｌこ、例えばプラズマＣＶＤ法を用いて、ｎ”ａ−Ｓ
ｔ膜（２８）を約５０ＯＡ形成し、さらにスパッタリン
グ法等を用いてｓ Ｍｏ膜を約５００Ａ％ＡＪ膜を約１
μｍ形成し、第２図（ｆ）に示すように、ソース電極（
２９）及び画素電極（２７）と接続するドレイン電極（
、Ｔ’を形成する。Next, for example, using plasma CVD method, n”a-S
A t film (28) of about 50 OA is formed, and an s Mo film of about 500 A% and an AJ film of about 1
As shown in FIG. 2(f), the source electrode (
29) and the drain electrode (27) connected to the pixel electrode (27).
, T'.
以上のような工程ｌζより、画素電極を伴なったＴＰＴ
基板が完成する。第２図ではｎ”ａ−８ｉ膜（２８）が
、第１のゲート絶＃膜（η）上と画素電極（２７）上ｌ
こも残っているが、第１図のようにｎ”ａ−８ｔ膜（２
８）が残っていなくともよい。Through the above process lζ, the TPT with the pixel electrode
The board is completed. In FIG. 2, an n"a-8i film (28) is formed on the first gate insulation film (η) and on the pixel electrode (27).
However, as shown in Figure 1, the n”a-8t film (2
8) may not be left.
このような構造のＴＰＴでは、しきい値電圧が約２ｖと
良好なＴＰＴ特性が得られ、保護膜のクラックや膜はが
れは全く認められなかった。In the TPT having such a structure, good TPT characteristics with a threshold voltage of about 2V were obtained, and no cracks or peeling of the protective film were observed.
また、ｉ層ａ−８ｔが５０ＯＡと薄いため、１０万／Ｘ
−の外光照射でもリーク電流を低く抑えることができ、
耐光性も強いＴＰＴ特性となった。In addition, since the i-layer a-8t is as thin as 50OA, 100,000/X
- Leakage current can be kept low even with external light irradiation,
It also has TPT characteristics with strong light resistance.
また、第１の保護膜であるシリコン窒化膜を原料ガスと
してシランとアンモニア、光源として低圧水銀ランプを
用いた光Ｑ■法ｆこより形成することにより、プラズマ
中の荷電粒子による損傷がなくなったことから、長時間
でのしきい値電圧の変動が少なくなり、信頼性の向上が
認められた。In addition, by forming the silicon nitride film, which is the first protective film, using the optical Q method using silane and ammonia as raw material gases and a low-pressure mercury lamp as a light source, damage caused by charged particles in plasma was eliminated. As a result, fluctuations in threshold voltage over a long period of time were reduced, and reliability was improved.
本発明によれば、保護膜ｌこ起因するＴＦ’ｒのしきい
値電圧の変化を抑えることができ、保護膜のクラックや
膜はがれも抑えたＴＰＴを得ることができる。According to the present invention, it is possible to suppress changes in the threshold voltage of TF'r caused by the protective film, and to obtain a TPT in which cracks and peeling of the protective film are suppressed.
第１図はこの発明の一実施例の断面図、第２図は第１図
に示す薄膜トランジスタを得るための製造方法を示す図
、第３図は従来の薄膜トランジスタの断面図である。
２０・・・透光性絶縁基板、２１・・・ゲート電極、２
２・・・酸化物からなるゲート絶縁膜（第１のゲート絶
縁Ｍ）、２３・・・窒化物からなるゲートＰ！巌換（第
２のゲート絶縁膜）、２４・・・半導体薄膜からなる活
性層、２５・・・窒化物からなる保護Ｍ（第１の保護膜
）、２６・・・酸化物からなる保護膜（第２の保護膜）
、２７・・・画素電極、２８・・・オーミックコンタク
ト層（ｎ”ａ−８ｔ膜）、２９−・・ソース１！Ｌ極、
３０・・・ドレイン電極。FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a diagram showing a manufacturing method for obtaining the thin film transistor shown in FIG. 1, and FIG. 3 is a sectional view of a conventional thin film transistor. 20... Transparent insulating substrate, 21... Gate electrode, 2
2... Gate insulating film made of oxide (first gate insulating M), 23... Gate P made of nitride! Iwakae (second gate insulating film), 24... active layer made of semiconductor thin film, 25... protection M made of nitride (first protective film), 26... protective film made of oxide (Second protective film)
, 27... Pixel electrode, 28... Ohmic contact layer (n''a-8t film), 29-... Source 1!L pole,
30...Drain electrode.
Claims (2)
のゲート電極上にゲート絶縁膜を介して形成された半導
体膜と、この半導体膜上に形成されたソースおよびドレ
イン電極と、このソース、ドレイン電極間の半導体膜上
に形成された保護膜を具備した薄膜トランジスタにおい
て、前記保護膜がシリコン窒化膜とシリコン酸化膜の積
層膜で、シリコン窒化膜が半導体膜に接する側にあるこ
とを特徴とする薄膜トランジスタ。(1) A gate electrode formed on a light-transmitting insulating substrate, a semiconductor film formed on this gate electrode via a gate insulating film, a source and drain electrode formed on this semiconductor film, and In a thin film transistor including a protective film formed on a semiconductor film between source and drain electrodes, the protective film is a laminated film of a silicon nitride film and a silicon oxide film, and the silicon nitride film is on the side in contact with the semiconductor film. Features of thin film transistors.
ＣＶＤ法により形成することを特徴とする薄膜トランジ
スタの製造方法。(2) A method for manufacturing a thin film transistor, characterized in that the silicon nitride film as the protective film according to claim 1 is formed by a photo-CVD method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63150094A JPH023231A (en) | 1988-06-20 | 1988-06-20 | Thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63150094A JPH023231A (en) | 1988-06-20 | 1988-06-20 | Thin film transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH023231A true JPH023231A (en) | 1990-01-08 |
Family
ID=15489381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63150094A Pending JPH023231A (en) | 1988-06-20 | 1988-06-20 | Thin film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH023231A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02155275A (en) * | 1988-12-07 | 1990-06-14 | Fuji Xerox Co Ltd | Thin film transistor |
| JPH03148136A (en) * | 1989-11-02 | 1991-06-24 | Matsushita Electric Ind Co Ltd | Semiconductor element and manufacture thereof |
| CN105633170A (en) * | 2016-02-23 | 2016-06-01 | 广州新视界光电科技有限公司 | Metal oxide thin film transistor and preparation method therefor, array substrate and display apparatus |
| CN107749422A (en) * | 2017-09-21 | 2018-03-02 | 信利（惠州）智能显示有限公司 | Oxide semiconductor thin-film transistor |
-
1988
- 1988-06-20 JP JP63150094A patent/JPH023231A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02155275A (en) * | 1988-12-07 | 1990-06-14 | Fuji Xerox Co Ltd | Thin film transistor |
| JPH03148136A (en) * | 1989-11-02 | 1991-06-24 | Matsushita Electric Ind Co Ltd | Semiconductor element and manufacture thereof |
| CN105633170A (en) * | 2016-02-23 | 2016-06-01 | 广州新视界光电科技有限公司 | Metal oxide thin film transistor and preparation method therefor, array substrate and display apparatus |
| CN107749422A (en) * | 2017-09-21 | 2018-03-02 | 信利（惠州）智能显示有限公司 | Oxide semiconductor thin-film transistor |
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