JPH023222A - Manufacture of semiconductor quantum wire - Google Patents

Manufacture of semiconductor quantum wire

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Publication number
JPH023222A
JPH023222A JP15180988A JP15180988A JPH023222A JP H023222 A JPH023222 A JP H023222A JP 15180988 A JP15180988 A JP 15180988A JP 15180988 A JP15180988 A JP 15180988A JP H023222 A JPH023222 A JP H023222A
Authority
JP
Japan
Prior art keywords
growth
thickness
deposited
quantum wire
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15180988A
Other languages
Japanese (ja)
Inventor
Takashi Fukui
孝志 福井
Seigo Ando
精後 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15180988A priority Critical patent/JPH023222A/en
Publication of JPH023222A publication Critical patent/JPH023222A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To improve the performance of a device by a method wherein a trapezoidal multi-layer structure is grown at a specified temperature on a substrate, on which a selection mask is located in advance, by an organic metal vapor growth method and a one-dimensional electronic state is made by continuous growth on the side face of the multi-layer structure by modulation doping for making a quantum wire. CONSTITUTION:SiO29 is deposited on a GaAs substrate by a sputtering method or a CVD method and a long stripe opening is formed in the [110] direction. After a non-dope AlGaAs 7 is deposited on this substrate at the temperature of 750 deg.C of below, for example, at 650 deg.C, in the thickness of 100nm by an organic metal vapor phase growth method, GaAs 3 and AlGaAs 2 are deposited in this order in the thickness of 10nm to make a multi-layer structure. Finally, an undoped AlGaAs 8 is deposited in the thickness of 100nm. At this time, the growth layer is in the shaped of a trapezoid and there is no deposition on the side face of it. Nextly, an undoped AlGaAs 4 is deposited on the trapezoidal multi-layer structure at 800 deg.C in the thickness of 10nm to make a one- dimensional electronic state on the side face of the trapezoid.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、超高速の一次元電子トランジスタ、あるいは
量子干渉を利用した高変換効率の非線形素子等に利用さ
れる半導体一次元量子細線の製造方法に関するものであ
る。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to the production of semiconductor one-dimensional quantum wires used in ultra-high-speed one-dimensional electronic transistors or nonlinear elements with high conversion efficiency using quantum interference. It is about the method.

〔従来の技術〕[Conventional technology]

材料としてA I G a A s / G a A 
sを例にとって従来提案されている一次元量子細線の製
造を第1図に示す。これは、AfGaAs/GaAsの
多層膜の側面に変調ドープによって一次元電子状態を実
現するものである。図中点線で囲まれた多層膜/ A 
I G a A s界面の部分が一次元電子状態になる
As a material A I G a A s / G a A
FIG. 1 shows the production of a one-dimensional quantum wire that has been proposed in the past by taking s as an example. This realizes a one-dimensional electronic state by modulation doping on the side surfaces of an AfGaAs/GaAs multilayer film. Multilayer film surrounded by dotted lines in the figure/A
The part of the IGaAs interface becomes a one-dimensional electronic state.

この構造の作製方法を次に示す。先ず、分子線エピタキ
シャル成長法あるいは、有機金属気相成長法によってノ
ンドープの2のA7!GaAs 3のGaAsを順次成
長させ、多層構造を作製する。
The method for manufacturing this structure is shown below. First, non-doped A7! GaAs 3 and GaAs are sequentially grown to produce a multilayer structure.

次に、多層膜ウェハ上のエツチングマスクを〔110)
方向に配し、(第2図+al)、化学エツチングあるい
はプラズマエツチングによって段差を作る(第2図(b
l)、再び分子線エピタキシャル成長法か有機金属気相
成長法で4のノンドープA/GaAsをIOnmの長さ
でエツチング側面に成長させ、引き続き5のSi ドー
プ(〜10 l1lc m−’)A7!GaAsを11
00nの厚さで成長させて、側面に一次元状態を実現す
る(第2図(C))。
Next, the etching mask on the multilayer film wafer [110]
(Fig. 2 + al), and create a step by chemical etching or plasma etching (Fig. 2 (b)
l), undoped A/GaAs of 4 is grown on the etched side surface with a length of IONm again by molecular beam epitaxial growth or metal-organic vapor phase epitaxy, followed by Si-doped (~10 l1lc m-') of 5 A7! 11 GaAs
It is grown to a thickness of 00n to achieve a one-dimensional state on the side surface (FIG. 2(C)).

化学エツチングにより形成された側面(第1図の斜線部
分)は、炭素、酸素、シリコン等で汚染されており、こ
れらの汚染物は電子の散乱要因や再結合中心となり、さ
らにトラップとして働くためキャリア濃度が低下すると
いう問題がある。さらに化学エツチングでは物質の種類
によってエツチング速度が異なるので、エツチングの側
面は凹凸になり、やはり電子の散乱要因となる。一方、
プラズマエツチングによって加工する場合、加工面(第
1図の斜線部分)にダメージ層あるいは変質層ができる
。それらの層も電子の散乱要因や再結合中心となり、こ
の量子細線を使ったデバイスの性能を著しく悪くすると
いう問題がある。第1図の構造を持つ量子細線は加工側
面を使うものであるから、界面の汚染や加工ダメージは
致命的な欠陥となる。
The side surface formed by chemical etching (the shaded area in Figure 1) is contaminated with carbon, oxygen, silicon, etc., and these contaminants act as scattering factors and recombination centers for electrons, and further act as traps to trap carriers. There is a problem that the concentration decreases. Furthermore, in chemical etching, the etching speed differs depending on the type of material, so the etched side surfaces become uneven, which also causes scattering of electrons. on the other hand,
When processing by plasma etching, a damaged layer or altered layer is formed on the processed surface (the shaded area in FIG. 1). These layers also act as scattering factors and recombination centers for electrons, significantly degrading the performance of devices using quantum wires. Since the quantum wire with the structure shown in Figure 1 uses the processing side, contamination of the interface and processing damage are fatal defects.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上記で説明した量子細線の作製方法には、次の
ような問題点がある。
However, the quantum wire manufacturing method described above has the following problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の量子細線の製造方法は、エツチング側面の凹凸
や汚染あるいは加工によるダメージを克服するために考
えられたものであり、予め選択マスクを配置した基板状
に、有機金属気相成長法を使って台形状の多層構造を成
長させ、引き続(成長によってその台形状の多層構造の
側面に変調ドープによって一次元電子状態を実現し、量
子細線を作ることを主要な特徴とした製造方法である。
The method for producing quantum wires of the present invention was devised to overcome damage caused by unevenness, contamination, or processing on the etching side surface, and uses metal organic vapor phase epitaxy on a substrate on which a selective mask is placed in advance. This is a manufacturing method whose main feature is to grow a trapezoidal multilayer structure, and then (through growth, modulation doping is applied to the sides of the trapezoidal multilayer structure to realize a one-dimensional electronic state, creating a quantum wire. .

〔作 用〕[For production]

本発明の製造方法は、成長温度によって選択成長の成長
様式が変わることを巧みに利用したものであり、すべて
成長工程のみで量子細線を形成するものであるから、加
工ダメージや汚染から完全に逃れることは勿論のこと横
方向の界面の急峻性も単原子オーダで制御可能である。
The manufacturing method of the present invention skillfully utilizes the fact that the growth mode of selective growth changes depending on the growth temperature, and forms quantum wires only through the growth process, completely avoiding processing damage and contamination. Needless to say, the steepness of the lateral interface can also be controlled on the order of a single atom.

〔実施例〕〔Example〕

以下、材料としてA I!G a A s / G a
 A sを例にとって本発明の実施例について詳細に説
明する。
The following materials are AI! G a As / G a
Embodiments of the present invention will be described in detail by taking As as an example.

第3図は、本発明の方法によって作られた量子細線の基
本構造であり、量子細線は点線で囲まれた界面の部分に
存在する。
FIG. 3 shows the basic structure of a quantum wire produced by the method of the present invention, and the quantum wire exists in the interface portion surrounded by the dotted line.

第4図(al fbl (C)は、第3図の構造を作製
する手順(工程)を示しており、以下順次説明する。ま
ず、GaAs基板上に5iOz9をスパッタ法かCVD
法で堆積させ、(110)方向に長いストライプ状の開
口部を作る(第4図(a))。この基板上に有機金属気
相成長法を使って650℃の成長温度で7のノンドープ
Aj!GaAs 100nmを成長させた後、3のGa
Asと2のAj!GaAsを順次10nmの厚さで成長
させ多層構造を作製し、最後に8のノンドープAj!G
aAsを1100n成長させる。この時、第4図fbl
に示すように成長層は台形状になり、その台形の側壁に
はいっさい成長しない。次に、800℃の成長温度でこ
の台形状の多層構造の上に4のノンドープA7!GaA
SをlQnm成長させ、続いて5のSiドープA7!G
aAsによって台形の側面は有効に変調ドープされるが
、台形状多層膜の上面は1100nの8のAffiGa
Asがあるため上側界面に電子は存在しないので、台形
側面に一次元電子状態が実現できる0本実施例では高周
波加熱の横型炉を用い、減圧下で成長を行なった。原料
としてトリメチルガリウム、トリメチルアルミニウム、
アルシンを用いて、第4図(alで示した基板上に選択
成長させた。
FIG. 4 (C) shows the procedure (process) for producing the structure shown in FIG. 3, which will be explained in sequence below.
The film is deposited using a method to form long stripe-shaped openings in the (110) direction (FIG. 4(a)). Non-doped Aj! of 7 was grown on this substrate at a growth temperature of 650°C using metal organic vapor phase epitaxy. After growing 100 nm of GaAs, 3 Ga
As and 2 Aj! GaAs was sequentially grown to a thickness of 10 nm to fabricate a multilayer structure, and finally 8 non-doped Aj! G
Grow aAs to 1100n. At this time, Fig. 4 fbl
As shown in , the growth layer becomes trapezoidal, and no growth occurs on the sidewalls of the trapezoid. Next, at a growth temperature of 800°C, 4 non-doped A7! GaA
S is grown to lQnm, followed by 5 Si-doped A7! G
Although the sides of the trapezoid are effectively modulated and doped by aAs, the top surface of the trapezoidal multilayer film is 1100n of 8 AffiGa.
Since no electrons exist at the upper interface due to the presence of As, a one-dimensional electronic state can be realized on the side surfaces of the trapezoid.In this example, growth was performed under reduced pressure using a horizontal furnace with high frequency heating. Trimethyl gallium, trimethyl aluminum as raw materials,
Using arsine, selective growth was performed on the substrate shown in FIG. 4 (al).

また、類似の細線成長はAsatらによりAppj!i
ed  Physics  Letters51巻(1
987年)第1518−20頁に報告されているが、(
110)方向のストライブを用いてGaAs層のみを台
形上に成長した。単にGaAsをAj!GaAsで覆う
細線の場合はこの方向で良好な細線が得られた。しかし
、AffGaAs / Q a A S多層膜を台形上
に成長する場合は、(110)方向ストライブでは(1
10)方向と比較して良好な台形形状は得られない。へ
j!GaAs成長で[110)方向ストライプの場合は
55度傾いた(111) 8面が鏡面成長するが、〔1
10〕方向ストライプの場合では側面はほぼ(111)
A面になるが鏡面は得られない。従って、本発明の主要
な特徴は、(110)方向のストライブにより良好な多
層膜を成長したことにある。第5図には、このようにし
て作製した細線の一例として幅70nmの量子細線を示
す。なお斜めに界面に一次元電子が存在することは磁気
抵抗の653場方位依存性から6m認している。
Similar thin line growth was also reported by Asat et al. in Appj! i
ed Physics Letters Volume 51 (1
987), pp. 1518-20, but (
Only a GaAs layer was grown on a trapezoid using a stripe in the 110) direction. Simply Aj GaAs! In the case of a thin wire covered with GaAs, a good thin wire was obtained in this direction. However, when growing an AffGaAs/Q a A S multilayer film on a trapezoid, the (110) direction stripe requires (1
10) A good trapezoidal shape cannot be obtained compared to the direction. Hey! In the case of [110) direction stripes in GaAs growth, eight (111) planes tilted by 55 degrees grow mirror-like, but in the case of [110] direction stripes, the [110]
10] In the case of directional stripes, the sides are approximately (111)
It will be the A side, but you will not get a mirror finish. Therefore, the main feature of the present invention is that a good multilayer film can be grown by striping in the (110) direction. FIG. 5 shows a quantum wire with a width of 70 nm as an example of the thin wire produced in this manner. The existence of one-dimensional electrons obliquely at the interface is recognized from the 653 field orientation dependence of magnetoresistance.

以上説明したように、本実施例の作製方法によれば、す
べて成長工程だけで作製可能なので、エツチング汚染や
加工ダメージがなく、側面も単原子オーダで平坦な量子
細線となる。
As explained above, according to the manufacturing method of this embodiment, the entire quantum wire can be manufactured only by the growth process, so there is no etching contamination or processing damage, and the quantum wire has flat side surfaces on the order of monoatomic atoms.

本発明の実施例では、A j2 G a A s / 
G a A s糸材料で説明したが、Gaj!np/G
aAs、Ga l n A s / Rn pのm−v
族生導体及びその混晶系、Z n S e / G a
 A s等のII−Vl族半導体とその混晶系材料でも
実現できる。
In the embodiment of the present invention, A j2 G a A s /
I explained about G a As yarn material, but Gaj! np/G
aAs, GalnAs/Rnp m-v
Family conductors and their mixed crystal systems, Z n S e / G a
It can also be realized using II-Vl group semiconductors such as As and their mixed crystal materials.

〔発明の効果〕〔Effect of the invention〕

本発明の製造方法は、成長工程のみで量子細線を形成す
るものであるから、加工ダメージや汚染から完全に逃れ
ることはもちろんのこと横方向の界面の急峻性も単原子
オーダで制御可能である。
Since the manufacturing method of the present invention forms quantum wires only through the growth process, it is not only completely free from processing damage and contamination, but also the steepness of the lateral interface can be controlled to the monatomic order. .

本発明を用いることにより、従来のプレーナ型FETと
比較して高いトランスコンダクタンスをもつ一次FET
が得られた。
By using the present invention, a primary FET with a higher transconductance compared to a conventional planar FET can be realized.
was gotten.

第1図Figure 1

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来提案されている量子細線構造の断面図であ
り、第2図(al (bl (c+は従来提案されてい
る作製方法を説明する図である。第3図は本発明の方法
によって作られる量子細線の基本構造を示す。 第4図(al (bl (C1は、本発明の作製手順(
工程)を示す。第5図は7Qnm幅のπ子細線を示す。 1・・・半絶縁性GaAs法板、2,7.8・・・ノン
ドープAlGaAs成長層、3・・・ノンドープGaA
s成長層、4・・・ノンドープA I G a A s
 / G aAsスペーサ層、5 ・−3iドープAA
GaAs成長層、6・・・エツチングマスク、9・・・
選択成長マスク 特許出願人  日本電信電話株式会社 代理人 弁理士 玉 蟲 久五部 (外2名) 1・・・半i!8縁性GaAs基板 2・・・ノンドープAlGaAs成長層6・・ノンドー
プGaAs成長層 4・・・ノンドープA I GaAsスペーサ層5・・
・$1ドープ人lGaAs成長層従来提案されている−
次元量子細線 1 半絶縁性GaAs基板 従来の作製方法 第 図 1・・半絶縁性GaAs基板 2.7.8・・・ノンドープAlGaAs成長層3・・
・ノンドープGa A s成長層4・・・ノンドープA
lGaAsスペーサ層5・・・S1ド一プAlGaAs
成長層9・・・選択成長マスク
FIG. 1 is a cross-sectional view of a conventionally proposed quantum wire structure, and FIG. 2 is a diagram illustrating a conventionally proposed manufacturing method. The basic structure of the quantum wire made by
process). FIG. 5 shows a π-thin wire with a width of 7Q nm. 1... Semi-insulating GaAs method plate, 2,7.8... Non-doped AlGaAs growth layer, 3... Non-doped GaA
s growth layer, 4... non-doped AI Ga As
/GaAs spacer layer, 5·-3i doped AA
GaAs growth layer, 6... etching mask, 9...
Selective Growth Mask Patent Applicant Nippon Telegraph and Telephone Co., Ltd. Agent Patent Attorney Tama Mushi Kugobe (2 others) 1...half i! 8-edge GaAs substrate 2...Non-doped AlGaAs growth layer 6...Non-doped GaAs growth layer 4...Non-doped AI GaAs spacer layer 5...
・$1 doped GaAs growth layer has been proposed in the past.
Dimensional quantum wire 1 Conventional manufacturing method of semi-insulating GaAs substrate Fig. 1...Semi-insulating GaAs substrate 2.7.8...Non-doped AlGaAs growth layer 3...
・Non-doped Ga As growth layer 4...Non-doped A
lGaAs spacer layer 5...S1 doped AlGaAs
Growth layer 9...selective growth mask

Claims (2)

【特許請求の範囲】[Claims] (1)(001)化合物半導体基板面上に絶縁膜を堆積
し、〔110〕方向のストライプ状の開口部を形成した
後に、該半導体基板上に有機金属気相成長法を使つて、
750℃以下の成長温度で少なくとも2種類以上の低不
純物濃度の半導体を順次成長させて、ストライプを台形
状にしたのち、引き続き高不純物濃度の半導体を台形の
側面に成長させることを特徴とする半導体量子細線の製
造方法。
(1) After depositing an insulating film on the surface of a (001) compound semiconductor substrate and forming striped openings in the [110] direction, using metal organic vapor phase epitaxy on the semiconductor substrate,
A semiconductor characterized by sequentially growing at least two types of low impurity concentration semiconductors at a growth temperature of 750°C or lower to form a trapezoidal stripe, and then subsequently growing a high impurity concentration semiconductor on the sides of the trapezoid. Quantum wire manufacturing method.
(2)(001)化合物半導体基板面上に絶縁膜を堆積
し、〔110〕方向のストライプ状の開口部を形成した
後に、該半導体基板上に有機金属気相成長法を使つて、
750℃以下の成長温度で少なくとも2種類以上の低不
純物濃度の半導体を順次成長させて、ストライプを台形
状にしたのち、750℃以上の成長温度で低不純物濃度
の別の半導体を50ナノメータ以下の厚さで台形の側面
に成長させ、引き続き高不純物濃度の半導体を同側面に
成長させることを特徴とする前記特許請求の範囲第1項
記載の半導体量子細線の製造方法。
(2) After depositing an insulating film on the surface of the (001) compound semiconductor substrate and forming striped openings in the [110] direction, using metal organic vapor phase epitaxy on the semiconductor substrate,
At least two types of low impurity concentration semiconductors are sequentially grown at a growth temperature of 750°C or lower to form a trapezoidal stripe, and then another low impurity concentration semiconductor is grown at a growth temperature of 750°C or higher to a thickness of 50 nanometers or less. 2. The method of manufacturing a semiconductor quantum wire according to claim 1, wherein the semiconductor quantum wire is grown to a thickness on a side surface of a trapezoid, and then a semiconductor with a high impurity concentration is grown on the same side surface.
JP15180988A 1988-06-20 1988-06-20 Manufacture of semiconductor quantum wire Pending JPH023222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15180988A JPH023222A (en) 1988-06-20 1988-06-20 Manufacture of semiconductor quantum wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15180988A JPH023222A (en) 1988-06-20 1988-06-20 Manufacture of semiconductor quantum wire

Publications (1)

Publication Number Publication Date
JPH023222A true JPH023222A (en) 1990-01-08

Family

ID=15526783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15180988A Pending JPH023222A (en) 1988-06-20 1988-06-20 Manufacture of semiconductor quantum wire

Country Status (1)

Country Link
JP (1) JPH023222A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202290A (en) * 1991-12-02 1993-04-13 Martin Moskovits Process for manufacture of quantum dot and quantum wire semiconductors
US5367274A (en) * 1991-06-28 1994-11-22 Telefonaktiebolaget L M Ericsson Quantum wave guiding electronic switch
CN109192806A (en) * 2018-08-30 2019-01-11 武汉电信器件有限公司 A kind of photodetector and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367274A (en) * 1991-06-28 1994-11-22 Telefonaktiebolaget L M Ericsson Quantum wave guiding electronic switch
US5202290A (en) * 1991-12-02 1993-04-13 Martin Moskovits Process for manufacture of quantum dot and quantum wire semiconductors
CN109192806A (en) * 2018-08-30 2019-01-11 武汉电信器件有限公司 A kind of photodetector and preparation method thereof

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