JPH023180A - Mos transistor and non-volatile static ram using it - Google Patents

Abstract

PURPOSE:To attain high speed operation and to attain the non-volatile holding of data by constituting a memory cell to be composed of an FF, which uses a floating gate type MOS TR for a driver. CONSTITUTION:When the drain of one Q1 out of a pair of floating gate type MOSTe Q1 and Q2 is in H and the drain of the other Q2 is in an L condition, the drain of the TR Q1 is closed to 15V by the boosting of a power source voltage and the drain of the TR Q2 goes to be much lower. As a result, in the Q4, electron discharge is executed from a floating gate to the drain and in the Q2, electron is discharged from the drain to the floating gate. Thus, the Q1 goes to the condition of large driving ability and the Q2 goes to the condition of the small ability. The non-volatile storage of this condition change is executed even after a power source is turned off. When the power source is inputted again, the TR Q1 is turned on at first by the difference of the driving ability for the TR Q2. Namely, the automatic initial set is executed to the drain of the Q1 to L and the drain of the Q2 to H. Such a condition is reverse to a condition before the power source is turned off.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a MOS transistor having a floating gate and a non-volatile static RAM (SRAM) using the same.
Regarding.

(Prior Art) MOS transistors with floating gates are used in EEPROM memory cells and the like that hold data in a nonvolatile manner. In this type of EEPROM, data is written or erased by transferring charges between the substrate and the floating gate using a tunnel current through a gate insulating film. Due to this principle of operation, EEPROMs have slower write and erase speeds than, for example, SRAMs whose memory cells are flip-flops using ordinary MOS transistors.

Therefore, EEPROM is used to store the status of home appliances and various controllers, to store initial values of operating modes of personal computers, etc., but cannot be used for applications where rewriting is frequently performed.

On the other hand, since SRAM can be written to and read at high speed and has low power consumption, it is used as the main storage device of computers where data is frequently rewritten.

However, data in SRAM is lost when the power is turned off.

Therefore, if you want to retain data, it is necessary to rewrite the data in nonvolatile memory. There is also the problem that all written data will be erased in the event of a sudden power outage.

(Problem to be solved by the invention) As mentioned above, EEPRO can store data non-volatilely.
M has a slow operation speed and has limited uses.

Another problem is that SRAMs capable of high-speed operation cannot hold data in a non-volatile manner.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a MOS transistor that is optimal for constructing an SRAM that can operate at high speed and hold data in a nonvolatile manner.

The present invention also includes: It is an object of the present invention to provide a nonvolatile SRAM configured using such MOS transistors.

[Structure of the Invention] (Means for Solving the Problems) A MOS transistor according to the present invention is constructed by embedding a floating gate in a gate insulating film.

However, unlike floating gate MOS transistors used in conventional EEFROMs, etc., the floating gate partially covers the channel region in the channel width direction, and is arranged so as to be at least adjacent to the drain region in the channel length direction. be done. A tunnel insulating film is provided partially or entirely under the floating gate.

The nonvolatile SRAM according to the present invention uses a memory cell configured as a flip-flop using a pair of such floating gate MOS transistors as a driver, and injects charge into one of the floating gates according to data. It is characterized by being configured to hold data in a non-volatile manner.

The nonvolatile SRAM according to the present invention also includes: When using such a memory cell, take into account that the data will be inverted when writing non-volatile data.

The present invention is characterized in that a data inversion control circuit is provided at the input/output section of the memory cell array, and a nonvolatile binary counter flag circuit is provided to control these data inversion control circuits.

(Function) The floating gate MOS transistor according to the present invention changes its characteristics by transferring charge between the floating gate and the substrate using tunnel injection, and maintains the changed characteristics in a non-volatile manner. can do. In the case of a floating gate MOS transistor used in a normal EEPROM, the threshold value is greatly different between the state in which charge is injected into the floating gate and the state in which the charge is released. The difference between them is used as information. However, the floating gate type MOS of this EEFROM
Transistors have a large difference in threshold value and drive ability between the written state and the erased state, and these differences can be directly applied to S
If used as a RAM driver, normal operation as an SRAM will no longer be possible. Floating gate type MOS of the present invention
In a transistor structure, the floating gate only partially covers the channel region in the channel width direction, so depending on whether or not charge is injected into the floating gate, its driving ability can be changed with almost no change in the threshold value. I can do it.

Further, by appropriately setting the area covering the channel region of the floating gate, it is possible to appropriately set the difference in drive capability between the written state and the erased state. Therefore, such a floating gate type MOS transistor is used as a driver to configure a flip-flop, and this is used as a memory cell in the SR.
By configuring AM, it is possible to realize an SRAM that can hold data in a non-volatile manner without interfering with normal operation as an SRAM.

Furthermore, when the power is turned off, the SRAM according to the present invention injects charge into one floating gate of the driver MO8 transistor according to the data at that time.
Data can be held in a non-volatile manner while the power is turned off due to the difference in driving ability of the OS transistors. As aforementioned,
The threshold value of the driver MOS transistor hardly changes depending on the data write state (the drive capacity changes only appropriately), so it maintains the normal high-speed read and write state as an SRAM, and is non-volatile. can have.

By the way, in the SRAM of the present invention, when the power is turned off, one M
If charge is injected into the floating gate using an OS transistor and data is held in a non-volatile manner by lowering its driving capability, the data will be inverted when the power is turned on again. Specifically, if we consider an n-channel, for example, when the power supply voltage is increased, the drain is at the “L” level and the gate is at the “H” level.
- In a transistor, electrons are injected into the floating gate.

As a result, in this MOS transistor, the threshold value under the floating gate becomes high, but since the floating gate does not cover the entire channel region, the threshold value of the transistor as a whole does not change much, and the channel width is effectively narrowed. As a result, the driving ability decreases. When the power is turned on again, the drain voltage of the MOS transistor on the side where the driving ability has decreased is less likely to drop than that of the other MOS transistor, so it is initialized to a stable state that is opposite to the state before the power was turned off. become.

Therefore, in the SRAM of the present invention, a data inverting circuit is provided in the input/output section of the memory cell array, and a nonvolatile binary counter flag circuit is provided to control the circuit, and input/output data is inverted during rewriting, so that correct reading can be performed. ,
Writing will be performed.

(Example) Hereinafter, nine embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a floating gate MOS transistor. (a) shows a plan view.

(b) and (C) are AA' and BB' of (a), respectively.
A cross section is shown. An element isolation insulating film 2 is formed on a p-type SL substrate 1, and a gate electrode 6 is formed in a region surrounded by the element isolation insulating film 2 with a gate insulating film 5 interposed therebetween. An n+ type source and drain region 7 is self-aligned to this gate electrode 6.
．． 8 is formed. A floating gate 4 is embedded in the gate insulating space 5 so as to partially cover the channel region and partially extend over the element isolation region. That is, the floating gate 4 has a total channel width w, + in the channel width direction.
The pattern is formed so as to cover a portion of width W1 with respect to w2, and to cover a portion of channel length L1 with respect to the entire channel length L1+L2 in the channel length direction. However, the drain side end of the floating gate 4 is provided adjacent to the drain region 7. A thin tunnel insulating film 3 is formed on the channel region under the floating gate 4.

FIG. 2 shows the relationship between gate voltage Vg and drain current ID, which shows the characteristics of this floating gate type MOS transistor. As long as electrons are not injected into or emitted from the floating gate, it exhibits the characteristic of curve 1 (A).

This is the same as a normal MOS transistor.

Apply a high positive potential (eg 15v) to the gate.

When the source and drain are set to a low potential (for example, OV), electrons are injected into the floating gate 4 via the tunnel insulating film 3. As a result, the MOS transistor.

The threshold value under the floating gate 4 becomes high, the effective channel width decreases from W 1 + W 2 to W2, and the driving capability decreases. Therefore, the characteristics change as shown by curve (b). The threshold value of the MOS transistor as a whole hardly changes because the channel width W2 does not change. Next, when the gate and source are set to a low potential and a positive high potential is applied to the drain, electrons are emitted from the floating gate 4 to the drain, and the threshold voltage under the floating gate 4 decreases. As a result, the characteristics become as shown in curve (c). At this time, there is almost no change in the threshold value of the transistor as a whole.

Thus, in the MOS transistor of this embodiment.

The driving ability can be changed without changing the threshold voltage, and the state can be maintained in a non-volatile manner.

FIG. 3 shows a MOS transistor of another embodiment corresponding to FIG. 1. The difference from FIG. 1 is that, like the gate electrode 6, the floating gate 4 covers the entire channel region in the channel length direction.

FIG. 4 shows the characteristics of this MOS transistor in correspondence with FIG. 2. By injecting electrons into the floating gate 4, the characteristics change from curve 1 (a) to curve (b). At this time, there is almost no change in the threshold value. The process up to this point is the same as the previous embodiment. When the floating gate 4 performs an electron emission operation, the overall threshold value is determined by the low threshold value under the floating gate 4, so the threshold value moves in the negative direction, resulting in a characteristic like the curve (c). .

FIG. 5 shows a MOS transistor of yet another embodiment, corresponding to FIG. 1. In the previous two embodiments, the lower gold surface of the floating gate 4 is used as a tunnel insulating film, whereas in this embodiment.

A part of the floating gate 4 is made to protrude above the drain region 7, and a tunnel insulating film 9 is partially provided on the drain region 7. In this embodiment as well, the same characteristics as the MOS transistor shown in FIG. 1 can be obtained only by localizing the electron exchange region.

Next, an example will be described in which an SRAM is constructed using MOS transistors of the present invention as described above.

FIGS. 6 to 8 show two examples of memory cell configurations of the SRAM of the present invention. Figure 6 shows an E/
R type, FIG. 7 has a p-channel MO3I-transistor Q5. The CMO3 type using Q6, FIG. 8 shows a D-tie 1MO3 transistor Q7. It is an E/D type using Q8. In any of these memory cells.

A pair of driver MOS transistors Q1. Q2 is.

This is the floating gate type MOS transistor mentioned above.

Further, r Q 3 + 04 is a switching MOS transistor that connects the memory node to the bit line.

A specific example of a pattern of an SRAM memory cell is shown in FIG. This is an example of the E/D type mesememory cell combination shown in FIG. Here, the floating gate type driver MOS transistors Ql and Q2 have a structure in which the floating gate 4 partially extends from the gate electrode 6 toward the drain region side.

By integrating such memory cells, SRA
M is obtained. This SRAM is similar to normal SRAM,
Capable of high-speed reading and writing.

Since its operation is well known, its explanation will be omitted.

When the SRAM is powered off, the state of each memory cell at that time is stored in a non-volatile manner.

This is done by raising the supply voltage Vl) to a high voltage (eg 15V) with respect to the normal operating supply voltage (eg 5V). Specifically, for example, using the memory cell shown in FIG. 6, when the drain of one transistor Ql is at "H" level and the drain of the other transistor Q2 is at "L" level, the power supply voltage increases. As a result, the drain of transistor Q1 approaches 15V, and the drain of transistor Q2 changes to become lower. As a result, electrons are emitted from the floating gate to the drain of the transistor Q1, and electrons are injected from the drain to the floating gate of the transistor Q2. As a result, the transistor Q1 becomes in a state with a high driving ability (the state shown by the curve (c) in FIG. 2), and the transistor Q2 becomes in a state Wi where the driving ability is small (the state shown by the curve (b) in FIG. 2). As already explained, these state changes are stored in a non-volatile manner even after the power is turned off.

When the power is turned on again, transistor Q1. Due to the difference in driving ability of Q2, the former turns on first.

That is, the drain of the transistor Q1 is automatically initialized to the "L" level, and the drain of the transistor Q1 is automatically initialized to the "H0" level. This state is the opposite of the state before the power was turned off.

Note that any method may be used to raise the power supply voltage immediately before turning off the power, such as providing a booster circuit in conjunction with a power switch inside the SRAM or supplying power from the outside.

Furthermore, it is useful to provide an automatic power-off detection circuit so as to cope with sudden power outage accidents.

In this manner, the memory cell of the present invention can normally perform high-speed reading and writing, and can non-volatilely store the immediately preceding information when the power is turned off. Furthermore, by using a floating gate type MOS transistor with a special structure as a driver transistor, it is possible to obtain a nonvolatile SRAM with the same number of transistors as a normal SRAM. However, since the information stored in a non-volatile manner is reversed when the power is turned on again, an actual SRAM configuration requires a means to compensate for this.

FIG. 10 shows an example of the configuration of an SRAM of the present invention to which a circuit for compensating for data inversion is added. An input circuit 12 for the SRAM memory cell array 11. Output circuit 13. Input buffer 14. Output buffers 15 and the like are provided in the same way as usual. An input signal inversion control circuit 16 is provided between the input circuit 12 and the input buffer 14, and an output signal inversion control circuit 17 is provided between the output circuit 13 and the output buffer 15. These control circuits 16,17.

Controlled by binary counter flag circuit 18.

Switching between inversion and non-inversion is performed. In this embodiment, the flag circuit 18 is constituted by a flip-flop using a floating gate type MOS transistor as a driver like the memory cell, and is connected to the memory array 11.
It is a non-volatile binary counter in which non-volatile writing is performed at the same time when data is non-volatile written.

With such a configuration, when the power is turned off and the information at that time is stored in a non-volatile manner, when the power is turned on and the information is reproduced, all the information in the memory cell array 11 is inverted as described above. This is determined by the flag circuit 18, and the node N1 is at II HIT level.

The node N2 becomes "L" level, causing the inverting control circuit 17 in the output section to operate as an inverter. This allows correct information to be read. At this time, since the output signal is inverted, the inversion control circuit 16 in the input section is also operated as an inverter.
The original data is inverted and written to the memory cell array. 2
When the power is turned off and turned on again, the memory cell array 11
The information is reversed again and returned to the original state. Therefore, in this case, data inversion is not necessary for reading and writing. At this time, the state of the flag circuit 18 is also inverted, and the node N1 becomes the "Lm" level and the node N2 becomes the "H" level, so that the inversion control circuits 16 and 17 allow the input signal and output signal to pass through, respectively. .

Thus, according to the present invention, it is possible to obtain a nonvolatile SRAM that is equipped with a flag circuit for data inversion when information is held nonvolatilely when the power is turned off, and that enables normal operation. In particular, by using a non-volatile binary counter with the same configuration as a memory cell as a flag circuit,
This can be easily integrated onto a memory chip.

[Effects of the Invention] As described above, according to the present invention, it is possible to change the driving ability without substantially changing the threshold value, and it is also possible to store the changed driving ability in a non-volatile manner. A floating gate type MOS transistor can be obtained.

Furthermore, the present invention realizes an SRAM that is capable of high-speed reading and writing and that can store data in a non-volatile manner by configuring a memory cell consisting of a flip-flop using such a floating gate MOS transistor as a driver. be able to.

Furthermore, in such a nonvolatile SRAM, the present invention is equipped with a nonvolatile binary counter flag circuit and a data inversion control circuit to cope with the inversion of data in the memory cell array when the power is turned off and on. It is possible to realize an SRAM that enables this.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(c) are plan views showing the structure of one embodiment of the MOS transistor of the present invention, and their A-A' and B-
B' cross-sectional view, FIG. 2 is a diagram showing the characteristics of the MOS transistor, and FIGS. 3 (a) to (C) are plan views showing the MOS transistor structure of other embodiments, and their A-A' and B
-B' sectional view, Figure 4 is a diagram showing its characteristics, Figure 5 (a
) to (c) are plan views of other embodiments, and their AA' and BB' cross-sectional views 2. Figures 6 to 8 are SRAs of the present invention.
FIG. 3 is an equivalent circuit diagram showing an example of a memory cell configuration of M. FIG. 9 is a diagram showing an example of an SRAM memory cell pattern, and FIG. 10 is an equivalent circuit diagram showing the main part configuration of the SRAM of the present invention. 1...p-type Si substrate, 2... element isolation insulating film. 3.9...Tunnel insulating film, 4...Floating gate. 5... Gate insulating film, 6... Gate electrode, 7, 8...
...Drain, source region + Q 1r Q2...
・Driver MO3 transistor (floating gate type), 11
...Memory cell array, 12...Input circuit, 13.
...Output circuit, 14...Input buffer, 15...Output buffer. 16.17...Inversion control circuit, 18...Nonvolatile 2
Advance counter flag circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 1 Figure 4

Claims (3)

[Claims] (1) In a MOS transistor in which source and drain regions are formed at a predetermined interval on a semiconductor substrate, and a gate electrode is provided on a channel region between these source and drain regions with a gate insulating film interposed therebetween, the gate insulating film is To,
1. A MOS transistor characterized in that a floating gate is embedded at least adjacent to a drain region, partially covering a channel region in the channel width direction, and having a tunnel insulating film thereunder. (2) In a static RAM having a memory cell consisting of a flip-flop using a pair of MOS transistors as drivers, the pair of MOS transistors are arranged in a gate insulating film adjacent to at least a drain region and a channel region in a channel width direction. A floating gate is partially covered and has a tunnel insulating film buried thereunder, and the data is held in a non-volatile manner by injecting charge into one of the floating gates according to the data. Non-volatile static RAM featuring: (3) In a static RAM having a memory cell consisting of a flip-flop using a pair of MOS transistors as drivers, the pair of MOS transistors are arranged in a gate insulating film adjacent to at least a drain region and a channel region in a channel width direction. The floating gate is partially covered and has a tunnel insulating film buried thereunder, and the data is held in a non-volatile manner by injecting charge into one of the floating gates according to the data. A nonvolatile static RAM characterized in that a data inversion control circuit is provided at an input/output section of a cell array, and a nonvolatile binary counter flag circuit is provided for controlling the data inversion control circuit.