JPH02312238A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH02312238A
JPH02312238A JP13301689A JP13301689A JPH02312238A JP H02312238 A JPH02312238 A JP H02312238A JP 13301689 A JP13301689 A JP 13301689A JP 13301689 A JP13301689 A JP 13301689A JP H02312238 A JPH02312238 A JP H02312238A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
product
patterns
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13301689A
Other languages
Japanese (ja)
Inventor
Tooru Hokari
浦仮 透
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP13301689A priority Critical patent/JPH02312238A/en
Publication of JPH02312238A publication Critical patent/JPH02312238A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make possible the discrimination of the products of semiconductor integrated circuits clearly add simply and to dispense with high technicians by a method wherein patterns for discriminating the products are respectively formed on the surface of each semiconductor integrated circuit. CONSTITUTION:A pattern region 3 for discriminating a product is set at a position, where a region 1 constituting an electronic circuit does not overlap with bonding pad regions 2 in a semiconductor integrated circuit, or at a position which exerts no effect on the constitution of a real pattern within the region 1 and the regions 2. Moreover, in the process treatment of patterns 4 for discriminating the product, a process for clarifying the forms of the patterns is used and the patterns 4 are constituted of discriminable characters or graphic forms by the arrangement of a group of the characters or graphic forms. In such a way, as the patterns for discriminating the product are provided in the integrated circuit, the function and kind of the circuit are judged clearly and simply, high technicians become unnecessary and the flow of the product becomes possible correctly and in a short time.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は半導体集積回路のパターン形状に関する。[Detailed description of the invention] [Industrial application fields] The present invention relates to a pattern shape of a semiconductor integrated circuit.

[発明の概要コ 本発明は、半導体集積回路製造過程におけるプロセス処
理を行なった結果、半導体基板上に残るパターンとして
電子回路を構成するパターン以外に、製品を識別するパ
ターンを保有することにより、製品の内容、他製品との
区別を行なえる要素を盛り込み、製品判定に要する人的
能力の綴和を計ると同時に、判定時間の短縮によるコス
トダウンと、正確なプロセス流動による品質の向上を実
現したものである。
[Summary of the Invention] The present invention provides a process for manufacturing a semiconductor integrated circuit, in which a pattern remaining on a semiconductor substrate as a result of processing in the manufacturing process includes a pattern for identifying the product, in addition to the pattern constituting the electronic circuit. By incorporating elements that can differentiate products from other products, we have achieved a harmonious combination of human abilities required for product judgment, while at the same time reducing costs by shortening judgment time and improving quality by accurate process flow. It is something.

[従来の技術] 従来の半導体集積回路では、電子回路を構成するパター
ンのみ半導体基板上に存在していた。
[Prior Art] In a conventional semiconductor integrated circuit, only a pattern constituting an electronic circuit exists on a semiconductor substrate.

[発明が解決しようとする課M] しかし、前述の従来技術では、製品として半導体集積回
路を識別する場合、半導体基板上に構成された電子回路
の一部または、全部を認識することにより判定しなけれ
ばならず、半導体集積回路の製造及び製品化において正
確な流動を行なうために多くの判定時間と、回路認識を
行なえる高度な技術を有する人材の投入を要する等の問
題点を有する。
[Problem M to be solved by the invention] However, in the above-mentioned conventional technology, when identifying a semiconductor integrated circuit as a product, it is determined by recognizing part or all of the electronic circuit configured on the semiconductor substrate. However, there are problems in that it takes a lot of judgment time and requires the input of human resources with advanced technology for circuit recognition in order to carry out accurate flow in the manufacture and commercialization of semiconductor integrated circuits.

そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、製品仕保と一致した半導体集積
回路を短納期で提供するところにある。
SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide semiconductor integrated circuits that meet product specifications in a short delivery time.

[課題を解決するための手段] 本発明の半導体集積回路は、半導体基板上に残るパター
ンに、電子回路を構成するパターンだけでな(、製品と
しての識別を明確に行なえるパターンを加えることを特
徴とする。
[Means for Solving the Problems] The semiconductor integrated circuit of the present invention includes adding not only a pattern constituting an electronic circuit to a pattern remaining on a semiconductor substrate, but also a pattern that can be clearly identified as a product. Features.

[実施例] 第1図は本発明の1実施例を示す半導体集積回路の平面
図である。
[Embodiment] FIG. 1 is a plan view of a semiconductor integrated circuit showing one embodiment of the present invention.

1は半導体集積回路の電子回路を構成する領域、2は電
子回路の入出力用ポンディングパッドの領域、3は製品
を識別するためのパターン領域を示す。
Reference numeral 1 indicates an area constituting an electronic circuit of a semiconductor integrated circuit, 2 indicates an area of a bonding pad for input/output of the electronic circuit, and 3 indicates a pattern area for identifying a product.

第2図は、第1図の5の拡大図である。FIG. 2 is an enlarged view of 5 in FIG.

第1図に示す製品を識別するためのパターン領域は、半
導体集積回路における電子回路を構成する領域及び、ポ
ンディングパッド領域と重複しない位置、または、電子
回路を構成する領域及び、ポンディングパッド領域内の
実パターンの構成に影響しない位置に設定する。
The pattern area for identifying the product shown in FIG. 1 is located at a position that does not overlap with the area constituting the electronic circuit and the bonding pad area in the semiconductor integrated circuit, or the area constituting the electronic circuit and the bonding pad area. Set it in a position that does not affect the actual pattern structure within the pattern.

第2図に示す製品を識別するパターンは、プロセス処理
において形状が明確になる工程を用い、文字または、図
形群の配置配列により識別が可能となるものから構成さ
れる。
The pattern for identifying the product shown in FIG. 2 uses a step in which the shape becomes clear during processing, and is made up of characters or patterns that can be identified by the arrangement of a group of figures.

製品を識別するパターンを半導体集積回路内に有するこ
とにより、半導体集積回路の機能、種類が明確かつ簡単
に判断でき、高度な技術を有する人材を要することなく
、正確かつ短時間での製品流動が可能となる。
By having a pattern in the semiconductor integrated circuit that identifies the product, the function and type of the semiconductor integrated circuit can be determined clearly and easily, and products can be moved accurately and in a short time without requiring highly skilled personnel. It becomes possible.

[発明の効果] 以上述べたように本発明によれば、半導体集積回路の表
面に製品を識別するパターンを形成することにより、半
導体集積回路の製品識別を明確かつCゴI単に行なえる
こととなり、識別に要する時間の減少からくる納期短縮
ならびに、識別に従事する人材に高度な技術を必要とし
ない事から(る人件費削減による低コスト化が達成でき
るという効果を有する。
[Effects of the Invention] As described above, according to the present invention, by forming a pattern for identifying the product on the surface of the semiconductor integrated circuit, product identification of the semiconductor integrated circuit can be clearly and easily performed. This has the effect of shortening the delivery time due to the reduction in the time required for identification, and lowering costs due to the fact that the personnel engaged in identification does not require advanced technology (reducing personnel expenses).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体集積回路のデータ配置の一実施
例を示す平面図。 第2図は本発明の半導体集積回路における製品詔Ωパタ
ーンの一実施例を示す主要平面図。 1・・・・・・・・・半導体集積回路の電子回路を構成
する領域 2・・・・・・・・・電子回路の入出力用ポンディング
パッドの領域  ′ 3・・・・・・・・・製品を識別するパターンの領域4
・・・・・・・・・識別パターン 5・・・・・・・・・チップ 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜三部(他1名)第1図 第2図
FIG. 1 is a plan view showing an embodiment of data arrangement of a semiconductor integrated circuit according to the present invention. FIG. 2 is a main plan view showing an embodiment of the product Ω pattern in the semiconductor integrated circuit of the present invention. 1... Area that constitutes the electronic circuit of the semiconductor integrated circuit 2... Area of the input/output bonding pad of the electronic circuit ' 3... ...Pattern area 4 for identifying products
・・・・・・・・・Identification pattern 5・・・・・・・・・Chip and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 other person) Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路の製造過程におけるプロセス処理後パタ
ーン形状において、電子回路を構成するパターン以外に
、製品を識別するパターンを保有することを特徴とする
半導体集積回路。
A semiconductor integrated circuit characterized in that a pattern shape after processing in the manufacturing process of the semiconductor integrated circuit has a pattern for identifying a product in addition to a pattern constituting an electronic circuit.
JP13301689A 1989-05-26 1989-05-26 Semiconductor integrated circuit Pending JPH02312238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13301689A JPH02312238A (en) 1989-05-26 1989-05-26 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13301689A JPH02312238A (en) 1989-05-26 1989-05-26 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02312238A true JPH02312238A (en) 1990-12-27

Family

ID=15094827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13301689A Pending JPH02312238A (en) 1989-05-26 1989-05-26 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02312238A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5350715A (en) * 1991-11-12 1994-09-27 Samsung Electronics Co., Ltd. Chip identification scheme

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5350715A (en) * 1991-11-12 1994-09-27 Samsung Electronics Co., Ltd. Chip identification scheme

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